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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -o - %s | FileCheck %s3# Check that there is no assert on subregister uses.4 5---6name: vl_optimizer_subreg_assert7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $v8m211 12 ; CHECK-LABEL: name: vl_optimizer_subreg_assert13 ; CHECK: liveins: $v8m214 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF16 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vmv0 = IMPLICIT_DEF17 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vrm8 = IMPLICIT_DEF18 ; CHECK-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed [[DEF2]], [[DEF]], [[DEF1]], -1, 6 /* e64 */19 ; CHECK-NEXT: [[PseudoVREDMAXU_VS_M8_E64_:%[0-9]+]]:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, [[PseudoVMERGE_VVM_M8_]], [[PseudoVMERGE_VVM_M8_]].sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */20 ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAXU_VS_M8_E64_]], 6 /* e64 */21 ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]22 ; CHECK-NEXT: PseudoRET implicit $x1023 %0:vrm8 = IMPLICIT_DEF24 %1:vmv0 = IMPLICIT_DEF25 %2:vrm8 = IMPLICIT_DEF26 %3:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed %2, %0, %1, -1, 6 /* e64 */27 %4:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, %3, %3.sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */28 %5:gpr = PseudoVMV_X_S killed %4, 6 /* e64 */29 $x10 = COPY %530 PseudoRET implicit $x1031 32...33