1339 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i64> @intrinsic_vle_v_nxv1i64_nxv1i64(ptr %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11; CHECK-NEXT: vle64.v v8, (a0)12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64(15 <vscale x 1 x i64> poison,16 ptr %0,17 iXLen %1)18 19 ret <vscale x 1 x i64> %a20}21 22define <vscale x 1 x i64> @intrinsic_vle_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i64_nxv1i64:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu26; CHECK-NEXT: vle64.v v8, (a0), v0.t27; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(30 <vscale x 1 x i64> %0,31 ptr %1,32 <vscale x 1 x i1> %2,33 iXLen %3, iXLen 1)34 35 ret <vscale x 1 x i64> %a36}37 38define <vscale x 2 x i64> @intrinsic_vle_v_nxv2i64_nxv2i64(ptr %0, iXLen %1) nounwind {39; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma42; CHECK-NEXT: vle64.v v8, (a0)43; CHECK-NEXT: ret44entry:45 %a = call <vscale x 2 x i64> @llvm.riscv.vle.nxv2i64(46 <vscale x 2 x i64> poison,47 ptr %0,48 iXLen %1)49 50 ret <vscale x 2 x i64> %a51}52 53define <vscale x 2 x i64> @intrinsic_vle_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {54; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i64_nxv2i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu57; CHECK-NEXT: vle64.v v8, (a0), v0.t58; CHECK-NEXT: ret59entry:60 %a = call <vscale x 2 x i64> @llvm.riscv.vle.mask.nxv2i64(61 <vscale x 2 x i64> %0,62 ptr %1,63 <vscale x 2 x i1> %2,64 iXLen %3, iXLen 1)65 66 ret <vscale x 2 x i64> %a67}68 69define <vscale x 4 x i64> @intrinsic_vle_v_nxv4i64_nxv4i64(ptr %0, iXLen %1) nounwind {70; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma73; CHECK-NEXT: vle64.v v8, (a0)74; CHECK-NEXT: ret75entry:76 %a = call <vscale x 4 x i64> @llvm.riscv.vle.nxv4i64(77 <vscale x 4 x i64> poison,78 ptr %0,79 iXLen %1)80 81 ret <vscale x 4 x i64> %a82}83 84define <vscale x 4 x i64> @intrinsic_vle_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {85; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i64_nxv4i64:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu88; CHECK-NEXT: vle64.v v8, (a0), v0.t89; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x i64> @llvm.riscv.vle.mask.nxv4i64(92 <vscale x 4 x i64> %0,93 ptr %1,94 <vscale x 4 x i1> %2,95 iXLen %3, iXLen 1)96 97 ret <vscale x 4 x i64> %a98}99 100define <vscale x 8 x i64> @intrinsic_vle_v_nxv8i64_nxv8i64(ptr %0, iXLen %1) nounwind {101; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma104; CHECK-NEXT: vle64.v v8, (a0)105; CHECK-NEXT: ret106entry:107 %a = call <vscale x 8 x i64> @llvm.riscv.vle.nxv8i64(108 <vscale x 8 x i64> poison,109 ptr %0,110 iXLen %1)111 112 ret <vscale x 8 x i64> %a113}114 115define <vscale x 8 x i64> @intrinsic_vle_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {116; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i64_nxv8i64:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu119; CHECK-NEXT: vle64.v v8, (a0), v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 8 x i64> @llvm.riscv.vle.mask.nxv8i64(123 <vscale x 8 x i64> %0,124 ptr %1,125 <vscale x 8 x i1> %2,126 iXLen %3, iXLen 1)127 128 ret <vscale x 8 x i64> %a129}130 131define <vscale x 1 x double> @intrinsic_vle_v_nxv1f64_nxv1f64(ptr %0, iXLen %1) nounwind {132; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma135; CHECK-NEXT: vle64.v v8, (a0)136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 1 x double> @llvm.riscv.vle.nxv1f64(139 <vscale x 1 x double> poison,140 ptr %0,141 iXLen %1)142 143 ret <vscale x 1 x double> %a144}145 146define <vscale x 1 x double> @intrinsic_vle_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {147; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f64_nxv1f64:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu150; CHECK-NEXT: vle64.v v8, (a0), v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 1 x double> @llvm.riscv.vle.mask.nxv1f64(154 <vscale x 1 x double> %0,155 ptr %1,156 <vscale x 1 x i1> %2,157 iXLen %3, iXLen 1)158 159 ret <vscale x 1 x double> %a160}161 162define <vscale x 2 x double> @intrinsic_vle_v_nxv2f64_nxv2f64(ptr %0, iXLen %1) nounwind {163; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma166; CHECK-NEXT: vle64.v v8, (a0)167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 2 x double> @llvm.riscv.vle.nxv2f64(170 <vscale x 2 x double> poison,171 ptr %0,172 iXLen %1)173 174 ret <vscale x 2 x double> %a175}176 177define <vscale x 2 x double> @intrinsic_vle_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f64_nxv2f64:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu181; CHECK-NEXT: vle64.v v8, (a0), v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 2 x double> @llvm.riscv.vle.mask.nxv2f64(185 <vscale x 2 x double> %0,186 ptr %1,187 <vscale x 2 x i1> %2,188 iXLen %3, iXLen 1)189 190 ret <vscale x 2 x double> %a191}192 193define <vscale x 4 x double> @intrinsic_vle_v_nxv4f64_nxv4f64(ptr %0, iXLen %1) nounwind {194; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma197; CHECK-NEXT: vle64.v v8, (a0)198; CHECK-NEXT: ret199entry:200 %a = call <vscale x 4 x double> @llvm.riscv.vle.nxv4f64(201 <vscale x 4 x double> poison,202 ptr %0,203 iXLen %1)204 205 ret <vscale x 4 x double> %a206}207 208define <vscale x 4 x double> @intrinsic_vle_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {209; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f64_nxv4f64:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu212; CHECK-NEXT: vle64.v v8, (a0), v0.t213; CHECK-NEXT: ret214entry:215 %a = call <vscale x 4 x double> @llvm.riscv.vle.mask.nxv4f64(216 <vscale x 4 x double> %0,217 ptr %1,218 <vscale x 4 x i1> %2,219 iXLen %3, iXLen 1)220 221 ret <vscale x 4 x double> %a222}223 224define <vscale x 8 x double> @intrinsic_vle_v_nxv8f64_nxv8f64(ptr %0, iXLen %1) nounwind {225; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma228; CHECK-NEXT: vle64.v v8, (a0)229; CHECK-NEXT: ret230entry:231 %a = call <vscale x 8 x double> @llvm.riscv.vle.nxv8f64(232 <vscale x 8 x double> poison,233 ptr %0,234 iXLen %1)235 236 ret <vscale x 8 x double> %a237}238 239define <vscale x 8 x double> @intrinsic_vle_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {240; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f64_nxv8f64:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu243; CHECK-NEXT: vle64.v v8, (a0), v0.t244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 8 x double> @llvm.riscv.vle.mask.nxv8f64(247 <vscale x 8 x double> %0,248 ptr %1,249 <vscale x 8 x i1> %2,250 iXLen %3, iXLen 1)251 252 ret <vscale x 8 x double> %a253}254 255define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(ptr %0, iXLen %1) nounwind {256; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma259; CHECK-NEXT: vle32.v v8, (a0)260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(263 <vscale x 1 x i32> poison,264 ptr %0,265 iXLen %1)266 267 ret <vscale x 1 x i32> %a268}269 270define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {271; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu274; CHECK-NEXT: vle32.v v8, (a0), v0.t275; CHECK-NEXT: ret276entry:277 %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(278 <vscale x 1 x i32> %0,279 ptr %1,280 <vscale x 1 x i1> %2,281 iXLen %3, iXLen 1)282 283 ret <vscale x 1 x i32> %a284}285 286define <vscale x 2 x i32> @intrinsic_vle_v_nxv2i32_nxv2i32(ptr %0, iXLen %1) nounwind {287; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma290; CHECK-NEXT: vle32.v v8, (a0)291; CHECK-NEXT: ret292entry:293 %a = call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32(294 <vscale x 2 x i32> poison,295 ptr %0,296 iXLen %1)297 298 ret <vscale x 2 x i32> %a299}300 301define <vscale x 2 x i32> @intrinsic_vle_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {302; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32:303; CHECK: # %bb.0: # %entry304; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu305; CHECK-NEXT: vle32.v v8, (a0), v0.t306; CHECK-NEXT: ret307entry:308 %a = call <vscale x 2 x i32> @llvm.riscv.vle.mask.nxv2i32(309 <vscale x 2 x i32> %0,310 ptr %1,311 <vscale x 2 x i1> %2,312 iXLen %3, iXLen 1)313 314 ret <vscale x 2 x i32> %a315}316 317define <vscale x 4 x i32> @intrinsic_vle_v_nxv4i32_nxv4i32(ptr %0, iXLen %1) nounwind {318; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma321; CHECK-NEXT: vle32.v v8, (a0)322; CHECK-NEXT: ret323entry:324 %a = call <vscale x 4 x i32> @llvm.riscv.vle.nxv4i32(325 <vscale x 4 x i32> poison,326 ptr %0,327 iXLen %1)328 329 ret <vscale x 4 x i32> %a330}331 332define <vscale x 4 x i32> @intrinsic_vle_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {333; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu336; CHECK-NEXT: vle32.v v8, (a0), v0.t337; CHECK-NEXT: ret338entry:339 %a = call <vscale x 4 x i32> @llvm.riscv.vle.mask.nxv4i32(340 <vscale x 4 x i32> %0,341 ptr %1,342 <vscale x 4 x i1> %2,343 iXLen %3, iXLen 1)344 345 ret <vscale x 4 x i32> %a346}347 348define <vscale x 8 x i32> @intrinsic_vle_v_nxv8i32_nxv8i32(ptr %0, iXLen %1) nounwind {349; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma352; CHECK-NEXT: vle32.v v8, (a0)353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 8 x i32> @llvm.riscv.vle.nxv8i32(356 <vscale x 8 x i32> poison,357 ptr %0,358 iXLen %1)359 360 ret <vscale x 8 x i32> %a361}362 363define <vscale x 8 x i32> @intrinsic_vle_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {364; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32:365; CHECK: # %bb.0: # %entry366; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu367; CHECK-NEXT: vle32.v v8, (a0), v0.t368; CHECK-NEXT: ret369entry:370 %a = call <vscale x 8 x i32> @llvm.riscv.vle.mask.nxv8i32(371 <vscale x 8 x i32> %0,372 ptr %1,373 <vscale x 8 x i1> %2,374 iXLen %3, iXLen 1)375 376 ret <vscale x 8 x i32> %a377}378 379define <vscale x 16 x i32> @intrinsic_vle_v_nxv16i32_nxv16i32(ptr %0, iXLen %1) nounwind {380; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma383; CHECK-NEXT: vle32.v v8, (a0)384; CHECK-NEXT: ret385entry:386 %a = call <vscale x 16 x i32> @llvm.riscv.vle.nxv16i32(387 <vscale x 16 x i32> poison,388 ptr %0,389 iXLen %1)390 391 ret <vscale x 16 x i32> %a392}393 394define <vscale x 16 x i32> @intrinsic_vle_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {395; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32:396; CHECK: # %bb.0: # %entry397; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu398; CHECK-NEXT: vle32.v v8, (a0), v0.t399; CHECK-NEXT: ret400entry:401 %a = call <vscale x 16 x i32> @llvm.riscv.vle.mask.nxv16i32(402 <vscale x 16 x i32> %0,403 ptr %1,404 <vscale x 16 x i1> %2,405 iXLen %3, iXLen 1)406 407 ret <vscale x 16 x i32> %a408}409 410define <vscale x 1 x float> @intrinsic_vle_v_nxv1f32_nxv1f32(ptr %0, iXLen %1) nounwind {411; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma414; CHECK-NEXT: vle32.v v8, (a0)415; CHECK-NEXT: ret416entry:417 %a = call <vscale x 1 x float> @llvm.riscv.vle.nxv1f32(418 <vscale x 1 x float> poison,419 ptr %0,420 iXLen %1)421 422 ret <vscale x 1 x float> %a423}424 425define <vscale x 1 x float> @intrinsic_vle_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {426; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu429; CHECK-NEXT: vle32.v v8, (a0), v0.t430; CHECK-NEXT: ret431entry:432 %a = call <vscale x 1 x float> @llvm.riscv.vle.mask.nxv1f32(433 <vscale x 1 x float> %0,434 ptr %1,435 <vscale x 1 x i1> %2,436 iXLen %3, iXLen 1)437 438 ret <vscale x 1 x float> %a439}440 441define <vscale x 2 x float> @intrinsic_vle_v_nxv2f32_nxv2f32(ptr %0, iXLen %1) nounwind {442; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32:443; CHECK: # %bb.0: # %entry444; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma445; CHECK-NEXT: vle32.v v8, (a0)446; CHECK-NEXT: ret447entry:448 %a = call <vscale x 2 x float> @llvm.riscv.vle.nxv2f32(449 <vscale x 2 x float> poison,450 ptr %0,451 iXLen %1)452 453 ret <vscale x 2 x float> %a454}455 456define <vscale x 2 x float> @intrinsic_vle_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {457; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu460; CHECK-NEXT: vle32.v v8, (a0), v0.t461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 2 x float> @llvm.riscv.vle.mask.nxv2f32(464 <vscale x 2 x float> %0,465 ptr %1,466 <vscale x 2 x i1> %2,467 iXLen %3, iXLen 1)468 469 ret <vscale x 2 x float> %a470}471 472define <vscale x 4 x float> @intrinsic_vle_v_nxv4f32_nxv4f32(ptr %0, iXLen %1) nounwind {473; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma476; CHECK-NEXT: vle32.v v8, (a0)477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 4 x float> @llvm.riscv.vle.nxv4f32(480 <vscale x 4 x float> poison,481 ptr %0,482 iXLen %1)483 484 ret <vscale x 4 x float> %a485}486 487define <vscale x 4 x float> @intrinsic_vle_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {488; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu491; CHECK-NEXT: vle32.v v8, (a0), v0.t492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 4 x float> @llvm.riscv.vle.mask.nxv4f32(495 <vscale x 4 x float> %0,496 ptr %1,497 <vscale x 4 x i1> %2,498 iXLen %3, iXLen 1)499 500 ret <vscale x 4 x float> %a501}502 503define <vscale x 8 x float> @intrinsic_vle_v_nxv8f32_nxv8f32(ptr %0, iXLen %1) nounwind {504; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma507; CHECK-NEXT: vle32.v v8, (a0)508; CHECK-NEXT: ret509entry:510 %a = call <vscale x 8 x float> @llvm.riscv.vle.nxv8f32(511 <vscale x 8 x float> poison,512 ptr %0,513 iXLen %1)514 515 ret <vscale x 8 x float> %a516}517 518define <vscale x 8 x float> @intrinsic_vle_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {519; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu522; CHECK-NEXT: vle32.v v8, (a0), v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 8 x float> @llvm.riscv.vle.mask.nxv8f32(526 <vscale x 8 x float> %0,527 ptr %1,528 <vscale x 8 x i1> %2,529 iXLen %3, iXLen 1)530 531 ret <vscale x 8 x float> %a532}533 534define <vscale x 16 x float> @intrinsic_vle_v_nxv16f32_nxv16f32(ptr %0, iXLen %1) nounwind {535; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma538; CHECK-NEXT: vle32.v v8, (a0)539; CHECK-NEXT: ret540entry:541 %a = call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32(542 <vscale x 16 x float> poison,543 ptr %0,544 iXLen %1)545 546 ret <vscale x 16 x float> %a547}548 549define <vscale x 16 x float> @intrinsic_vle_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {550; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32:551; CHECK: # %bb.0: # %entry552; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu553; CHECK-NEXT: vle32.v v8, (a0), v0.t554; CHECK-NEXT: ret555entry:556 %a = call <vscale x 16 x float> @llvm.riscv.vle.mask.nxv16f32(557 <vscale x 16 x float> %0,558 ptr %1,559 <vscale x 16 x i1> %2,560 iXLen %3, iXLen 1)561 562 ret <vscale x 16 x float> %a563}564 565define <vscale x 1 x i16> @intrinsic_vle_v_nxv1i16_nxv1i16(ptr %0, iXLen %1) nounwind {566; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16:567; CHECK: # %bb.0: # %entry568; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma569; CHECK-NEXT: vle16.v v8, (a0)570; CHECK-NEXT: ret571entry:572 %a = call <vscale x 1 x i16> @llvm.riscv.vle.nxv1i16(573 <vscale x 1 x i16> poison,574 ptr %0,575 iXLen %1)576 577 ret <vscale x 1 x i16> %a578}579 580define <vscale x 1 x i16> @intrinsic_vle_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {581; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu584; CHECK-NEXT: vle16.v v8, (a0), v0.t585; CHECK-NEXT: ret586entry:587 %a = call <vscale x 1 x i16> @llvm.riscv.vle.mask.nxv1i16(588 <vscale x 1 x i16> %0,589 ptr %1,590 <vscale x 1 x i1> %2,591 iXLen %3, iXLen 1)592 593 ret <vscale x 1 x i16> %a594}595 596define <vscale x 2 x i16> @intrinsic_vle_v_nxv2i16_nxv2i16(ptr %0, iXLen %1) nounwind {597; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16:598; CHECK: # %bb.0: # %entry599; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma600; CHECK-NEXT: vle16.v v8, (a0)601; CHECK-NEXT: ret602entry:603 %a = call <vscale x 2 x i16> @llvm.riscv.vle.nxv2i16(604 <vscale x 2 x i16> poison,605 ptr %0,606 iXLen %1)607 608 ret <vscale x 2 x i16> %a609}610 611define <vscale x 2 x i16> @intrinsic_vle_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {612; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16:613; CHECK: # %bb.0: # %entry614; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu615; CHECK-NEXT: vle16.v v8, (a0), v0.t616; CHECK-NEXT: ret617entry:618 %a = call <vscale x 2 x i16> @llvm.riscv.vle.mask.nxv2i16(619 <vscale x 2 x i16> %0,620 ptr %1,621 <vscale x 2 x i1> %2,622 iXLen %3, iXLen 1)623 624 ret <vscale x 2 x i16> %a625}626 627define <vscale x 4 x i16> @intrinsic_vle_v_nxv4i16_nxv4i16(ptr %0, iXLen %1) nounwind {628; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16:629; CHECK: # %bb.0: # %entry630; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma631; CHECK-NEXT: vle16.v v8, (a0)632; CHECK-NEXT: ret633entry:634 %a = call <vscale x 4 x i16> @llvm.riscv.vle.nxv4i16(635 <vscale x 4 x i16> poison,636 ptr %0,637 iXLen %1)638 639 ret <vscale x 4 x i16> %a640}641 642define <vscale x 4 x i16> @intrinsic_vle_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {643; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16:644; CHECK: # %bb.0: # %entry645; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu646; CHECK-NEXT: vle16.v v8, (a0), v0.t647; CHECK-NEXT: ret648entry:649 %a = call <vscale x 4 x i16> @llvm.riscv.vle.mask.nxv4i16(650 <vscale x 4 x i16> %0,651 ptr %1,652 <vscale x 4 x i1> %2,653 iXLen %3, iXLen 1)654 655 ret <vscale x 4 x i16> %a656}657 658define <vscale x 8 x i16> @intrinsic_vle_v_nxv8i16_nxv8i16(ptr %0, iXLen %1) nounwind {659; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16:660; CHECK: # %bb.0: # %entry661; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma662; CHECK-NEXT: vle16.v v8, (a0)663; CHECK-NEXT: ret664entry:665 %a = call <vscale x 8 x i16> @llvm.riscv.vle.nxv8i16(666 <vscale x 8 x i16> poison,667 ptr %0,668 iXLen %1)669 670 ret <vscale x 8 x i16> %a671}672 673define <vscale x 8 x i16> @intrinsic_vle_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {674; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16:675; CHECK: # %bb.0: # %entry676; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu677; CHECK-NEXT: vle16.v v8, (a0), v0.t678; CHECK-NEXT: ret679entry:680 %a = call <vscale x 8 x i16> @llvm.riscv.vle.mask.nxv8i16(681 <vscale x 8 x i16> %0,682 ptr %1,683 <vscale x 8 x i1> %2,684 iXLen %3, iXLen 1)685 686 ret <vscale x 8 x i16> %a687}688 689define <vscale x 16 x i16> @intrinsic_vle_v_nxv16i16_nxv16i16(ptr %0, iXLen %1) nounwind {690; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16:691; CHECK: # %bb.0: # %entry692; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma693; CHECK-NEXT: vle16.v v8, (a0)694; CHECK-NEXT: ret695entry:696 %a = call <vscale x 16 x i16> @llvm.riscv.vle.nxv16i16(697 <vscale x 16 x i16> poison,698 ptr %0,699 iXLen %1)700 701 ret <vscale x 16 x i16> %a702}703 704define <vscale x 16 x i16> @intrinsic_vle_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {705; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16:706; CHECK: # %bb.0: # %entry707; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu708; CHECK-NEXT: vle16.v v8, (a0), v0.t709; CHECK-NEXT: ret710entry:711 %a = call <vscale x 16 x i16> @llvm.riscv.vle.mask.nxv16i16(712 <vscale x 16 x i16> %0,713 ptr %1,714 <vscale x 16 x i1> %2,715 iXLen %3, iXLen 1)716 717 ret <vscale x 16 x i16> %a718}719 720define <vscale x 32 x i16> @intrinsic_vle_v_nxv32i16_nxv32i16(ptr %0, iXLen %1) nounwind {721; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16:722; CHECK: # %bb.0: # %entry723; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma724; CHECK-NEXT: vle16.v v8, (a0)725; CHECK-NEXT: ret726entry:727 %a = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16(728 <vscale x 32 x i16> poison,729 ptr %0,730 iXLen %1)731 732 ret <vscale x 32 x i16> %a733}734 735define <vscale x 32 x i16> @intrinsic_vle_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {736; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16:737; CHECK: # %bb.0: # %entry738; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu739; CHECK-NEXT: vle16.v v8, (a0), v0.t740; CHECK-NEXT: ret741entry:742 %a = call <vscale x 32 x i16> @llvm.riscv.vle.mask.nxv32i16(743 <vscale x 32 x i16> %0,744 ptr %1,745 <vscale x 32 x i1> %2,746 iXLen %3, iXLen 1)747 748 ret <vscale x 32 x i16> %a749}750 751define <vscale x 1 x half> @intrinsic_vle_v_nxv1f16_nxv1f16(ptr %0, iXLen %1) nounwind {752; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16:753; CHECK: # %bb.0: # %entry754; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma755; CHECK-NEXT: vle16.v v8, (a0)756; CHECK-NEXT: ret757entry:758 %a = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16(759 <vscale x 1 x half> poison,760 ptr %0,761 iXLen %1)762 763 ret <vscale x 1 x half> %a764}765 766define <vscale x 1 x half> @intrinsic_vle_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {767; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu770; CHECK-NEXT: vle16.v v8, (a0), v0.t771; CHECK-NEXT: ret772entry:773 %a = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16(774 <vscale x 1 x half> %0,775 ptr %1,776 <vscale x 1 x i1> %2,777 iXLen %3, iXLen 1)778 779 ret <vscale x 1 x half> %a780}781 782define <vscale x 2 x half> @intrinsic_vle_v_nxv2f16_nxv2f16(ptr %0, iXLen %1) nounwind {783; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma786; CHECK-NEXT: vle16.v v8, (a0)787; CHECK-NEXT: ret788entry:789 %a = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16(790 <vscale x 2 x half> poison,791 ptr %0,792 iXLen %1)793 794 ret <vscale x 2 x half> %a795}796 797define <vscale x 2 x half> @intrinsic_vle_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {798; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16:799; CHECK: # %bb.0: # %entry800; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu801; CHECK-NEXT: vle16.v v8, (a0), v0.t802; CHECK-NEXT: ret803entry:804 %a = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16(805 <vscale x 2 x half> %0,806 ptr %1,807 <vscale x 2 x i1> %2,808 iXLen %3, iXLen 1)809 810 ret <vscale x 2 x half> %a811}812 813define <vscale x 4 x half> @intrinsic_vle_v_nxv4f16_nxv4f16(ptr %0, iXLen %1) nounwind {814; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16:815; CHECK: # %bb.0: # %entry816; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma817; CHECK-NEXT: vle16.v v8, (a0)818; CHECK-NEXT: ret819entry:820 %a = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16(821 <vscale x 4 x half> poison,822 ptr %0,823 iXLen %1)824 825 ret <vscale x 4 x half> %a826}827 828define <vscale x 4 x half> @intrinsic_vle_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {829; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16:830; CHECK: # %bb.0: # %entry831; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu832; CHECK-NEXT: vle16.v v8, (a0), v0.t833; CHECK-NEXT: ret834entry:835 %a = call <vscale x 4 x half> @llvm.riscv.vle.mask.nxv4f16(836 <vscale x 4 x half> %0,837 ptr %1,838 <vscale x 4 x i1> %2,839 iXLen %3, iXLen 1)840 841 ret <vscale x 4 x half> %a842}843 844define <vscale x 8 x half> @intrinsic_vle_v_nxv8f16_nxv8f16(ptr %0, iXLen %1) nounwind {845; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16:846; CHECK: # %bb.0: # %entry847; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma848; CHECK-NEXT: vle16.v v8, (a0)849; CHECK-NEXT: ret850entry:851 %a = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16(852 <vscale x 8 x half> poison,853 ptr %0,854 iXLen %1)855 856 ret <vscale x 8 x half> %a857}858 859define <vscale x 8 x half> @intrinsic_vle_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {860; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16:861; CHECK: # %bb.0: # %entry862; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu863; CHECK-NEXT: vle16.v v8, (a0), v0.t864; CHECK-NEXT: ret865entry:866 %a = call <vscale x 8 x half> @llvm.riscv.vle.mask.nxv8f16(867 <vscale x 8 x half> %0,868 ptr %1,869 <vscale x 8 x i1> %2,870 iXLen %3, iXLen 1)871 872 ret <vscale x 8 x half> %a873}874 875define <vscale x 16 x half> @intrinsic_vle_v_nxv16f16_nxv16f16(ptr %0, iXLen %1) nounwind {876; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16:877; CHECK: # %bb.0: # %entry878; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma879; CHECK-NEXT: vle16.v v8, (a0)880; CHECK-NEXT: ret881entry:882 %a = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16(883 <vscale x 16 x half> poison,884 ptr %0,885 iXLen %1)886 887 ret <vscale x 16 x half> %a888}889 890define <vscale x 16 x half> @intrinsic_vle_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {891; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16:892; CHECK: # %bb.0: # %entry893; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu894; CHECK-NEXT: vle16.v v8, (a0), v0.t895; CHECK-NEXT: ret896entry:897 %a = call <vscale x 16 x half> @llvm.riscv.vle.mask.nxv16f16(898 <vscale x 16 x half> %0,899 ptr %1,900 <vscale x 16 x i1> %2,901 iXLen %3, iXLen 1)902 903 ret <vscale x 16 x half> %a904}905 906define <vscale x 32 x half> @intrinsic_vle_v_nxv32f16_nxv32f16(ptr %0, iXLen %1) nounwind {907; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16:908; CHECK: # %bb.0: # %entry909; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma910; CHECK-NEXT: vle16.v v8, (a0)911; CHECK-NEXT: ret912entry:913 %a = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16(914 <vscale x 32 x half> poison,915 ptr %0,916 iXLen %1)917 918 ret <vscale x 32 x half> %a919}920 921define <vscale x 32 x half> @intrinsic_vle_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {922; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16:923; CHECK: # %bb.0: # %entry924; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu925; CHECK-NEXT: vle16.v v8, (a0), v0.t926; CHECK-NEXT: ret927entry:928 %a = call <vscale x 32 x half> @llvm.riscv.vle.mask.nxv32f16(929 <vscale x 32 x half> %0,930 ptr %1,931 <vscale x 32 x i1> %2,932 iXLen %3, iXLen 1)933 934 ret <vscale x 32 x half> %a935}936 937define <vscale x 1 x bfloat> @intrinsic_vle_v_nxv1bf16_nxv1bf16(ptr %0, iXLen %1) nounwind {938; CHECK-LABEL: intrinsic_vle_v_nxv1bf16_nxv1bf16:939; CHECK: # %bb.0: # %entry940; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma941; CHECK-NEXT: vle16.v v8, (a0)942; CHECK-NEXT: ret943entry:944 %a = call <vscale x 1 x bfloat> @llvm.riscv.vle.nxv1bf16(945 <vscale x 1 x bfloat> poison,946 ptr %0,947 iXLen %1)948 949 ret <vscale x 1 x bfloat> %a950}951 952define <vscale x 1 x bfloat> @intrinsic_vle_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {953; CHECK-LABEL: intrinsic_vle_mask_v_nxv1bf16_nxv1bf16:954; CHECK: # %bb.0: # %entry955; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu956; CHECK-NEXT: vle16.v v8, (a0), v0.t957; CHECK-NEXT: ret958entry:959 %a = call <vscale x 1 x bfloat> @llvm.riscv.vle.mask.nxv1bf16(960 <vscale x 1 x bfloat> %0,961 ptr %1,962 <vscale x 1 x i1> %2,963 iXLen %3, iXLen 1)964 965 ret <vscale x 1 x bfloat> %a966}967 968define <vscale x 2 x bfloat> @intrinsic_vle_v_nxv2bf16_nxv2bf16(ptr %0, iXLen %1) nounwind {969; CHECK-LABEL: intrinsic_vle_v_nxv2bf16_nxv2bf16:970; CHECK: # %bb.0: # %entry971; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma972; CHECK-NEXT: vle16.v v8, (a0)973; CHECK-NEXT: ret974entry:975 %a = call <vscale x 2 x bfloat> @llvm.riscv.vle.nxv2bf16(976 <vscale x 2 x bfloat> poison,977 ptr %0,978 iXLen %1)979 980 ret <vscale x 2 x bfloat> %a981}982 983define <vscale x 2 x bfloat> @intrinsic_vle_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {984; CHECK-LABEL: intrinsic_vle_mask_v_nxv2bf16_nxv2bf16:985; CHECK: # %bb.0: # %entry986; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu987; CHECK-NEXT: vle16.v v8, (a0), v0.t988; CHECK-NEXT: ret989entry:990 %a = call <vscale x 2 x bfloat> @llvm.riscv.vle.mask.nxv2bf16(991 <vscale x 2 x bfloat> %0,992 ptr %1,993 <vscale x 2 x i1> %2,994 iXLen %3, iXLen 1)995 996 ret <vscale x 2 x bfloat> %a997}998 999define <vscale x 4 x bfloat> @intrinsic_vle_v_nxv4bf16_nxv4bf16(ptr %0, iXLen %1) nounwind {1000; CHECK-LABEL: intrinsic_vle_v_nxv4bf16_nxv4bf16:1001; CHECK: # %bb.0: # %entry1002; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1003; CHECK-NEXT: vle16.v v8, (a0)1004; CHECK-NEXT: ret1005entry:1006 %a = call <vscale x 4 x bfloat> @llvm.riscv.vle.nxv4bf16(1007 <vscale x 4 x bfloat> poison,1008 ptr %0,1009 iXLen %1)1010 1011 ret <vscale x 4 x bfloat> %a1012}1013 1014define <vscale x 4 x bfloat> @intrinsic_vle_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1015; CHECK-LABEL: intrinsic_vle_mask_v_nxv4bf16_nxv4bf16:1016; CHECK: # %bb.0: # %entry1017; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1018; CHECK-NEXT: vle16.v v8, (a0), v0.t1019; CHECK-NEXT: ret1020entry:1021 %a = call <vscale x 4 x bfloat> @llvm.riscv.vle.mask.nxv4bf16(1022 <vscale x 4 x bfloat> %0,1023 ptr %1,1024 <vscale x 4 x i1> %2,1025 iXLen %3, iXLen 1)1026 1027 ret <vscale x 4 x bfloat> %a1028}1029 1030define <vscale x 8 x bfloat> @intrinsic_vle_v_nxv8bf16_nxv8bf16(ptr %0, iXLen %1) nounwind {1031; CHECK-LABEL: intrinsic_vle_v_nxv8bf16_nxv8bf16:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1034; CHECK-NEXT: vle16.v v8, (a0)1035; CHECK-NEXT: ret1036entry:1037 %a = call <vscale x 8 x bfloat> @llvm.riscv.vle.nxv8bf16(1038 <vscale x 8 x bfloat> poison,1039 ptr %0,1040 iXLen %1)1041 1042 ret <vscale x 8 x bfloat> %a1043}1044 1045define <vscale x 8 x bfloat> @intrinsic_vle_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1046; CHECK-LABEL: intrinsic_vle_mask_v_nxv8bf16_nxv8bf16:1047; CHECK: # %bb.0: # %entry1048; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1049; CHECK-NEXT: vle16.v v8, (a0), v0.t1050; CHECK-NEXT: ret1051entry:1052 %a = call <vscale x 8 x bfloat> @llvm.riscv.vle.mask.nxv8bf16(1053 <vscale x 8 x bfloat> %0,1054 ptr %1,1055 <vscale x 8 x i1> %2,1056 iXLen %3, iXLen 1)1057 1058 ret <vscale x 8 x bfloat> %a1059}1060 1061define <vscale x 16 x bfloat> @intrinsic_vle_v_nxv16bf16_nxv16bf16(ptr %0, iXLen %1) nounwind {1062; CHECK-LABEL: intrinsic_vle_v_nxv16bf16_nxv16bf16:1063; CHECK: # %bb.0: # %entry1064; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1065; CHECK-NEXT: vle16.v v8, (a0)1066; CHECK-NEXT: ret1067entry:1068 %a = call <vscale x 16 x bfloat> @llvm.riscv.vle.nxv16bf16(1069 <vscale x 16 x bfloat> poison,1070 ptr %0,1071 iXLen %1)1072 1073 ret <vscale x 16 x bfloat> %a1074}1075 1076define <vscale x 16 x bfloat> @intrinsic_vle_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1077; CHECK-LABEL: intrinsic_vle_mask_v_nxv16bf16_nxv16bf16:1078; CHECK: # %bb.0: # %entry1079; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1080; CHECK-NEXT: vle16.v v8, (a0), v0.t1081; CHECK-NEXT: ret1082entry:1083 %a = call <vscale x 16 x bfloat> @llvm.riscv.vle.mask.nxv16bf16(1084 <vscale x 16 x bfloat> %0,1085 ptr %1,1086 <vscale x 16 x i1> %2,1087 iXLen %3, iXLen 1)1088 1089 ret <vscale x 16 x bfloat> %a1090}1091 1092define <vscale x 32 x bfloat> @intrinsic_vle_v_nxv32bf16_nxv32bf16(ptr %0, iXLen %1) nounwind {1093; CHECK-LABEL: intrinsic_vle_v_nxv32bf16_nxv32bf16:1094; CHECK: # %bb.0: # %entry1095; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1096; CHECK-NEXT: vle16.v v8, (a0)1097; CHECK-NEXT: ret1098entry:1099 %a = call <vscale x 32 x bfloat> @llvm.riscv.vle.nxv32bf16(1100 <vscale x 32 x bfloat> poison,1101 ptr %0,1102 iXLen %1)1103 1104 ret <vscale x 32 x bfloat> %a1105}1106 1107define <vscale x 32 x bfloat> @intrinsic_vle_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1108; CHECK-LABEL: intrinsic_vle_mask_v_nxv32bf16_nxv32bf16:1109; CHECK: # %bb.0: # %entry1110; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1111; CHECK-NEXT: vle16.v v8, (a0), v0.t1112; CHECK-NEXT: ret1113entry:1114 %a = call <vscale x 32 x bfloat> @llvm.riscv.vle.mask.nxv32bf16(1115 <vscale x 32 x bfloat> %0,1116 ptr %1,1117 <vscale x 32 x i1> %2,1118 iXLen %3, iXLen 1)1119 1120 ret <vscale x 32 x bfloat> %a1121}1122 1123define <vscale x 1 x i8> @intrinsic_vle_v_nxv1i8_nxv1i8(ptr %0, iXLen %1) nounwind {1124; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8:1125; CHECK: # %bb.0: # %entry1126; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1127; CHECK-NEXT: vle8.v v8, (a0)1128; CHECK-NEXT: ret1129entry:1130 %a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(1131 <vscale x 1 x i8> poison,1132 ptr %0,1133 iXLen %1)1134 1135 ret <vscale x 1 x i8> %a1136}1137 1138define <vscale x 1 x i8> @intrinsic_vle_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1139; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8:1140; CHECK: # %bb.0: # %entry1141; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu1142; CHECK-NEXT: vle8.v v8, (a0), v0.t1143; CHECK-NEXT: ret1144entry:1145 %a = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8(1146 <vscale x 1 x i8> %0,1147 ptr %1,1148 <vscale x 1 x i1> %2,1149 iXLen %3, iXLen 1)1150 1151 ret <vscale x 1 x i8> %a1152}1153 1154define <vscale x 2 x i8> @intrinsic_vle_v_nxv2i8_nxv2i8(ptr %0, iXLen %1) nounwind {1155; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8:1156; CHECK: # %bb.0: # %entry1157; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1158; CHECK-NEXT: vle8.v v8, (a0)1159; CHECK-NEXT: ret1160entry:1161 %a = call <vscale x 2 x i8> @llvm.riscv.vle.nxv2i8(1162 <vscale x 2 x i8> poison,1163 ptr %0,1164 iXLen %1)1165 1166 ret <vscale x 2 x i8> %a1167}1168 1169define <vscale x 2 x i8> @intrinsic_vle_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1170; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8:1171; CHECK: # %bb.0: # %entry1172; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu1173; CHECK-NEXT: vle8.v v8, (a0), v0.t1174; CHECK-NEXT: ret1175entry:1176 %a = call <vscale x 2 x i8> @llvm.riscv.vle.mask.nxv2i8(1177 <vscale x 2 x i8> %0,1178 ptr %1,1179 <vscale x 2 x i1> %2,1180 iXLen %3, iXLen 1)1181 1182 ret <vscale x 2 x i8> %a1183}1184 1185define <vscale x 4 x i8> @intrinsic_vle_v_nxv4i8_nxv4i8(ptr %0, iXLen %1) nounwind {1186; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8:1187; CHECK: # %bb.0: # %entry1188; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1189; CHECK-NEXT: vle8.v v8, (a0)1190; CHECK-NEXT: ret1191entry:1192 %a = call <vscale x 4 x i8> @llvm.riscv.vle.nxv4i8(1193 <vscale x 4 x i8> poison,1194 ptr %0,1195 iXLen %1)1196 1197 ret <vscale x 4 x i8> %a1198}1199 1200define <vscale x 4 x i8> @intrinsic_vle_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1201; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8:1202; CHECK: # %bb.0: # %entry1203; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu1204; CHECK-NEXT: vle8.v v8, (a0), v0.t1205; CHECK-NEXT: ret1206entry:1207 %a = call <vscale x 4 x i8> @llvm.riscv.vle.mask.nxv4i8(1208 <vscale x 4 x i8> %0,1209 ptr %1,1210 <vscale x 4 x i1> %2,1211 iXLen %3, iXLen 1)1212 1213 ret <vscale x 4 x i8> %a1214}1215 1216define <vscale x 8 x i8> @intrinsic_vle_v_nxv8i8_nxv8i8(ptr %0, iXLen %1) nounwind {1217; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8:1218; CHECK: # %bb.0: # %entry1219; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1220; CHECK-NEXT: vle8.v v8, (a0)1221; CHECK-NEXT: ret1222entry:1223 %a = call <vscale x 8 x i8> @llvm.riscv.vle.nxv8i8(1224 <vscale x 8 x i8> poison,1225 ptr %0,1226 iXLen %1)1227 1228 ret <vscale x 8 x i8> %a1229}1230 1231define <vscale x 8 x i8> @intrinsic_vle_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1232; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8:1233; CHECK: # %bb.0: # %entry1234; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu1235; CHECK-NEXT: vle8.v v8, (a0), v0.t1236; CHECK-NEXT: ret1237entry:1238 %a = call <vscale x 8 x i8> @llvm.riscv.vle.mask.nxv8i8(1239 <vscale x 8 x i8> %0,1240 ptr %1,1241 <vscale x 8 x i1> %2,1242 iXLen %3, iXLen 1)1243 1244 ret <vscale x 8 x i8> %a1245}1246 1247define <vscale x 16 x i8> @intrinsic_vle_v_nxv16i8_nxv16i8(ptr %0, iXLen %1) nounwind {1248; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8:1249; CHECK: # %bb.0: # %entry1250; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1251; CHECK-NEXT: vle8.v v8, (a0)1252; CHECK-NEXT: ret1253entry:1254 %a = call <vscale x 16 x i8> @llvm.riscv.vle.nxv16i8(1255 <vscale x 16 x i8> poison,1256 ptr %0,1257 iXLen %1)1258 1259 ret <vscale x 16 x i8> %a1260}1261 1262define <vscale x 16 x i8> @intrinsic_vle_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1263; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8:1264; CHECK: # %bb.0: # %entry1265; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu1266; CHECK-NEXT: vle8.v v8, (a0), v0.t1267; CHECK-NEXT: ret1268entry:1269 %a = call <vscale x 16 x i8> @llvm.riscv.vle.mask.nxv16i8(1270 <vscale x 16 x i8> %0,1271 ptr %1,1272 <vscale x 16 x i1> %2,1273 iXLen %3, iXLen 1)1274 1275 ret <vscale x 16 x i8> %a1276}1277 1278define <vscale x 32 x i8> @intrinsic_vle_v_nxv32i8_nxv32i8(ptr %0, iXLen %1) nounwind {1279; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8:1280; CHECK: # %bb.0: # %entry1281; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1282; CHECK-NEXT: vle8.v v8, (a0)1283; CHECK-NEXT: ret1284entry:1285 %a = call <vscale x 32 x i8> @llvm.riscv.vle.nxv32i8(1286 <vscale x 32 x i8> poison,1287 ptr %0,1288 iXLen %1)1289 1290 ret <vscale x 32 x i8> %a1291}1292 1293define <vscale x 32 x i8> @intrinsic_vle_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1294; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8:1295; CHECK: # %bb.0: # %entry1296; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu1297; CHECK-NEXT: vle8.v v8, (a0), v0.t1298; CHECK-NEXT: ret1299entry:1300 %a = call <vscale x 32 x i8> @llvm.riscv.vle.mask.nxv32i8(1301 <vscale x 32 x i8> %0,1302 ptr %1,1303 <vscale x 32 x i1> %2,1304 iXLen %3, iXLen 1)1305 1306 ret <vscale x 32 x i8> %a1307}1308 1309define <vscale x 64 x i8> @intrinsic_vle_v_nxv64i8_nxv64i8(ptr %0, iXLen %1) nounwind {1310; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8:1311; CHECK: # %bb.0: # %entry1312; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1313; CHECK-NEXT: vle8.v v8, (a0)1314; CHECK-NEXT: ret1315entry:1316 %a = call <vscale x 64 x i8> @llvm.riscv.vle.nxv64i8(1317 <vscale x 64 x i8> poison,1318 ptr %0,1319 iXLen %1)1320 1321 ret <vscale x 64 x i8> %a1322}1323 1324define <vscale x 64 x i8> @intrinsic_vle_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1325; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8:1326; CHECK: # %bb.0: # %entry1327; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu1328; CHECK-NEXT: vle8.v v8, (a0), v0.t1329; CHECK-NEXT: ret1330entry:1331 %a = call <vscale x 64 x i8> @llvm.riscv.vle.mask.nxv64i8(1332 <vscale x 64 x i8> %0,1333 ptr %1,1334 <vscale x 64 x i1> %2,1335 iXLen %3, iXLen 1)1336 1337 ret <vscale x 64 x i8> %a1338}1339