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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel -target-abi=lp64 < %s | FileCheck %s3 4define i64 @test_vleff_nxv8i8(ptr %p, i64 %vl) {5 ; CHECK-LABEL: name: test_vleff_nxv8i86 ; CHECK: bb.0.entry:7 ; CHECK-NEXT: liveins: $x10, $x118 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1011 ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1)12 ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]]13 ; CHECK-NEXT: PseudoRET implicit $x1014entry:15 %0 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8> poison, ptr %p, i64 %vl)16 %1 = extractvalue { <vscale x 8 x i8>, i64 } %0, 117 ret i64 %118}19 20define i64 @test_vleff_nxv8i8_tu(<vscale x 8 x i8> %passthru, ptr %p, i64 %vl) {21 ; CHECK-LABEL: name: test_vleff_nxv8i8_tu22 ; CHECK: bb.0.entry:23 ; CHECK-NEXT: liveins: $v8, $x10, $x1124 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1126 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1027 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v828 ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1)29 ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]]30 ; CHECK-NEXT: PseudoRET implicit $x1031entry:32 %0 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8> %passthru, ptr %p, i64 %vl)33 %1 = extractvalue { <vscale x 8 x i8>, i64 } %0, 134 ret i64 %135}36 37define i64 @test_vleff_nxv8i8_mask(<vscale x 8 x i8> %maskedoff, ptr %p, <vscale x 8 x i1> %m, i64 %vl) {38 ; CHECK-LABEL: name: test_vleff_nxv8i8_mask39 ; CHECK: bb.0.entry:40 ; CHECK-NEXT: liveins: $v8, $x10, $v0, $x1141 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1143 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v044 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1045 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrnov0 = COPY $v846 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vmv0 = COPY [[COPY1]]47 ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_MASK:%[0-9]+]]:vrnov0, [[PseudoVLE8FF_V_M1_MASK1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1_MASK [[COPY3]], [[COPY2]], [[COPY4]], [[COPY]], 3 /* e8 */, 0 /* tu, mu */ :: (load unknown-size from %ir.p, align 1)48 ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_MASK1]]49 ; CHECK-NEXT: PseudoRET implicit $x1050entry:51 %0 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8> %maskedoff, ptr %p, <vscale x 8 x i1> %m, i64 %vl, i64 0)52 %1 = extractvalue { <vscale x 8 x i8>, i64 } %0, 153 ret i64 %154}55 56define i64 @test_vlseg2ff_nxv8i8(ptr %base, i64 %vl, ptr %outvl) {57 ; CHECK-LABEL: name: test_vlseg2ff_nxv8i858 ; CHECK: bb.0.entry:59 ; CHECK-NEXT: liveins: $x10, $x1160 ; CHECK-NEXT: {{ $}}61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1162 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1063 ; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.base, align 1)64 ; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_1]]65 ; CHECK-NEXT: PseudoRET implicit $x1066entry:67 %0 = tail call {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) poison, ptr %base, i64 %vl, i64 3)68 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} %0, 169 ret i64 %170}71 72define i64 @test_vlseg2ff_nxv8i8_tu(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, i64 %vl, ptr %outvl) {73 ; CHECK-LABEL: name: test_vlseg2ff_nxv8i8_tu74 ; CHECK: bb.0.entry:75 ; CHECK-NEXT: liveins: $v8_v9, $x10, $x1176 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1079 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY $v8_v980 ; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.base, align 1)81 ; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_1]]82 ; CHECK-NEXT: PseudoRET implicit $x1083entry:84 %0 = tail call {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, i64 %vl, i64 3)85 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} %0, 186 ret i64 %187}88 89define i64 @test_vlseg2ff_nxv8i8_mask(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i1> %mask, i64 %vl, ptr %outvl) {90 ; CHECK-LABEL: name: test_vlseg2ff_nxv8i8_mask91 ; CHECK: bb.0.entry:92 ; CHECK-NEXT: liveins: $v8_v9, $x10, $v0, $x1193 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1195 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v096 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1097 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrn2m1nov0 = COPY $v8_v998 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vmv0 = COPY [[COPY1]]99 ; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_MASK:%[0-9]+]]:vrn2m1nov0, [[PseudoVLSEG2E8FF_V_M1_MASK1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1_MASK [[COPY3]], [[COPY2]], [[COPY4]], [[COPY]], 3 /* e8 */, 0 /* tu, mu */ :: (load unknown-size from %ir.base, align 1)100 ; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_MASK1]]101 ; CHECK-NEXT: PseudoRET implicit $x10102entry:103 %0 = tail call {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i1> %mask, i64 %vl, i64 0, i64 3)104 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 8 x i8>, 2), i64} %0, 1105 ret i64 %1106}107