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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(ptr %0, iXLen %1, ptr %2) nounwind {8; RV32-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64:9; RV32: # %bb.0: # %entry10; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma11; RV32-NEXT: vle64ff.v v8, (a0)12; RV32-NEXT: csrr a0, vl13; RV32-NEXT: sw a0, 0(a2)14; RV32-NEXT: ret15;16; RV64-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64:17; RV64: # %bb.0: # %entry18; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma19; RV64-NEXT: vle64ff.v v8, (a0)20; RV64-NEXT: csrr a0, vl21; RV64-NEXT: sd a0, 0(a2)22; RV64-NEXT: ret23entry:24 %a = call { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.nxv1i64(25 <vscale x 1 x i64> poison,26 ptr %0,27 iXLen %1)28 %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 029 %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 130 store iXLen %c, ptr %231 ret <vscale x 1 x i64> %b32}33 34define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {35; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:36; RV32: # %bb.0: # %entry37; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, mu38; RV32-NEXT: vle64ff.v v8, (a0), v0.t39; RV32-NEXT: csrr a0, vl40; RV32-NEXT: sw a0, 0(a2)41; RV32-NEXT: ret42;43; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64:44; RV64: # %bb.0: # %entry45; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu46; RV64-NEXT: vle64ff.v v8, (a0), v0.t47; RV64-NEXT: csrr a0, vl48; RV64-NEXT: sd a0, 0(a2)49; RV64-NEXT: ret50entry:51 %a = call { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv1i64(52 <vscale x 1 x i64> %0,53 ptr %1,54 <vscale x 1 x i1> %2,55 iXLen %3, iXLen 1)56 %b = extractvalue { <vscale x 1 x i64>, iXLen } %a, 057 %c = extractvalue { <vscale x 1 x i64>, iXLen } %a, 158 store iXLen %c, ptr %459 60 ret <vscale x 1 x i64> %b61}62 63define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(ptr %0, iXLen %1, ptr %2) nounwind {64; RV32-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64:65; RV32: # %bb.0: # %entry66; RV32-NEXT: vsetvli zero, a1, e64, m2, ta, ma67; RV32-NEXT: vle64ff.v v8, (a0)68; RV32-NEXT: csrr a0, vl69; RV32-NEXT: sw a0, 0(a2)70; RV32-NEXT: ret71;72; RV64-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64:73; RV64: # %bb.0: # %entry74; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma75; RV64-NEXT: vle64ff.v v8, (a0)76; RV64-NEXT: csrr a0, vl77; RV64-NEXT: sd a0, 0(a2)78; RV64-NEXT: ret79entry:80 %a = call { <vscale x 2 x i64>, iXLen } @llvm.riscv.vleff.nxv2i64(81 <vscale x 2 x i64> poison,82 ptr %0,83 iXLen %1)84 %b = extractvalue { <vscale x 2 x i64>, iXLen } %a, 085 %c = extractvalue { <vscale x 2 x i64>, iXLen } %a, 186 store iXLen %c, ptr %287 ret <vscale x 2 x i64> %b88}89 90define <vscale x 2 x i64> @intrinsic_vleff_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {91; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64:92; RV32: # %bb.0: # %entry93; RV32-NEXT: vsetvli zero, a1, e64, m2, ta, mu94; RV32-NEXT: vle64ff.v v8, (a0), v0.t95; RV32-NEXT: csrr a0, vl96; RV32-NEXT: sw a0, 0(a2)97; RV32-NEXT: ret98;99; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64:100; RV64: # %bb.0: # %entry101; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu102; RV64-NEXT: vle64ff.v v8, (a0), v0.t103; RV64-NEXT: csrr a0, vl104; RV64-NEXT: sd a0, 0(a2)105; RV64-NEXT: ret106entry:107 %a = call { <vscale x 2 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv2i64(108 <vscale x 2 x i64> %0,109 ptr %1,110 <vscale x 2 x i1> %2,111 iXLen %3, iXLen 1)112 %b = extractvalue { <vscale x 2 x i64>, iXLen } %a, 0113 %c = extractvalue { <vscale x 2 x i64>, iXLen } %a, 1114 store iXLen %c, ptr %4115 116 ret <vscale x 2 x i64> %b117}118 119define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(ptr %0, iXLen %1, ptr %2) nounwind {120; RV32-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64:121; RV32: # %bb.0: # %entry122; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma123; RV32-NEXT: vle64ff.v v8, (a0)124; RV32-NEXT: csrr a0, vl125; RV32-NEXT: sw a0, 0(a2)126; RV32-NEXT: ret127;128; RV64-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64:129; RV64: # %bb.0: # %entry130; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma131; RV64-NEXT: vle64ff.v v8, (a0)132; RV64-NEXT: csrr a0, vl133; RV64-NEXT: sd a0, 0(a2)134; RV64-NEXT: ret135entry:136 %a = call { <vscale x 4 x i64>, iXLen } @llvm.riscv.vleff.nxv4i64(137 <vscale x 4 x i64> poison,138 ptr %0,139 iXLen %1)140 %b = extractvalue { <vscale x 4 x i64>, iXLen } %a, 0141 %c = extractvalue { <vscale x 4 x i64>, iXLen } %a, 1142 store iXLen %c, ptr %2143 ret <vscale x 4 x i64> %b144}145 146define <vscale x 4 x i64> @intrinsic_vleff_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {147; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64:148; RV32: # %bb.0: # %entry149; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu150; RV32-NEXT: vle64ff.v v8, (a0), v0.t151; RV32-NEXT: csrr a0, vl152; RV32-NEXT: sw a0, 0(a2)153; RV32-NEXT: ret154;155; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64:156; RV64: # %bb.0: # %entry157; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu158; RV64-NEXT: vle64ff.v v8, (a0), v0.t159; RV64-NEXT: csrr a0, vl160; RV64-NEXT: sd a0, 0(a2)161; RV64-NEXT: ret162entry:163 %a = call { <vscale x 4 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv4i64(164 <vscale x 4 x i64> %0,165 ptr %1,166 <vscale x 4 x i1> %2,167 iXLen %3, iXLen 1)168 %b = extractvalue { <vscale x 4 x i64>, iXLen } %a, 0169 %c = extractvalue { <vscale x 4 x i64>, iXLen } %a, 1170 store iXLen %c, ptr %4171 172 ret <vscale x 4 x i64> %b173}174 175define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(ptr %0, iXLen %1, ptr %2) nounwind {176; RV32-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64:177; RV32: # %bb.0: # %entry178; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma179; RV32-NEXT: vle64ff.v v8, (a0)180; RV32-NEXT: csrr a0, vl181; RV32-NEXT: sw a0, 0(a2)182; RV32-NEXT: ret183;184; RV64-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64:185; RV64: # %bb.0: # %entry186; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma187; RV64-NEXT: vle64ff.v v8, (a0)188; RV64-NEXT: csrr a0, vl189; RV64-NEXT: sd a0, 0(a2)190; RV64-NEXT: ret191entry:192 %a = call { <vscale x 8 x i64>, iXLen } @llvm.riscv.vleff.nxv8i64(193 <vscale x 8 x i64> poison,194 ptr %0,195 iXLen %1)196 %b = extractvalue { <vscale x 8 x i64>, iXLen } %a, 0197 %c = extractvalue { <vscale x 8 x i64>, iXLen } %a, 1198 store iXLen %c, ptr %2199 ret <vscale x 8 x i64> %b200}201 202define <vscale x 8 x i64> @intrinsic_vleff_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {203; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64:204; RV32: # %bb.0: # %entry205; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu206; RV32-NEXT: vle64ff.v v8, (a0), v0.t207; RV32-NEXT: csrr a0, vl208; RV32-NEXT: sw a0, 0(a2)209; RV32-NEXT: ret210;211; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64:212; RV64: # %bb.0: # %entry213; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu214; RV64-NEXT: vle64ff.v v8, (a0), v0.t215; RV64-NEXT: csrr a0, vl216; RV64-NEXT: sd a0, 0(a2)217; RV64-NEXT: ret218entry:219 %a = call { <vscale x 8 x i64>, iXLen } @llvm.riscv.vleff.mask.nxv8i64(220 <vscale x 8 x i64> %0,221 ptr %1,222 <vscale x 8 x i1> %2,223 iXLen %3, iXLen 1)224 %b = extractvalue { <vscale x 8 x i64>, iXLen } %a, 0225 %c = extractvalue { <vscale x 8 x i64>, iXLen } %a, 1226 store iXLen %c, ptr %4227 228 ret <vscale x 8 x i64> %b229}230 231define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(ptr %0, iXLen %1, ptr %2) nounwind {232; RV32-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64:233; RV32: # %bb.0: # %entry234; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma235; RV32-NEXT: vle64ff.v v8, (a0)236; RV32-NEXT: csrr a0, vl237; RV32-NEXT: sw a0, 0(a2)238; RV32-NEXT: ret239;240; RV64-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64:241; RV64: # %bb.0: # %entry242; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma243; RV64-NEXT: vle64ff.v v8, (a0)244; RV64-NEXT: csrr a0, vl245; RV64-NEXT: sd a0, 0(a2)246; RV64-NEXT: ret247entry:248 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.nxv1f64(249 <vscale x 1 x double> poison,250 ptr %0,251 iXLen %1)252 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 0253 %c = extractvalue { <vscale x 1 x double>, iXLen } %a, 1254 store iXLen %c, ptr %2255 ret <vscale x 1 x double> %b256}257 258define <vscale x 1 x double> @intrinsic_vleff_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {259; RV32-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64:260; RV32: # %bb.0: # %entry261; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, mu262; RV32-NEXT: vle64ff.v v8, (a0), v0.t263; RV32-NEXT: csrr a0, vl264; RV32-NEXT: sw a0, 0(a2)265; RV32-NEXT: ret266;267; RV64-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64:268; RV64: # %bb.0: # %entry269; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu270; RV64-NEXT: vle64ff.v v8, (a0), v0.t271; RV64-NEXT: csrr a0, vl272; RV64-NEXT: sd a0, 0(a2)273; RV64-NEXT: ret274entry:275 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.mask.nxv1f64(276 <vscale x 1 x double> %0,277 ptr %1,278 <vscale x 1 x i1> %2,279 iXLen %3, iXLen 1)280 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 0281 %c = extractvalue { <vscale x 1 x double>, iXLen } %a, 1282 store iXLen %c, ptr %4283 284 ret <vscale x 1 x double> %b285}286 287define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(ptr %0, iXLen %1, ptr %2) nounwind {288; RV32-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64:289; RV32: # %bb.0: # %entry290; RV32-NEXT: vsetvli zero, a1, e64, m2, ta, ma291; RV32-NEXT: vle64ff.v v8, (a0)292; RV32-NEXT: csrr a0, vl293; RV32-NEXT: sw a0, 0(a2)294; RV32-NEXT: ret295;296; RV64-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64:297; RV64: # %bb.0: # %entry298; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma299; RV64-NEXT: vle64ff.v v8, (a0)300; RV64-NEXT: csrr a0, vl301; RV64-NEXT: sd a0, 0(a2)302; RV64-NEXT: ret303entry:304 %a = call { <vscale x 2 x double>, iXLen } @llvm.riscv.vleff.nxv2f64(305 <vscale x 2 x double> poison,306 ptr %0,307 iXLen %1)308 %b = extractvalue { <vscale x 2 x double>, iXLen } %a, 0309 %c = extractvalue { <vscale x 2 x double>, iXLen } %a, 1310 store iXLen %c, ptr %2311 ret <vscale x 2 x double> %b312}313 314define <vscale x 2 x double> @intrinsic_vleff_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {315; RV32-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64:316; RV32: # %bb.0: # %entry317; RV32-NEXT: vsetvli zero, a1, e64, m2, ta, mu318; RV32-NEXT: vle64ff.v v8, (a0), v0.t319; RV32-NEXT: csrr a0, vl320; RV32-NEXT: sw a0, 0(a2)321; RV32-NEXT: ret322;323; RV64-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64:324; RV64: # %bb.0: # %entry325; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu326; RV64-NEXT: vle64ff.v v8, (a0), v0.t327; RV64-NEXT: csrr a0, vl328; RV64-NEXT: sd a0, 0(a2)329; RV64-NEXT: ret330entry:331 %a = call { <vscale x 2 x double>, iXLen } @llvm.riscv.vleff.mask.nxv2f64(332 <vscale x 2 x double> %0,333 ptr %1,334 <vscale x 2 x i1> %2,335 iXLen %3, iXLen 1)336 %b = extractvalue { <vscale x 2 x double>, iXLen } %a, 0337 %c = extractvalue { <vscale x 2 x double>, iXLen } %a, 1338 store iXLen %c, ptr %4339 340 ret <vscale x 2 x double> %b341}342 343define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(ptr %0, iXLen %1, ptr %2) nounwind {344; RV32-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64:345; RV32: # %bb.0: # %entry346; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, ma347; RV32-NEXT: vle64ff.v v8, (a0)348; RV32-NEXT: csrr a0, vl349; RV32-NEXT: sw a0, 0(a2)350; RV32-NEXT: ret351;352; RV64-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64:353; RV64: # %bb.0: # %entry354; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma355; RV64-NEXT: vle64ff.v v8, (a0)356; RV64-NEXT: csrr a0, vl357; RV64-NEXT: sd a0, 0(a2)358; RV64-NEXT: ret359entry:360 %a = call { <vscale x 4 x double>, iXLen } @llvm.riscv.vleff.nxv4f64(361 <vscale x 4 x double> poison,362 ptr %0,363 iXLen %1)364 %b = extractvalue { <vscale x 4 x double>, iXLen } %a, 0365 %c = extractvalue { <vscale x 4 x double>, iXLen } %a, 1366 store iXLen %c, ptr %2367 ret <vscale x 4 x double> %b368}369 370define <vscale x 4 x double> @intrinsic_vleff_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {371; RV32-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64:372; RV32: # %bb.0: # %entry373; RV32-NEXT: vsetvli zero, a1, e64, m4, ta, mu374; RV32-NEXT: vle64ff.v v8, (a0), v0.t375; RV32-NEXT: csrr a0, vl376; RV32-NEXT: sw a0, 0(a2)377; RV32-NEXT: ret378;379; RV64-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64:380; RV64: # %bb.0: # %entry381; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu382; RV64-NEXT: vle64ff.v v8, (a0), v0.t383; RV64-NEXT: csrr a0, vl384; RV64-NEXT: sd a0, 0(a2)385; RV64-NEXT: ret386entry:387 %a = call { <vscale x 4 x double>, iXLen } @llvm.riscv.vleff.mask.nxv4f64(388 <vscale x 4 x double> %0,389 ptr %1,390 <vscale x 4 x i1> %2,391 iXLen %3, iXLen 1)392 %b = extractvalue { <vscale x 4 x double>, iXLen } %a, 0393 %c = extractvalue { <vscale x 4 x double>, iXLen } %a, 1394 store iXLen %c, ptr %4395 396 ret <vscale x 4 x double> %b397}398 399define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(ptr %0, iXLen %1, ptr %2) nounwind {400; RV32-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64:401; RV32: # %bb.0: # %entry402; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma403; RV32-NEXT: vle64ff.v v8, (a0)404; RV32-NEXT: csrr a0, vl405; RV32-NEXT: sw a0, 0(a2)406; RV32-NEXT: ret407;408; RV64-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64:409; RV64: # %bb.0: # %entry410; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma411; RV64-NEXT: vle64ff.v v8, (a0)412; RV64-NEXT: csrr a0, vl413; RV64-NEXT: sd a0, 0(a2)414; RV64-NEXT: ret415entry:416 %a = call { <vscale x 8 x double>, iXLen } @llvm.riscv.vleff.nxv8f64(417 <vscale x 8 x double> poison,418 ptr %0,419 iXLen %1)420 %b = extractvalue { <vscale x 8 x double>, iXLen } %a, 0421 %c = extractvalue { <vscale x 8 x double>, iXLen } %a, 1422 store iXLen %c, ptr %2423 ret <vscale x 8 x double> %b424}425 426define <vscale x 8 x double> @intrinsic_vleff_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {427; RV32-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64:428; RV32: # %bb.0: # %entry429; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu430; RV32-NEXT: vle64ff.v v8, (a0), v0.t431; RV32-NEXT: csrr a0, vl432; RV32-NEXT: sw a0, 0(a2)433; RV32-NEXT: ret434;435; RV64-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64:436; RV64: # %bb.0: # %entry437; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu438; RV64-NEXT: vle64ff.v v8, (a0), v0.t439; RV64-NEXT: csrr a0, vl440; RV64-NEXT: sd a0, 0(a2)441; RV64-NEXT: ret442entry:443 %a = call { <vscale x 8 x double>, iXLen } @llvm.riscv.vleff.mask.nxv8f64(444 <vscale x 8 x double> %0,445 ptr %1,446 <vscale x 8 x i1> %2,447 iXLen %3, iXLen 1)448 %b = extractvalue { <vscale x 8 x double>, iXLen } %a, 0449 %c = extractvalue { <vscale x 8 x double>, iXLen } %a, 1450 store iXLen %c, ptr %4451 452 ret <vscale x 8 x double> %b453}454 455define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(ptr %0, iXLen %1, ptr %2) nounwind {456; RV32-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32:457; RV32: # %bb.0: # %entry458; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma459; RV32-NEXT: vle32ff.v v8, (a0)460; RV32-NEXT: csrr a0, vl461; RV32-NEXT: sw a0, 0(a2)462; RV32-NEXT: ret463;464; RV64-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32:465; RV64: # %bb.0: # %entry466; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma467; RV64-NEXT: vle32ff.v v8, (a0)468; RV64-NEXT: csrr a0, vl469; RV64-NEXT: sd a0, 0(a2)470; RV64-NEXT: ret471entry:472 %a = call { <vscale x 1 x i32>, iXLen } @llvm.riscv.vleff.nxv1i32(473 <vscale x 1 x i32> poison,474 ptr %0,475 iXLen %1)476 %b = extractvalue { <vscale x 1 x i32>, iXLen } %a, 0477 %c = extractvalue { <vscale x 1 x i32>, iXLen } %a, 1478 store iXLen %c, ptr %2479 ret <vscale x 1 x i32> %b480}481 482define <vscale x 1 x i32> @intrinsic_vleff_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {483; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32:484; RV32: # %bb.0: # %entry485; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, mu486; RV32-NEXT: vle32ff.v v8, (a0), v0.t487; RV32-NEXT: csrr a0, vl488; RV32-NEXT: sw a0, 0(a2)489; RV32-NEXT: ret490;491; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32:492; RV64: # %bb.0: # %entry493; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, mu494; RV64-NEXT: vle32ff.v v8, (a0), v0.t495; RV64-NEXT: csrr a0, vl496; RV64-NEXT: sd a0, 0(a2)497; RV64-NEXT: ret498entry:499 %a = call { <vscale x 1 x i32>, iXLen } @llvm.riscv.vleff.mask.nxv1i32(500 <vscale x 1 x i32> %0,501 ptr %1,502 <vscale x 1 x i1> %2,503 iXLen %3, iXLen 1)504 %b = extractvalue { <vscale x 1 x i32>, iXLen } %a, 0505 %c = extractvalue { <vscale x 1 x i32>, iXLen } %a, 1506 store iXLen %c, ptr %4507 508 ret <vscale x 1 x i32> %b509}510 511define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(ptr %0, iXLen %1, ptr %2) nounwind {512; RV32-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32:513; RV32: # %bb.0: # %entry514; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma515; RV32-NEXT: vle32ff.v v8, (a0)516; RV32-NEXT: csrr a0, vl517; RV32-NEXT: sw a0, 0(a2)518; RV32-NEXT: ret519;520; RV64-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32:521; RV64: # %bb.0: # %entry522; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma523; RV64-NEXT: vle32ff.v v8, (a0)524; RV64-NEXT: csrr a0, vl525; RV64-NEXT: sd a0, 0(a2)526; RV64-NEXT: ret527entry:528 %a = call { <vscale x 2 x i32>, iXLen } @llvm.riscv.vleff.nxv2i32(529 <vscale x 2 x i32> poison,530 ptr %0,531 iXLen %1)532 %b = extractvalue { <vscale x 2 x i32>, iXLen } %a, 0533 %c = extractvalue { <vscale x 2 x i32>, iXLen } %a, 1534 store iXLen %c, ptr %2535 ret <vscale x 2 x i32> %b536}537 538define <vscale x 2 x i32> @intrinsic_vleff_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {539; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32:540; RV32: # %bb.0: # %entry541; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, mu542; RV32-NEXT: vle32ff.v v8, (a0), v0.t543; RV32-NEXT: csrr a0, vl544; RV32-NEXT: sw a0, 0(a2)545; RV32-NEXT: ret546;547; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32:548; RV64: # %bb.0: # %entry549; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, mu550; RV64-NEXT: vle32ff.v v8, (a0), v0.t551; RV64-NEXT: csrr a0, vl552; RV64-NEXT: sd a0, 0(a2)553; RV64-NEXT: ret554entry:555 %a = call { <vscale x 2 x i32>, iXLen } @llvm.riscv.vleff.mask.nxv2i32(556 <vscale x 2 x i32> %0,557 ptr %1,558 <vscale x 2 x i1> %2,559 iXLen %3, iXLen 1)560 %b = extractvalue { <vscale x 2 x i32>, iXLen } %a, 0561 %c = extractvalue { <vscale x 2 x i32>, iXLen } %a, 1562 store iXLen %c, ptr %4563 564 ret <vscale x 2 x i32> %b565}566 567define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(ptr %0, iXLen %1, ptr %2) nounwind {568; RV32-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32:569; RV32: # %bb.0: # %entry570; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma571; RV32-NEXT: vle32ff.v v8, (a0)572; RV32-NEXT: csrr a0, vl573; RV32-NEXT: sw a0, 0(a2)574; RV32-NEXT: ret575;576; RV64-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32:577; RV64: # %bb.0: # %entry578; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma579; RV64-NEXT: vle32ff.v v8, (a0)580; RV64-NEXT: csrr a0, vl581; RV64-NEXT: sd a0, 0(a2)582; RV64-NEXT: ret583entry:584 %a = call { <vscale x 4 x i32>, iXLen } @llvm.riscv.vleff.nxv4i32(585 <vscale x 4 x i32> poison,586 ptr %0,587 iXLen %1)588 %b = extractvalue { <vscale x 4 x i32>, iXLen } %a, 0589 %c = extractvalue { <vscale x 4 x i32>, iXLen } %a, 1590 store iXLen %c, ptr %2591 ret <vscale x 4 x i32> %b592}593 594define <vscale x 4 x i32> @intrinsic_vleff_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {595; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32:596; RV32: # %bb.0: # %entry597; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu598; RV32-NEXT: vle32ff.v v8, (a0), v0.t599; RV32-NEXT: csrr a0, vl600; RV32-NEXT: sw a0, 0(a2)601; RV32-NEXT: ret602;603; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32:604; RV64: # %bb.0: # %entry605; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu606; RV64-NEXT: vle32ff.v v8, (a0), v0.t607; RV64-NEXT: csrr a0, vl608; RV64-NEXT: sd a0, 0(a2)609; RV64-NEXT: ret610entry:611 %a = call { <vscale x 4 x i32>, iXLen } @llvm.riscv.vleff.mask.nxv4i32(612 <vscale x 4 x i32> %0,613 ptr %1,614 <vscale x 4 x i1> %2,615 iXLen %3, iXLen 1)616 %b = extractvalue { <vscale x 4 x i32>, iXLen } %a, 0617 %c = extractvalue { <vscale x 4 x i32>, iXLen } %a, 1618 store iXLen %c, ptr %4619 620 ret <vscale x 4 x i32> %b621}622 623define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(ptr %0, iXLen %1, ptr %2) nounwind {624; RV32-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32:625; RV32: # %bb.0: # %entry626; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma627; RV32-NEXT: vle32ff.v v8, (a0)628; RV32-NEXT: csrr a0, vl629; RV32-NEXT: sw a0, 0(a2)630; RV32-NEXT: ret631;632; RV64-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32:633; RV64: # %bb.0: # %entry634; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma635; RV64-NEXT: vle32ff.v v8, (a0)636; RV64-NEXT: csrr a0, vl637; RV64-NEXT: sd a0, 0(a2)638; RV64-NEXT: ret639entry:640 %a = call { <vscale x 8 x i32>, iXLen } @llvm.riscv.vleff.nxv8i32(641 <vscale x 8 x i32> poison,642 ptr %0,643 iXLen %1)644 %b = extractvalue { <vscale x 8 x i32>, iXLen } %a, 0645 %c = extractvalue { <vscale x 8 x i32>, iXLen } %a, 1646 store iXLen %c, ptr %2647 ret <vscale x 8 x i32> %b648}649 650define <vscale x 8 x i32> @intrinsic_vleff_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {651; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32:652; RV32: # %bb.0: # %entry653; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu654; RV32-NEXT: vle32ff.v v8, (a0), v0.t655; RV32-NEXT: csrr a0, vl656; RV32-NEXT: sw a0, 0(a2)657; RV32-NEXT: ret658;659; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32:660; RV64: # %bb.0: # %entry661; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, mu662; RV64-NEXT: vle32ff.v v8, (a0), v0.t663; RV64-NEXT: csrr a0, vl664; RV64-NEXT: sd a0, 0(a2)665; RV64-NEXT: ret666entry:667 %a = call { <vscale x 8 x i32>, iXLen } @llvm.riscv.vleff.mask.nxv8i32(668 <vscale x 8 x i32> %0,669 ptr %1,670 <vscale x 8 x i1> %2,671 iXLen %3, iXLen 1)672 %b = extractvalue { <vscale x 8 x i32>, iXLen } %a, 0673 %c = extractvalue { <vscale x 8 x i32>, iXLen } %a, 1674 store iXLen %c, ptr %4675 676 ret <vscale x 8 x i32> %b677}678 679define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(ptr %0, iXLen %1, ptr %2) nounwind {680; RV32-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32:681; RV32: # %bb.0: # %entry682; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma683; RV32-NEXT: vle32ff.v v8, (a0)684; RV32-NEXT: csrr a0, vl685; RV32-NEXT: sw a0, 0(a2)686; RV32-NEXT: ret687;688; RV64-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32:689; RV64: # %bb.0: # %entry690; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma691; RV64-NEXT: vle32ff.v v8, (a0)692; RV64-NEXT: csrr a0, vl693; RV64-NEXT: sd a0, 0(a2)694; RV64-NEXT: ret695entry:696 %a = call { <vscale x 16 x i32>, iXLen } @llvm.riscv.vleff.nxv16i32(697 <vscale x 16 x i32> poison,698 ptr %0,699 iXLen %1)700 %b = extractvalue { <vscale x 16 x i32>, iXLen } %a, 0701 %c = extractvalue { <vscale x 16 x i32>, iXLen } %a, 1702 store iXLen %c, ptr %2703 ret <vscale x 16 x i32> %b704}705 706define <vscale x 16 x i32> @intrinsic_vleff_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {707; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32:708; RV32: # %bb.0: # %entry709; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu710; RV32-NEXT: vle32ff.v v8, (a0), v0.t711; RV32-NEXT: csrr a0, vl712; RV32-NEXT: sw a0, 0(a2)713; RV32-NEXT: ret714;715; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32:716; RV64: # %bb.0: # %entry717; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu718; RV64-NEXT: vle32ff.v v8, (a0), v0.t719; RV64-NEXT: csrr a0, vl720; RV64-NEXT: sd a0, 0(a2)721; RV64-NEXT: ret722entry:723 %a = call { <vscale x 16 x i32>, iXLen } @llvm.riscv.vleff.mask.nxv16i32(724 <vscale x 16 x i32> %0,725 ptr %1,726 <vscale x 16 x i1> %2,727 iXLen %3, iXLen 1)728 %b = extractvalue { <vscale x 16 x i32>, iXLen } %a, 0729 %c = extractvalue { <vscale x 16 x i32>, iXLen } %a, 1730 store iXLen %c, ptr %4731 732 ret <vscale x 16 x i32> %b733}734 735define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(ptr %0, iXLen %1, ptr %2) nounwind {736; RV32-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32:737; RV32: # %bb.0: # %entry738; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma739; RV32-NEXT: vle32ff.v v8, (a0)740; RV32-NEXT: csrr a0, vl741; RV32-NEXT: sw a0, 0(a2)742; RV32-NEXT: ret743;744; RV64-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32:745; RV64: # %bb.0: # %entry746; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma747; RV64-NEXT: vle32ff.v v8, (a0)748; RV64-NEXT: csrr a0, vl749; RV64-NEXT: sd a0, 0(a2)750; RV64-NEXT: ret751entry:752 %a = call { <vscale x 1 x float>, iXLen } @llvm.riscv.vleff.nxv1f32(753 <vscale x 1 x float> poison,754 ptr %0,755 iXLen %1)756 %b = extractvalue { <vscale x 1 x float>, iXLen } %a, 0757 %c = extractvalue { <vscale x 1 x float>, iXLen } %a, 1758 store iXLen %c, ptr %2759 ret <vscale x 1 x float> %b760}761 762define <vscale x 1 x float> @intrinsic_vleff_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {763; RV32-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32:764; RV32: # %bb.0: # %entry765; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, mu766; RV32-NEXT: vle32ff.v v8, (a0), v0.t767; RV32-NEXT: csrr a0, vl768; RV32-NEXT: sw a0, 0(a2)769; RV32-NEXT: ret770;771; RV64-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32:772; RV64: # %bb.0: # %entry773; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, mu774; RV64-NEXT: vle32ff.v v8, (a0), v0.t775; RV64-NEXT: csrr a0, vl776; RV64-NEXT: sd a0, 0(a2)777; RV64-NEXT: ret778entry:779 %a = call { <vscale x 1 x float>, iXLen } @llvm.riscv.vleff.mask.nxv1f32(780 <vscale x 1 x float> %0,781 ptr %1,782 <vscale x 1 x i1> %2,783 iXLen %3, iXLen 1)784 %b = extractvalue { <vscale x 1 x float>, iXLen } %a, 0785 %c = extractvalue { <vscale x 1 x float>, iXLen } %a, 1786 store iXLen %c, ptr %4787 788 ret <vscale x 1 x float> %b789}790 791define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(ptr %0, iXLen %1, ptr %2) nounwind {792; RV32-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32:793; RV32: # %bb.0: # %entry794; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma795; RV32-NEXT: vle32ff.v v8, (a0)796; RV32-NEXT: csrr a0, vl797; RV32-NEXT: sw a0, 0(a2)798; RV32-NEXT: ret799;800; RV64-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32:801; RV64: # %bb.0: # %entry802; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma803; RV64-NEXT: vle32ff.v v8, (a0)804; RV64-NEXT: csrr a0, vl805; RV64-NEXT: sd a0, 0(a2)806; RV64-NEXT: ret807entry:808 %a = call { <vscale x 2 x float>, iXLen } @llvm.riscv.vleff.nxv2f32(809 <vscale x 2 x float> poison,810 ptr %0,811 iXLen %1)812 %b = extractvalue { <vscale x 2 x float>, iXLen } %a, 0813 %c = extractvalue { <vscale x 2 x float>, iXLen } %a, 1814 store iXLen %c, ptr %2815 ret <vscale x 2 x float> %b816}817 818define <vscale x 2 x float> @intrinsic_vleff_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {819; RV32-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32:820; RV32: # %bb.0: # %entry821; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, mu822; RV32-NEXT: vle32ff.v v8, (a0), v0.t823; RV32-NEXT: csrr a0, vl824; RV32-NEXT: sw a0, 0(a2)825; RV32-NEXT: ret826;827; RV64-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32:828; RV64: # %bb.0: # %entry829; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, mu830; RV64-NEXT: vle32ff.v v8, (a0), v0.t831; RV64-NEXT: csrr a0, vl832; RV64-NEXT: sd a0, 0(a2)833; RV64-NEXT: ret834entry:835 %a = call { <vscale x 2 x float>, iXLen } @llvm.riscv.vleff.mask.nxv2f32(836 <vscale x 2 x float> %0,837 ptr %1,838 <vscale x 2 x i1> %2,839 iXLen %3, iXLen 1)840 %b = extractvalue { <vscale x 2 x float>, iXLen } %a, 0841 %c = extractvalue { <vscale x 2 x float>, iXLen } %a, 1842 store iXLen %c, ptr %4843 844 ret <vscale x 2 x float> %b845}846 847define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(ptr %0, iXLen %1, ptr %2) nounwind {848; RV32-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32:849; RV32: # %bb.0: # %entry850; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, ma851; RV32-NEXT: vle32ff.v v8, (a0)852; RV32-NEXT: csrr a0, vl853; RV32-NEXT: sw a0, 0(a2)854; RV32-NEXT: ret855;856; RV64-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32:857; RV64: # %bb.0: # %entry858; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma859; RV64-NEXT: vle32ff.v v8, (a0)860; RV64-NEXT: csrr a0, vl861; RV64-NEXT: sd a0, 0(a2)862; RV64-NEXT: ret863entry:864 %a = call { <vscale x 4 x float>, iXLen } @llvm.riscv.vleff.nxv4f32(865 <vscale x 4 x float> poison,866 ptr %0,867 iXLen %1)868 %b = extractvalue { <vscale x 4 x float>, iXLen } %a, 0869 %c = extractvalue { <vscale x 4 x float>, iXLen } %a, 1870 store iXLen %c, ptr %2871 ret <vscale x 4 x float> %b872}873 874define <vscale x 4 x float> @intrinsic_vleff_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {875; RV32-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32:876; RV32: # %bb.0: # %entry877; RV32-NEXT: vsetvli zero, a1, e32, m2, ta, mu878; RV32-NEXT: vle32ff.v v8, (a0), v0.t879; RV32-NEXT: csrr a0, vl880; RV32-NEXT: sw a0, 0(a2)881; RV32-NEXT: ret882;883; RV64-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32:884; RV64: # %bb.0: # %entry885; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, mu886; RV64-NEXT: vle32ff.v v8, (a0), v0.t887; RV64-NEXT: csrr a0, vl888; RV64-NEXT: sd a0, 0(a2)889; RV64-NEXT: ret890entry:891 %a = call { <vscale x 4 x float>, iXLen } @llvm.riscv.vleff.mask.nxv4f32(892 <vscale x 4 x float> %0,893 ptr %1,894 <vscale x 4 x i1> %2,895 iXLen %3, iXLen 1)896 %b = extractvalue { <vscale x 4 x float>, iXLen } %a, 0897 %c = extractvalue { <vscale x 4 x float>, iXLen } %a, 1898 store iXLen %c, ptr %4899 900 ret <vscale x 4 x float> %b901}902 903define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(ptr %0, iXLen %1, ptr %2) nounwind {904; RV32-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32:905; RV32: # %bb.0: # %entry906; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma907; RV32-NEXT: vle32ff.v v8, (a0)908; RV32-NEXT: csrr a0, vl909; RV32-NEXT: sw a0, 0(a2)910; RV32-NEXT: ret911;912; RV64-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32:913; RV64: # %bb.0: # %entry914; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma915; RV64-NEXT: vle32ff.v v8, (a0)916; RV64-NEXT: csrr a0, vl917; RV64-NEXT: sd a0, 0(a2)918; RV64-NEXT: ret919entry:920 %a = call { <vscale x 8 x float>, iXLen } @llvm.riscv.vleff.nxv8f32(921 <vscale x 8 x float> poison,922 ptr %0,923 iXLen %1)924 %b = extractvalue { <vscale x 8 x float>, iXLen } %a, 0925 %c = extractvalue { <vscale x 8 x float>, iXLen } %a, 1926 store iXLen %c, ptr %2927 ret <vscale x 8 x float> %b928}929 930define <vscale x 8 x float> @intrinsic_vleff_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {931; RV32-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32:932; RV32: # %bb.0: # %entry933; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, mu934; RV32-NEXT: vle32ff.v v8, (a0), v0.t935; RV32-NEXT: csrr a0, vl936; RV32-NEXT: sw a0, 0(a2)937; RV32-NEXT: ret938;939; RV64-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32:940; RV64: # %bb.0: # %entry941; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, mu942; RV64-NEXT: vle32ff.v v8, (a0), v0.t943; RV64-NEXT: csrr a0, vl944; RV64-NEXT: sd a0, 0(a2)945; RV64-NEXT: ret946entry:947 %a = call { <vscale x 8 x float>, iXLen } @llvm.riscv.vleff.mask.nxv8f32(948 <vscale x 8 x float> %0,949 ptr %1,950 <vscale x 8 x i1> %2,951 iXLen %3, iXLen 1)952 %b = extractvalue { <vscale x 8 x float>, iXLen } %a, 0953 %c = extractvalue { <vscale x 8 x float>, iXLen } %a, 1954 store iXLen %c, ptr %4955 956 ret <vscale x 8 x float> %b957}958 959define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(ptr %0, iXLen %1, ptr %2) nounwind {960; RV32-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32:961; RV32: # %bb.0: # %entry962; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma963; RV32-NEXT: vle32ff.v v8, (a0)964; RV32-NEXT: csrr a0, vl965; RV32-NEXT: sw a0, 0(a2)966; RV32-NEXT: ret967;968; RV64-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32:969; RV64: # %bb.0: # %entry970; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma971; RV64-NEXT: vle32ff.v v8, (a0)972; RV64-NEXT: csrr a0, vl973; RV64-NEXT: sd a0, 0(a2)974; RV64-NEXT: ret975entry:976 %a = call { <vscale x 16 x float>, iXLen } @llvm.riscv.vleff.nxv16f32(977 <vscale x 16 x float> poison,978 ptr %0,979 iXLen %1)980 %b = extractvalue { <vscale x 16 x float>, iXLen } %a, 0981 %c = extractvalue { <vscale x 16 x float>, iXLen } %a, 1982 store iXLen %c, ptr %2983 ret <vscale x 16 x float> %b984}985 986define <vscale x 16 x float> @intrinsic_vleff_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {987; RV32-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32:988; RV32: # %bb.0: # %entry989; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu990; RV32-NEXT: vle32ff.v v8, (a0), v0.t991; RV32-NEXT: csrr a0, vl992; RV32-NEXT: sw a0, 0(a2)993; RV32-NEXT: ret994;995; RV64-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32:996; RV64: # %bb.0: # %entry997; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu998; RV64-NEXT: vle32ff.v v8, (a0), v0.t999; RV64-NEXT: csrr a0, vl1000; RV64-NEXT: sd a0, 0(a2)1001; RV64-NEXT: ret1002entry:1003 %a = call { <vscale x 16 x float>, iXLen } @llvm.riscv.vleff.mask.nxv16f32(1004 <vscale x 16 x float> %0,1005 ptr %1,1006 <vscale x 16 x i1> %2,1007 iXLen %3, iXLen 1)1008 %b = extractvalue { <vscale x 16 x float>, iXLen } %a, 01009 %c = extractvalue { <vscale x 16 x float>, iXLen } %a, 11010 store iXLen %c, ptr %41011 1012 ret <vscale x 16 x float> %b1013}1014 1015define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(ptr %0, iXLen %1, ptr %2) nounwind {1016; RV32-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16:1017; RV32: # %bb.0: # %entry1018; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1019; RV32-NEXT: vle16ff.v v8, (a0)1020; RV32-NEXT: csrr a0, vl1021; RV32-NEXT: sw a0, 0(a2)1022; RV32-NEXT: ret1023;1024; RV64-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16:1025; RV64: # %bb.0: # %entry1026; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1027; RV64-NEXT: vle16ff.v v8, (a0)1028; RV64-NEXT: csrr a0, vl1029; RV64-NEXT: sd a0, 0(a2)1030; RV64-NEXT: ret1031entry:1032 %a = call { <vscale x 1 x i16>, iXLen } @llvm.riscv.vleff.nxv1i16(1033 <vscale x 1 x i16> poison,1034 ptr %0,1035 iXLen %1)1036 %b = extractvalue { <vscale x 1 x i16>, iXLen } %a, 01037 %c = extractvalue { <vscale x 1 x i16>, iXLen } %a, 11038 store iXLen %c, ptr %21039 ret <vscale x 1 x i16> %b1040}1041 1042define <vscale x 1 x i16> @intrinsic_vleff_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {1043; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16:1044; RV32: # %bb.0: # %entry1045; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1046; RV32-NEXT: vle16ff.v v8, (a0), v0.t1047; RV32-NEXT: csrr a0, vl1048; RV32-NEXT: sw a0, 0(a2)1049; RV32-NEXT: ret1050;1051; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16:1052; RV64: # %bb.0: # %entry1053; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1054; RV64-NEXT: vle16ff.v v8, (a0), v0.t1055; RV64-NEXT: csrr a0, vl1056; RV64-NEXT: sd a0, 0(a2)1057; RV64-NEXT: ret1058entry:1059 %a = call { <vscale x 1 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv1i16(1060 <vscale x 1 x i16> %0,1061 ptr %1,1062 <vscale x 1 x i1> %2,1063 iXLen %3, iXLen 1)1064 %b = extractvalue { <vscale x 1 x i16>, iXLen } %a, 01065 %c = extractvalue { <vscale x 1 x i16>, iXLen } %a, 11066 store iXLen %c, ptr %41067 1068 ret <vscale x 1 x i16> %b1069}1070 1071define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(ptr %0, iXLen %1, ptr %2) nounwind {1072; RV32-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16:1073; RV32: # %bb.0: # %entry1074; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1075; RV32-NEXT: vle16ff.v v8, (a0)1076; RV32-NEXT: csrr a0, vl1077; RV32-NEXT: sw a0, 0(a2)1078; RV32-NEXT: ret1079;1080; RV64-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16:1081; RV64: # %bb.0: # %entry1082; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1083; RV64-NEXT: vle16ff.v v8, (a0)1084; RV64-NEXT: csrr a0, vl1085; RV64-NEXT: sd a0, 0(a2)1086; RV64-NEXT: ret1087entry:1088 %a = call { <vscale x 2 x i16>, iXLen } @llvm.riscv.vleff.nxv2i16(1089 <vscale x 2 x i16> poison,1090 ptr %0,1091 iXLen %1)1092 %b = extractvalue { <vscale x 2 x i16>, iXLen } %a, 01093 %c = extractvalue { <vscale x 2 x i16>, iXLen } %a, 11094 store iXLen %c, ptr %21095 ret <vscale x 2 x i16> %b1096}1097 1098define <vscale x 2 x i16> @intrinsic_vleff_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {1099; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16:1100; RV32: # %bb.0: # %entry1101; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1102; RV32-NEXT: vle16ff.v v8, (a0), v0.t1103; RV32-NEXT: csrr a0, vl1104; RV32-NEXT: sw a0, 0(a2)1105; RV32-NEXT: ret1106;1107; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16:1108; RV64: # %bb.0: # %entry1109; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1110; RV64-NEXT: vle16ff.v v8, (a0), v0.t1111; RV64-NEXT: csrr a0, vl1112; RV64-NEXT: sd a0, 0(a2)1113; RV64-NEXT: ret1114entry:1115 %a = call { <vscale x 2 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv2i16(1116 <vscale x 2 x i16> %0,1117 ptr %1,1118 <vscale x 2 x i1> %2,1119 iXLen %3, iXLen 1)1120 %b = extractvalue { <vscale x 2 x i16>, iXLen } %a, 01121 %c = extractvalue { <vscale x 2 x i16>, iXLen } %a, 11122 store iXLen %c, ptr %41123 1124 ret <vscale x 2 x i16> %b1125}1126 1127define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(ptr %0, iXLen %1, ptr %2) nounwind {1128; RV32-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16:1129; RV32: # %bb.0: # %entry1130; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1131; RV32-NEXT: vle16ff.v v8, (a0)1132; RV32-NEXT: csrr a0, vl1133; RV32-NEXT: sw a0, 0(a2)1134; RV32-NEXT: ret1135;1136; RV64-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16:1137; RV64: # %bb.0: # %entry1138; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1139; RV64-NEXT: vle16ff.v v8, (a0)1140; RV64-NEXT: csrr a0, vl1141; RV64-NEXT: sd a0, 0(a2)1142; RV64-NEXT: ret1143entry:1144 %a = call { <vscale x 4 x i16>, iXLen } @llvm.riscv.vleff.nxv4i16(1145 <vscale x 4 x i16> poison,1146 ptr %0,1147 iXLen %1)1148 %b = extractvalue { <vscale x 4 x i16>, iXLen } %a, 01149 %c = extractvalue { <vscale x 4 x i16>, iXLen } %a, 11150 store iXLen %c, ptr %21151 ret <vscale x 4 x i16> %b1152}1153 1154define <vscale x 4 x i16> @intrinsic_vleff_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {1155; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16:1156; RV32: # %bb.0: # %entry1157; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu1158; RV32-NEXT: vle16ff.v v8, (a0), v0.t1159; RV32-NEXT: csrr a0, vl1160; RV32-NEXT: sw a0, 0(a2)1161; RV32-NEXT: ret1162;1163; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16:1164; RV64: # %bb.0: # %entry1165; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu1166; RV64-NEXT: vle16ff.v v8, (a0), v0.t1167; RV64-NEXT: csrr a0, vl1168; RV64-NEXT: sd a0, 0(a2)1169; RV64-NEXT: ret1170entry:1171 %a = call { <vscale x 4 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv4i16(1172 <vscale x 4 x i16> %0,1173 ptr %1,1174 <vscale x 4 x i1> %2,1175 iXLen %3, iXLen 1)1176 %b = extractvalue { <vscale x 4 x i16>, iXLen } %a, 01177 %c = extractvalue { <vscale x 4 x i16>, iXLen } %a, 11178 store iXLen %c, ptr %41179 1180 ret <vscale x 4 x i16> %b1181}1182 1183define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(ptr %0, iXLen %1, ptr %2) nounwind {1184; RV32-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16:1185; RV32: # %bb.0: # %entry1186; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma1187; RV32-NEXT: vle16ff.v v8, (a0)1188; RV32-NEXT: csrr a0, vl1189; RV32-NEXT: sw a0, 0(a2)1190; RV32-NEXT: ret1191;1192; RV64-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16:1193; RV64: # %bb.0: # %entry1194; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma1195; RV64-NEXT: vle16ff.v v8, (a0)1196; RV64-NEXT: csrr a0, vl1197; RV64-NEXT: sd a0, 0(a2)1198; RV64-NEXT: ret1199entry:1200 %a = call { <vscale x 8 x i16>, iXLen } @llvm.riscv.vleff.nxv8i16(1201 <vscale x 8 x i16> poison,1202 ptr %0,1203 iXLen %1)1204 %b = extractvalue { <vscale x 8 x i16>, iXLen } %a, 01205 %c = extractvalue { <vscale x 8 x i16>, iXLen } %a, 11206 store iXLen %c, ptr %21207 ret <vscale x 8 x i16> %b1208}1209 1210define <vscale x 8 x i16> @intrinsic_vleff_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {1211; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16:1212; RV32: # %bb.0: # %entry1213; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu1214; RV32-NEXT: vle16ff.v v8, (a0), v0.t1215; RV32-NEXT: csrr a0, vl1216; RV32-NEXT: sw a0, 0(a2)1217; RV32-NEXT: ret1218;1219; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16:1220; RV64: # %bb.0: # %entry1221; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, mu1222; RV64-NEXT: vle16ff.v v8, (a0), v0.t1223; RV64-NEXT: csrr a0, vl1224; RV64-NEXT: sd a0, 0(a2)1225; RV64-NEXT: ret1226entry:1227 %a = call { <vscale x 8 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv8i16(1228 <vscale x 8 x i16> %0,1229 ptr %1,1230 <vscale x 8 x i1> %2,1231 iXLen %3, iXLen 1)1232 %b = extractvalue { <vscale x 8 x i16>, iXLen } %a, 01233 %c = extractvalue { <vscale x 8 x i16>, iXLen } %a, 11234 store iXLen %c, ptr %41235 1236 ret <vscale x 8 x i16> %b1237}1238 1239define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(ptr %0, iXLen %1, ptr %2) nounwind {1240; RV32-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16:1241; RV32: # %bb.0: # %entry1242; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma1243; RV32-NEXT: vle16ff.v v8, (a0)1244; RV32-NEXT: csrr a0, vl1245; RV32-NEXT: sw a0, 0(a2)1246; RV32-NEXT: ret1247;1248; RV64-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16:1249; RV64: # %bb.0: # %entry1250; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma1251; RV64-NEXT: vle16ff.v v8, (a0)1252; RV64-NEXT: csrr a0, vl1253; RV64-NEXT: sd a0, 0(a2)1254; RV64-NEXT: ret1255entry:1256 %a = call { <vscale x 16 x i16>, iXLen } @llvm.riscv.vleff.nxv16i16(1257 <vscale x 16 x i16> poison,1258 ptr %0,1259 iXLen %1)1260 %b = extractvalue { <vscale x 16 x i16>, iXLen } %a, 01261 %c = extractvalue { <vscale x 16 x i16>, iXLen } %a, 11262 store iXLen %c, ptr %21263 ret <vscale x 16 x i16> %b1264}1265 1266define <vscale x 16 x i16> @intrinsic_vleff_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {1267; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16:1268; RV32: # %bb.0: # %entry1269; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu1270; RV32-NEXT: vle16ff.v v8, (a0), v0.t1271; RV32-NEXT: csrr a0, vl1272; RV32-NEXT: sw a0, 0(a2)1273; RV32-NEXT: ret1274;1275; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16:1276; RV64: # %bb.0: # %entry1277; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu1278; RV64-NEXT: vle16ff.v v8, (a0), v0.t1279; RV64-NEXT: csrr a0, vl1280; RV64-NEXT: sd a0, 0(a2)1281; RV64-NEXT: ret1282entry:1283 %a = call { <vscale x 16 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv16i16(1284 <vscale x 16 x i16> %0,1285 ptr %1,1286 <vscale x 16 x i1> %2,1287 iXLen %3, iXLen 1)1288 %b = extractvalue { <vscale x 16 x i16>, iXLen } %a, 01289 %c = extractvalue { <vscale x 16 x i16>, iXLen } %a, 11290 store iXLen %c, ptr %41291 1292 ret <vscale x 16 x i16> %b1293}1294 1295define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(ptr %0, iXLen %1, ptr %2) nounwind {1296; RV32-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16:1297; RV32: # %bb.0: # %entry1298; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma1299; RV32-NEXT: vle16ff.v v8, (a0)1300; RV32-NEXT: csrr a0, vl1301; RV32-NEXT: sw a0, 0(a2)1302; RV32-NEXT: ret1303;1304; RV64-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16:1305; RV64: # %bb.0: # %entry1306; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma1307; RV64-NEXT: vle16ff.v v8, (a0)1308; RV64-NEXT: csrr a0, vl1309; RV64-NEXT: sd a0, 0(a2)1310; RV64-NEXT: ret1311entry:1312 %a = call { <vscale x 32 x i16>, iXLen } @llvm.riscv.vleff.nxv32i16(1313 <vscale x 32 x i16> poison,1314 ptr %0,1315 iXLen %1)1316 %b = extractvalue { <vscale x 32 x i16>, iXLen } %a, 01317 %c = extractvalue { <vscale x 32 x i16>, iXLen } %a, 11318 store iXLen %c, ptr %21319 ret <vscale x 32 x i16> %b1320}1321 1322define <vscale x 32 x i16> @intrinsic_vleff_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3, ptr %4) nounwind {1323; RV32-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16:1324; RV32: # %bb.0: # %entry1325; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu1326; RV32-NEXT: vle16ff.v v8, (a0), v0.t1327; RV32-NEXT: csrr a0, vl1328; RV32-NEXT: sw a0, 0(a2)1329; RV32-NEXT: ret1330;1331; RV64-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16:1332; RV64: # %bb.0: # %entry1333; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu1334; RV64-NEXT: vle16ff.v v8, (a0), v0.t1335; RV64-NEXT: csrr a0, vl1336; RV64-NEXT: sd a0, 0(a2)1337; RV64-NEXT: ret1338entry:1339 %a = call { <vscale x 32 x i16>, iXLen } @llvm.riscv.vleff.mask.nxv32i16(1340 <vscale x 32 x i16> %0,1341 ptr %1,1342 <vscale x 32 x i1> %2,1343 iXLen %3, iXLen 1)1344 %b = extractvalue { <vscale x 32 x i16>, iXLen } %a, 01345 %c = extractvalue { <vscale x 32 x i16>, iXLen } %a, 11346 store iXLen %c, ptr %41347 1348 ret <vscale x 32 x i16> %b1349}1350 1351define <vscale x 1 x half> @intrinsic_vleff_v_nxv1half_nxv1bf16(ptr %0, iXLen %1, ptr %2) nounwind {1352; RV32-LABEL: intrinsic_vleff_v_nxv1half_nxv1bf16:1353; RV32: # %bb.0: # %entry1354; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1355; RV32-NEXT: vle16ff.v v8, (a0)1356; RV32-NEXT: csrr a0, vl1357; RV32-NEXT: sw a0, 0(a2)1358; RV32-NEXT: ret1359;1360; RV64-LABEL: intrinsic_vleff_v_nxv1half_nxv1bf16:1361; RV64: # %bb.0: # %entry1362; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1363; RV64-NEXT: vle16ff.v v8, (a0)1364; RV64-NEXT: csrr a0, vl1365; RV64-NEXT: sd a0, 0(a2)1366; RV64-NEXT: ret1367entry:1368 %a = call { <vscale x 1 x half>, iXLen } @llvm.riscv.vleff.nxv1bf16(1369 <vscale x 1 x half> poison,1370 ptr %0,1371 iXLen %1)1372 %b = extractvalue { <vscale x 1 x half>, iXLen } %a, 01373 %c = extractvalue { <vscale x 1 x half>, iXLen } %a, 11374 store iXLen %c, ptr %21375 ret <vscale x 1 x half> %b1376}1377 1378define <vscale x 1 x half> @intrinsic_vleff_mask_v_nxv1half_nxv1bf16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {1379; RV32-LABEL: intrinsic_vleff_mask_v_nxv1half_nxv1bf16:1380; RV32: # %bb.0: # %entry1381; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1382; RV32-NEXT: vle16ff.v v8, (a0), v0.t1383; RV32-NEXT: csrr a0, vl1384; RV32-NEXT: sw a0, 0(a2)1385; RV32-NEXT: ret1386;1387; RV64-LABEL: intrinsic_vleff_mask_v_nxv1half_nxv1bf16:1388; RV64: # %bb.0: # %entry1389; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1390; RV64-NEXT: vle16ff.v v8, (a0), v0.t1391; RV64-NEXT: csrr a0, vl1392; RV64-NEXT: sd a0, 0(a2)1393; RV64-NEXT: ret1394entry:1395 %a = call { <vscale x 1 x half>, iXLen } @llvm.riscv.vleff.mask.nxv1bf16(1396 <vscale x 1 x half> %0,1397 ptr %1,1398 <vscale x 1 x i1> %2,1399 iXLen %3, iXLen 1)1400 %b = extractvalue { <vscale x 1 x half>, iXLen } %a, 01401 %c = extractvalue { <vscale x 1 x half>, iXLen } %a, 11402 store iXLen %c, ptr %41403 1404 ret <vscale x 1 x half> %b1405}1406 1407define <vscale x 2 x half> @intrinsic_vleff_v_nxv2half_nxv2bf16(ptr %0, iXLen %1, ptr %2) nounwind {1408; RV32-LABEL: intrinsic_vleff_v_nxv2half_nxv2bf16:1409; RV32: # %bb.0: # %entry1410; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1411; RV32-NEXT: vle16ff.v v8, (a0)1412; RV32-NEXT: csrr a0, vl1413; RV32-NEXT: sw a0, 0(a2)1414; RV32-NEXT: ret1415;1416; RV64-LABEL: intrinsic_vleff_v_nxv2half_nxv2bf16:1417; RV64: # %bb.0: # %entry1418; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1419; RV64-NEXT: vle16ff.v v8, (a0)1420; RV64-NEXT: csrr a0, vl1421; RV64-NEXT: sd a0, 0(a2)1422; RV64-NEXT: ret1423entry:1424 %a = call { <vscale x 2 x half>, iXLen } @llvm.riscv.vleff.nxv2bf16(1425 <vscale x 2 x half> poison,1426 ptr %0,1427 iXLen %1)1428 %b = extractvalue { <vscale x 2 x half>, iXLen } %a, 01429 %c = extractvalue { <vscale x 2 x half>, iXLen } %a, 11430 store iXLen %c, ptr %21431 ret <vscale x 2 x half> %b1432}1433 1434define <vscale x 2 x half> @intrinsic_vleff_mask_v_nxv2half_nxv2bf16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {1435; RV32-LABEL: intrinsic_vleff_mask_v_nxv2half_nxv2bf16:1436; RV32: # %bb.0: # %entry1437; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1438; RV32-NEXT: vle16ff.v v8, (a0), v0.t1439; RV32-NEXT: csrr a0, vl1440; RV32-NEXT: sw a0, 0(a2)1441; RV32-NEXT: ret1442;1443; RV64-LABEL: intrinsic_vleff_mask_v_nxv2half_nxv2bf16:1444; RV64: # %bb.0: # %entry1445; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1446; RV64-NEXT: vle16ff.v v8, (a0), v0.t1447; RV64-NEXT: csrr a0, vl1448; RV64-NEXT: sd a0, 0(a2)1449; RV64-NEXT: ret1450entry:1451 %a = call { <vscale x 2 x half>, iXLen } @llvm.riscv.vleff.mask.nxv2bf16(1452 <vscale x 2 x half> %0,1453 ptr %1,1454 <vscale x 2 x i1> %2,1455 iXLen %3, iXLen 1)1456 %b = extractvalue { <vscale x 2 x half>, iXLen } %a, 01457 %c = extractvalue { <vscale x 2 x half>, iXLen } %a, 11458 store iXLen %c, ptr %41459 1460 ret <vscale x 2 x half> %b1461}1462 1463define <vscale x 4 x half> @intrinsic_vleff_v_nxv4half_nxv4bf16(ptr %0, iXLen %1, ptr %2) nounwind {1464; RV32-LABEL: intrinsic_vleff_v_nxv4half_nxv4bf16:1465; RV32: # %bb.0: # %entry1466; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1467; RV32-NEXT: vle16ff.v v8, (a0)1468; RV32-NEXT: csrr a0, vl1469; RV32-NEXT: sw a0, 0(a2)1470; RV32-NEXT: ret1471;1472; RV64-LABEL: intrinsic_vleff_v_nxv4half_nxv4bf16:1473; RV64: # %bb.0: # %entry1474; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1475; RV64-NEXT: vle16ff.v v8, (a0)1476; RV64-NEXT: csrr a0, vl1477; RV64-NEXT: sd a0, 0(a2)1478; RV64-NEXT: ret1479entry:1480 %a = call { <vscale x 4 x half>, iXLen } @llvm.riscv.vleff.nxv4bf16(1481 <vscale x 4 x half> poison,1482 ptr %0,1483 iXLen %1)1484 %b = extractvalue { <vscale x 4 x half>, iXLen } %a, 01485 %c = extractvalue { <vscale x 4 x half>, iXLen } %a, 11486 store iXLen %c, ptr %21487 ret <vscale x 4 x half> %b1488}1489 1490define <vscale x 4 x half> @intrinsic_vleff_mask_v_nxv4half_nxv4bf16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {1491; RV32-LABEL: intrinsic_vleff_mask_v_nxv4half_nxv4bf16:1492; RV32: # %bb.0: # %entry1493; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu1494; RV32-NEXT: vle16ff.v v8, (a0), v0.t1495; RV32-NEXT: csrr a0, vl1496; RV32-NEXT: sw a0, 0(a2)1497; RV32-NEXT: ret1498;1499; RV64-LABEL: intrinsic_vleff_mask_v_nxv4half_nxv4bf16:1500; RV64: # %bb.0: # %entry1501; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu1502; RV64-NEXT: vle16ff.v v8, (a0), v0.t1503; RV64-NEXT: csrr a0, vl1504; RV64-NEXT: sd a0, 0(a2)1505; RV64-NEXT: ret1506entry:1507 %a = call { <vscale x 4 x half>, iXLen } @llvm.riscv.vleff.mask.nxv4bf16(1508 <vscale x 4 x half> %0,1509 ptr %1,1510 <vscale x 4 x i1> %2,1511 iXLen %3, iXLen 1)1512 %b = extractvalue { <vscale x 4 x half>, iXLen } %a, 01513 %c = extractvalue { <vscale x 4 x half>, iXLen } %a, 11514 store iXLen %c, ptr %41515 1516 ret <vscale x 4 x half> %b1517}1518 1519define <vscale x 8 x half> @intrinsic_vleff_v_nxv8half_nxv8bf16(ptr %0, iXLen %1, ptr %2) nounwind {1520; RV32-LABEL: intrinsic_vleff_v_nxv8half_nxv8bf16:1521; RV32: # %bb.0: # %entry1522; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma1523; RV32-NEXT: vle16ff.v v8, (a0)1524; RV32-NEXT: csrr a0, vl1525; RV32-NEXT: sw a0, 0(a2)1526; RV32-NEXT: ret1527;1528; RV64-LABEL: intrinsic_vleff_v_nxv8half_nxv8bf16:1529; RV64: # %bb.0: # %entry1530; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma1531; RV64-NEXT: vle16ff.v v8, (a0)1532; RV64-NEXT: csrr a0, vl1533; RV64-NEXT: sd a0, 0(a2)1534; RV64-NEXT: ret1535entry:1536 %a = call { <vscale x 8 x half>, iXLen } @llvm.riscv.vleff.nxv8bf16(1537 <vscale x 8 x half> poison,1538 ptr %0,1539 iXLen %1)1540 %b = extractvalue { <vscale x 8 x half>, iXLen } %a, 01541 %c = extractvalue { <vscale x 8 x half>, iXLen } %a, 11542 store iXLen %c, ptr %21543 ret <vscale x 8 x half> %b1544}1545 1546define <vscale x 8 x half> @intrinsic_vleff_mask_v_nxv8half_nxv8bf16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {1547; RV32-LABEL: intrinsic_vleff_mask_v_nxv8half_nxv8bf16:1548; RV32: # %bb.0: # %entry1549; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu1550; RV32-NEXT: vle16ff.v v8, (a0), v0.t1551; RV32-NEXT: csrr a0, vl1552; RV32-NEXT: sw a0, 0(a2)1553; RV32-NEXT: ret1554;1555; RV64-LABEL: intrinsic_vleff_mask_v_nxv8half_nxv8bf16:1556; RV64: # %bb.0: # %entry1557; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, mu1558; RV64-NEXT: vle16ff.v v8, (a0), v0.t1559; RV64-NEXT: csrr a0, vl1560; RV64-NEXT: sd a0, 0(a2)1561; RV64-NEXT: ret1562entry:1563 %a = call { <vscale x 8 x half>, iXLen } @llvm.riscv.vleff.mask.nxv8bf16(1564 <vscale x 8 x half> %0,1565 ptr %1,1566 <vscale x 8 x i1> %2,1567 iXLen %3, iXLen 1)1568 %b = extractvalue { <vscale x 8 x half>, iXLen } %a, 01569 %c = extractvalue { <vscale x 8 x half>, iXLen } %a, 11570 store iXLen %c, ptr %41571 1572 ret <vscale x 8 x half> %b1573}1574 1575define <vscale x 16 x half> @intrinsic_vleff_v_nxv16half_nxv16bf16(ptr %0, iXLen %1, ptr %2) nounwind {1576; RV32-LABEL: intrinsic_vleff_v_nxv16half_nxv16bf16:1577; RV32: # %bb.0: # %entry1578; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma1579; RV32-NEXT: vle16ff.v v8, (a0)1580; RV32-NEXT: csrr a0, vl1581; RV32-NEXT: sw a0, 0(a2)1582; RV32-NEXT: ret1583;1584; RV64-LABEL: intrinsic_vleff_v_nxv16half_nxv16bf16:1585; RV64: # %bb.0: # %entry1586; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma1587; RV64-NEXT: vle16ff.v v8, (a0)1588; RV64-NEXT: csrr a0, vl1589; RV64-NEXT: sd a0, 0(a2)1590; RV64-NEXT: ret1591entry:1592 %a = call { <vscale x 16 x half>, iXLen } @llvm.riscv.vleff.nxv16bf16(1593 <vscale x 16 x half> poison,1594 ptr %0,1595 iXLen %1)1596 %b = extractvalue { <vscale x 16 x half>, iXLen } %a, 01597 %c = extractvalue { <vscale x 16 x half>, iXLen } %a, 11598 store iXLen %c, ptr %21599 ret <vscale x 16 x half> %b1600}1601 1602define <vscale x 16 x half> @intrinsic_vleff_mask_v_nxv16half_nxv16bf16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {1603; RV32-LABEL: intrinsic_vleff_mask_v_nxv16half_nxv16bf16:1604; RV32: # %bb.0: # %entry1605; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu1606; RV32-NEXT: vle16ff.v v8, (a0), v0.t1607; RV32-NEXT: csrr a0, vl1608; RV32-NEXT: sw a0, 0(a2)1609; RV32-NEXT: ret1610;1611; RV64-LABEL: intrinsic_vleff_mask_v_nxv16half_nxv16bf16:1612; RV64: # %bb.0: # %entry1613; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu1614; RV64-NEXT: vle16ff.v v8, (a0), v0.t1615; RV64-NEXT: csrr a0, vl1616; RV64-NEXT: sd a0, 0(a2)1617; RV64-NEXT: ret1618entry:1619 %a = call { <vscale x 16 x half>, iXLen } @llvm.riscv.vleff.mask.nxv16bf16(1620 <vscale x 16 x half> %0,1621 ptr %1,1622 <vscale x 16 x i1> %2,1623 iXLen %3, iXLen 1)1624 %b = extractvalue { <vscale x 16 x half>, iXLen } %a, 01625 %c = extractvalue { <vscale x 16 x half>, iXLen } %a, 11626 store iXLen %c, ptr %41627 1628 ret <vscale x 16 x half> %b1629}1630 1631define <vscale x 32 x half> @intrinsic_vleff_v_nxv32half_nxv32bf16(ptr %0, iXLen %1, ptr %2) nounwind {1632; RV32-LABEL: intrinsic_vleff_v_nxv32half_nxv32bf16:1633; RV32: # %bb.0: # %entry1634; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma1635; RV32-NEXT: vle16ff.v v8, (a0)1636; RV32-NEXT: csrr a0, vl1637; RV32-NEXT: sw a0, 0(a2)1638; RV32-NEXT: ret1639;1640; RV64-LABEL: intrinsic_vleff_v_nxv32half_nxv32bf16:1641; RV64: # %bb.0: # %entry1642; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma1643; RV64-NEXT: vle16ff.v v8, (a0)1644; RV64-NEXT: csrr a0, vl1645; RV64-NEXT: sd a0, 0(a2)1646; RV64-NEXT: ret1647entry:1648 %a = call { <vscale x 32 x half>, iXLen } @llvm.riscv.vleff.nxv32bf16(1649 <vscale x 32 x half> poison,1650 ptr %0,1651 iXLen %1)1652 %b = extractvalue { <vscale x 32 x half>, iXLen } %a, 01653 %c = extractvalue { <vscale x 32 x half>, iXLen } %a, 11654 store iXLen %c, ptr %21655 ret <vscale x 32 x half> %b1656}1657 1658define <vscale x 32 x half> @intrinsic_vleff_mask_v_nxv32half_nxv32bf16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3, ptr %4) nounwind {1659; RV32-LABEL: intrinsic_vleff_mask_v_nxv32half_nxv32bf16:1660; RV32: # %bb.0: # %entry1661; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu1662; RV32-NEXT: vle16ff.v v8, (a0), v0.t1663; RV32-NEXT: csrr a0, vl1664; RV32-NEXT: sw a0, 0(a2)1665; RV32-NEXT: ret1666;1667; RV64-LABEL: intrinsic_vleff_mask_v_nxv32half_nxv32bf16:1668; RV64: # %bb.0: # %entry1669; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu1670; RV64-NEXT: vle16ff.v v8, (a0), v0.t1671; RV64-NEXT: csrr a0, vl1672; RV64-NEXT: sd a0, 0(a2)1673; RV64-NEXT: ret1674entry:1675 %a = call { <vscale x 32 x half>, iXLen } @llvm.riscv.vleff.mask.nxv32bf16(1676 <vscale x 32 x half> %0,1677 ptr %1,1678 <vscale x 32 x i1> %2,1679 iXLen %3, iXLen 1)1680 %b = extractvalue { <vscale x 32 x half>, iXLen } %a, 01681 %c = extractvalue { <vscale x 32 x half>, iXLen } %a, 11682 store iXLen %c, ptr %41683 1684 ret <vscale x 32 x half> %b1685}1686 1687define <vscale x 1 x bfloat> @intrinsic_vleff_v_nxv1bfloat_nxv1f16(ptr %0, iXLen %1, ptr %2) nounwind {1688; RV32-LABEL: intrinsic_vleff_v_nxv1bfloat_nxv1f16:1689; RV32: # %bb.0: # %entry1690; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1691; RV32-NEXT: vle16ff.v v8, (a0)1692; RV32-NEXT: csrr a0, vl1693; RV32-NEXT: sw a0, 0(a2)1694; RV32-NEXT: ret1695;1696; RV64-LABEL: intrinsic_vleff_v_nxv1bfloat_nxv1f16:1697; RV64: # %bb.0: # %entry1698; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1699; RV64-NEXT: vle16ff.v v8, (a0)1700; RV64-NEXT: csrr a0, vl1701; RV64-NEXT: sd a0, 0(a2)1702; RV64-NEXT: ret1703entry:1704 %a = call { <vscale x 1 x bfloat>, iXLen } @llvm.riscv.vleff.nxv1f16(1705 <vscale x 1 x bfloat> poison,1706 ptr %0,1707 iXLen %1)1708 %b = extractvalue { <vscale x 1 x bfloat>, iXLen } %a, 01709 %c = extractvalue { <vscale x 1 x bfloat>, iXLen } %a, 11710 store iXLen %c, ptr %21711 ret <vscale x 1 x bfloat> %b1712}1713 1714define <vscale x 1 x bfloat> @intrinsic_vleff_mask_v_nxv1bfloat_nxv1f16(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {1715; RV32-LABEL: intrinsic_vleff_mask_v_nxv1bfloat_nxv1f16:1716; RV32: # %bb.0: # %entry1717; RV32-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1718; RV32-NEXT: vle16ff.v v8, (a0), v0.t1719; RV32-NEXT: csrr a0, vl1720; RV32-NEXT: sw a0, 0(a2)1721; RV32-NEXT: ret1722;1723; RV64-LABEL: intrinsic_vleff_mask_v_nxv1bfloat_nxv1f16:1724; RV64: # %bb.0: # %entry1725; RV64-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1726; RV64-NEXT: vle16ff.v v8, (a0), v0.t1727; RV64-NEXT: csrr a0, vl1728; RV64-NEXT: sd a0, 0(a2)1729; RV64-NEXT: ret1730entry:1731 %a = call { <vscale x 1 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv1f16(1732 <vscale x 1 x bfloat> %0,1733 ptr %1,1734 <vscale x 1 x i1> %2,1735 iXLen %3, iXLen 1)1736 %b = extractvalue { <vscale x 1 x bfloat>, iXLen } %a, 01737 %c = extractvalue { <vscale x 1 x bfloat>, iXLen } %a, 11738 store iXLen %c, ptr %41739 1740 ret <vscale x 1 x bfloat> %b1741}1742 1743define <vscale x 2 x bfloat> @intrinsic_vleff_v_nxv2bfloat_nxv2f16(ptr %0, iXLen %1, ptr %2) nounwind {1744; RV32-LABEL: intrinsic_vleff_v_nxv2bfloat_nxv2f16:1745; RV32: # %bb.0: # %entry1746; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1747; RV32-NEXT: vle16ff.v v8, (a0)1748; RV32-NEXT: csrr a0, vl1749; RV32-NEXT: sw a0, 0(a2)1750; RV32-NEXT: ret1751;1752; RV64-LABEL: intrinsic_vleff_v_nxv2bfloat_nxv2f16:1753; RV64: # %bb.0: # %entry1754; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1755; RV64-NEXT: vle16ff.v v8, (a0)1756; RV64-NEXT: csrr a0, vl1757; RV64-NEXT: sd a0, 0(a2)1758; RV64-NEXT: ret1759entry:1760 %a = call { <vscale x 2 x bfloat>, iXLen } @llvm.riscv.vleff.nxv2f16(1761 <vscale x 2 x bfloat> poison,1762 ptr %0,1763 iXLen %1)1764 %b = extractvalue { <vscale x 2 x bfloat>, iXLen } %a, 01765 %c = extractvalue { <vscale x 2 x bfloat>, iXLen } %a, 11766 store iXLen %c, ptr %21767 ret <vscale x 2 x bfloat> %b1768}1769 1770define <vscale x 2 x bfloat> @intrinsic_vleff_mask_v_nxv2bfloat_nxv2f16(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {1771; RV32-LABEL: intrinsic_vleff_mask_v_nxv2bfloat_nxv2f16:1772; RV32: # %bb.0: # %entry1773; RV32-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1774; RV32-NEXT: vle16ff.v v8, (a0), v0.t1775; RV32-NEXT: csrr a0, vl1776; RV32-NEXT: sw a0, 0(a2)1777; RV32-NEXT: ret1778;1779; RV64-LABEL: intrinsic_vleff_mask_v_nxv2bfloat_nxv2f16:1780; RV64: # %bb.0: # %entry1781; RV64-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1782; RV64-NEXT: vle16ff.v v8, (a0), v0.t1783; RV64-NEXT: csrr a0, vl1784; RV64-NEXT: sd a0, 0(a2)1785; RV64-NEXT: ret1786entry:1787 %a = call { <vscale x 2 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv2f16(1788 <vscale x 2 x bfloat> %0,1789 ptr %1,1790 <vscale x 2 x i1> %2,1791 iXLen %3, iXLen 1)1792 %b = extractvalue { <vscale x 2 x bfloat>, iXLen } %a, 01793 %c = extractvalue { <vscale x 2 x bfloat>, iXLen } %a, 11794 store iXLen %c, ptr %41795 1796 ret <vscale x 2 x bfloat> %b1797}1798 1799define <vscale x 4 x bfloat> @intrinsic_vleff_v_nxv4bfloat_nxv4f16(ptr %0, iXLen %1, ptr %2) nounwind {1800; RV32-LABEL: intrinsic_vleff_v_nxv4bfloat_nxv4f16:1801; RV32: # %bb.0: # %entry1802; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, ma1803; RV32-NEXT: vle16ff.v v8, (a0)1804; RV32-NEXT: csrr a0, vl1805; RV32-NEXT: sw a0, 0(a2)1806; RV32-NEXT: ret1807;1808; RV64-LABEL: intrinsic_vleff_v_nxv4bfloat_nxv4f16:1809; RV64: # %bb.0: # %entry1810; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, ma1811; RV64-NEXT: vle16ff.v v8, (a0)1812; RV64-NEXT: csrr a0, vl1813; RV64-NEXT: sd a0, 0(a2)1814; RV64-NEXT: ret1815entry:1816 %a = call { <vscale x 4 x bfloat>, iXLen } @llvm.riscv.vleff.nxv4f16(1817 <vscale x 4 x bfloat> poison,1818 ptr %0,1819 iXLen %1)1820 %b = extractvalue { <vscale x 4 x bfloat>, iXLen } %a, 01821 %c = extractvalue { <vscale x 4 x bfloat>, iXLen } %a, 11822 store iXLen %c, ptr %21823 ret <vscale x 4 x bfloat> %b1824}1825 1826define <vscale x 4 x bfloat> @intrinsic_vleff_mask_v_nxv4bfloat_nxv4f16(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {1827; RV32-LABEL: intrinsic_vleff_mask_v_nxv4bfloat_nxv4f16:1828; RV32: # %bb.0: # %entry1829; RV32-NEXT: vsetvli zero, a1, e16, m1, ta, mu1830; RV32-NEXT: vle16ff.v v8, (a0), v0.t1831; RV32-NEXT: csrr a0, vl1832; RV32-NEXT: sw a0, 0(a2)1833; RV32-NEXT: ret1834;1835; RV64-LABEL: intrinsic_vleff_mask_v_nxv4bfloat_nxv4f16:1836; RV64: # %bb.0: # %entry1837; RV64-NEXT: vsetvli zero, a1, e16, m1, ta, mu1838; RV64-NEXT: vle16ff.v v8, (a0), v0.t1839; RV64-NEXT: csrr a0, vl1840; RV64-NEXT: sd a0, 0(a2)1841; RV64-NEXT: ret1842entry:1843 %a = call { <vscale x 4 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv4f16(1844 <vscale x 4 x bfloat> %0,1845 ptr %1,1846 <vscale x 4 x i1> %2,1847 iXLen %3, iXLen 1)1848 %b = extractvalue { <vscale x 4 x bfloat>, iXLen } %a, 01849 %c = extractvalue { <vscale x 4 x bfloat>, iXLen } %a, 11850 store iXLen %c, ptr %41851 1852 ret <vscale x 4 x bfloat> %b1853}1854 1855define <vscale x 8 x bfloat> @intrinsic_vleff_v_nxv8bfloat_nxv8f16(ptr %0, iXLen %1, ptr %2) nounwind {1856; RV32-LABEL: intrinsic_vleff_v_nxv8bfloat_nxv8f16:1857; RV32: # %bb.0: # %entry1858; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, ma1859; RV32-NEXT: vle16ff.v v8, (a0)1860; RV32-NEXT: csrr a0, vl1861; RV32-NEXT: sw a0, 0(a2)1862; RV32-NEXT: ret1863;1864; RV64-LABEL: intrinsic_vleff_v_nxv8bfloat_nxv8f16:1865; RV64: # %bb.0: # %entry1866; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma1867; RV64-NEXT: vle16ff.v v8, (a0)1868; RV64-NEXT: csrr a0, vl1869; RV64-NEXT: sd a0, 0(a2)1870; RV64-NEXT: ret1871entry:1872 %a = call { <vscale x 8 x bfloat>, iXLen } @llvm.riscv.vleff.nxv8f16(1873 <vscale x 8 x bfloat> poison,1874 ptr %0,1875 iXLen %1)1876 %b = extractvalue { <vscale x 8 x bfloat>, iXLen } %a, 01877 %c = extractvalue { <vscale x 8 x bfloat>, iXLen } %a, 11878 store iXLen %c, ptr %21879 ret <vscale x 8 x bfloat> %b1880}1881 1882define <vscale x 8 x bfloat> @intrinsic_vleff_mask_v_nxv8bfloat_nxv8f16(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {1883; RV32-LABEL: intrinsic_vleff_mask_v_nxv8bfloat_nxv8f16:1884; RV32: # %bb.0: # %entry1885; RV32-NEXT: vsetvli zero, a1, e16, m2, ta, mu1886; RV32-NEXT: vle16ff.v v8, (a0), v0.t1887; RV32-NEXT: csrr a0, vl1888; RV32-NEXT: sw a0, 0(a2)1889; RV32-NEXT: ret1890;1891; RV64-LABEL: intrinsic_vleff_mask_v_nxv8bfloat_nxv8f16:1892; RV64: # %bb.0: # %entry1893; RV64-NEXT: vsetvli zero, a1, e16, m2, ta, mu1894; RV64-NEXT: vle16ff.v v8, (a0), v0.t1895; RV64-NEXT: csrr a0, vl1896; RV64-NEXT: sd a0, 0(a2)1897; RV64-NEXT: ret1898entry:1899 %a = call { <vscale x 8 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv8f16(1900 <vscale x 8 x bfloat> %0,1901 ptr %1,1902 <vscale x 8 x i1> %2,1903 iXLen %3, iXLen 1)1904 %b = extractvalue { <vscale x 8 x bfloat>, iXLen } %a, 01905 %c = extractvalue { <vscale x 8 x bfloat>, iXLen } %a, 11906 store iXLen %c, ptr %41907 1908 ret <vscale x 8 x bfloat> %b1909}1910 1911define <vscale x 16 x bfloat> @intrinsic_vleff_v_nxv16bfloat_nxv16f16(ptr %0, iXLen %1, ptr %2) nounwind {1912; RV32-LABEL: intrinsic_vleff_v_nxv16bfloat_nxv16f16:1913; RV32: # %bb.0: # %entry1914; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma1915; RV32-NEXT: vle16ff.v v8, (a0)1916; RV32-NEXT: csrr a0, vl1917; RV32-NEXT: sw a0, 0(a2)1918; RV32-NEXT: ret1919;1920; RV64-LABEL: intrinsic_vleff_v_nxv16bfloat_nxv16f16:1921; RV64: # %bb.0: # %entry1922; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma1923; RV64-NEXT: vle16ff.v v8, (a0)1924; RV64-NEXT: csrr a0, vl1925; RV64-NEXT: sd a0, 0(a2)1926; RV64-NEXT: ret1927entry:1928 %a = call { <vscale x 16 x bfloat>, iXLen } @llvm.riscv.vleff.nxv16f16(1929 <vscale x 16 x bfloat> poison,1930 ptr %0,1931 iXLen %1)1932 %b = extractvalue { <vscale x 16 x bfloat>, iXLen } %a, 01933 %c = extractvalue { <vscale x 16 x bfloat>, iXLen } %a, 11934 store iXLen %c, ptr %21935 ret <vscale x 16 x bfloat> %b1936}1937 1938define <vscale x 16 x bfloat> @intrinsic_vleff_mask_v_nxv16bfloat_nxv16f16(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {1939; RV32-LABEL: intrinsic_vleff_mask_v_nxv16bfloat_nxv16f16:1940; RV32: # %bb.0: # %entry1941; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu1942; RV32-NEXT: vle16ff.v v8, (a0), v0.t1943; RV32-NEXT: csrr a0, vl1944; RV32-NEXT: sw a0, 0(a2)1945; RV32-NEXT: ret1946;1947; RV64-LABEL: intrinsic_vleff_mask_v_nxv16bfloat_nxv16f16:1948; RV64: # %bb.0: # %entry1949; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu1950; RV64-NEXT: vle16ff.v v8, (a0), v0.t1951; RV64-NEXT: csrr a0, vl1952; RV64-NEXT: sd a0, 0(a2)1953; RV64-NEXT: ret1954entry:1955 %a = call { <vscale x 16 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv16f16(1956 <vscale x 16 x bfloat> %0,1957 ptr %1,1958 <vscale x 16 x i1> %2,1959 iXLen %3, iXLen 1)1960 %b = extractvalue { <vscale x 16 x bfloat>, iXLen } %a, 01961 %c = extractvalue { <vscale x 16 x bfloat>, iXLen } %a, 11962 store iXLen %c, ptr %41963 1964 ret <vscale x 16 x bfloat> %b1965}1966 1967define <vscale x 32 x bfloat> @intrinsic_vleff_v_nxv32bfloat_nxv32f16(ptr %0, iXLen %1, ptr %2) nounwind {1968; RV32-LABEL: intrinsic_vleff_v_nxv32bfloat_nxv32f16:1969; RV32: # %bb.0: # %entry1970; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma1971; RV32-NEXT: vle16ff.v v8, (a0)1972; RV32-NEXT: csrr a0, vl1973; RV32-NEXT: sw a0, 0(a2)1974; RV32-NEXT: ret1975;1976; RV64-LABEL: intrinsic_vleff_v_nxv32bfloat_nxv32f16:1977; RV64: # %bb.0: # %entry1978; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, ma1979; RV64-NEXT: vle16ff.v v8, (a0)1980; RV64-NEXT: csrr a0, vl1981; RV64-NEXT: sd a0, 0(a2)1982; RV64-NEXT: ret1983entry:1984 %a = call { <vscale x 32 x bfloat>, iXLen } @llvm.riscv.vleff.nxv32f16(1985 <vscale x 32 x bfloat> poison,1986 ptr %0,1987 iXLen %1)1988 %b = extractvalue { <vscale x 32 x bfloat>, iXLen } %a, 01989 %c = extractvalue { <vscale x 32 x bfloat>, iXLen } %a, 11990 store iXLen %c, ptr %21991 ret <vscale x 32 x bfloat> %b1992}1993 1994define <vscale x 32 x bfloat> @intrinsic_vleff_mask_v_nxv32bfloat_nxv32f16(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3, ptr %4) nounwind {1995; RV32-LABEL: intrinsic_vleff_mask_v_nxv32bfloat_nxv32f16:1996; RV32: # %bb.0: # %entry1997; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu1998; RV32-NEXT: vle16ff.v v8, (a0), v0.t1999; RV32-NEXT: csrr a0, vl2000; RV32-NEXT: sw a0, 0(a2)2001; RV32-NEXT: ret2002;2003; RV64-LABEL: intrinsic_vleff_mask_v_nxv32bfloat_nxv32f16:2004; RV64: # %bb.0: # %entry2005; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu2006; RV64-NEXT: vle16ff.v v8, (a0), v0.t2007; RV64-NEXT: csrr a0, vl2008; RV64-NEXT: sd a0, 0(a2)2009; RV64-NEXT: ret2010entry:2011 %a = call { <vscale x 32 x bfloat>, iXLen } @llvm.riscv.vleff.mask.nxv32f16(2012 <vscale x 32 x bfloat> %0,2013 ptr %1,2014 <vscale x 32 x i1> %2,2015 iXLen %3, iXLen 1)2016 %b = extractvalue { <vscale x 32 x bfloat>, iXLen } %a, 02017 %c = extractvalue { <vscale x 32 x bfloat>, iXLen } %a, 12018 store iXLen %c, ptr %42019 2020 ret <vscale x 32 x bfloat> %b2021}2022 2023define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(ptr %0, iXLen %1, ptr %2) nounwind {2024; RV32-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8:2025; RV32: # %bb.0: # %entry2026; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2027; RV32-NEXT: vle8ff.v v8, (a0)2028; RV32-NEXT: csrr a0, vl2029; RV32-NEXT: sw a0, 0(a2)2030; RV32-NEXT: ret2031;2032; RV64-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8:2033; RV64: # %bb.0: # %entry2034; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2035; RV64-NEXT: vle8ff.v v8, (a0)2036; RV64-NEXT: csrr a0, vl2037; RV64-NEXT: sd a0, 0(a2)2038; RV64-NEXT: ret2039entry:2040 %a = call { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff.nxv1i8(2041 <vscale x 1 x i8> poison,2042 ptr %0,2043 iXLen %1)2044 %b = extractvalue { <vscale x 1 x i8>, iXLen } %a, 02045 %c = extractvalue { <vscale x 1 x i8>, iXLen } %a, 12046 store iXLen %c, ptr %22047 ret <vscale x 1 x i8> %b2048}2049 2050define <vscale x 1 x i8> @intrinsic_vleff_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {2051; RV32-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8:2052; RV32: # %bb.0: # %entry2053; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, mu2054; RV32-NEXT: vle8ff.v v8, (a0), v0.t2055; RV32-NEXT: csrr a0, vl2056; RV32-NEXT: sw a0, 0(a2)2057; RV32-NEXT: ret2058;2059; RV64-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8:2060; RV64: # %bb.0: # %entry2061; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, mu2062; RV64-NEXT: vle8ff.v v8, (a0), v0.t2063; RV64-NEXT: csrr a0, vl2064; RV64-NEXT: sd a0, 0(a2)2065; RV64-NEXT: ret2066entry:2067 %a = call { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv1i8(2068 <vscale x 1 x i8> %0,2069 ptr %1,2070 <vscale x 1 x i1> %2,2071 iXLen %3, iXLen 1)2072 %b = extractvalue { <vscale x 1 x i8>, iXLen } %a, 02073 %c = extractvalue { <vscale x 1 x i8>, iXLen } %a, 12074 store iXLen %c, ptr %42075 2076 ret <vscale x 1 x i8> %b2077}2078 2079define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(ptr %0, iXLen %1, ptr %2) nounwind {2080; RV32-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8:2081; RV32: # %bb.0: # %entry2082; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2083; RV32-NEXT: vle8ff.v v8, (a0)2084; RV32-NEXT: csrr a0, vl2085; RV32-NEXT: sw a0, 0(a2)2086; RV32-NEXT: ret2087;2088; RV64-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8:2089; RV64: # %bb.0: # %entry2090; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2091; RV64-NEXT: vle8ff.v v8, (a0)2092; RV64-NEXT: csrr a0, vl2093; RV64-NEXT: sd a0, 0(a2)2094; RV64-NEXT: ret2095entry:2096 %a = call { <vscale x 2 x i8>, iXLen } @llvm.riscv.vleff.nxv2i8(2097 <vscale x 2 x i8> poison,2098 ptr %0,2099 iXLen %1)2100 %b = extractvalue { <vscale x 2 x i8>, iXLen } %a, 02101 %c = extractvalue { <vscale x 2 x i8>, iXLen } %a, 12102 store iXLen %c, ptr %22103 ret <vscale x 2 x i8> %b2104}2105 2106define <vscale x 2 x i8> @intrinsic_vleff_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3, ptr %4) nounwind {2107; RV32-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8:2108; RV32: # %bb.0: # %entry2109; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, mu2110; RV32-NEXT: vle8ff.v v8, (a0), v0.t2111; RV32-NEXT: csrr a0, vl2112; RV32-NEXT: sw a0, 0(a2)2113; RV32-NEXT: ret2114;2115; RV64-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8:2116; RV64: # %bb.0: # %entry2117; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, mu2118; RV64-NEXT: vle8ff.v v8, (a0), v0.t2119; RV64-NEXT: csrr a0, vl2120; RV64-NEXT: sd a0, 0(a2)2121; RV64-NEXT: ret2122entry:2123 %a = call { <vscale x 2 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv2i8(2124 <vscale x 2 x i8> %0,2125 ptr %1,2126 <vscale x 2 x i1> %2,2127 iXLen %3, iXLen 1)2128 %b = extractvalue { <vscale x 2 x i8>, iXLen } %a, 02129 %c = extractvalue { <vscale x 2 x i8>, iXLen } %a, 12130 store iXLen %c, ptr %42131 2132 ret <vscale x 2 x i8> %b2133}2134 2135define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(ptr %0, iXLen %1, ptr %2) nounwind {2136; RV32-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8:2137; RV32: # %bb.0: # %entry2138; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2139; RV32-NEXT: vle8ff.v v8, (a0)2140; RV32-NEXT: csrr a0, vl2141; RV32-NEXT: sw a0, 0(a2)2142; RV32-NEXT: ret2143;2144; RV64-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8:2145; RV64: # %bb.0: # %entry2146; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2147; RV64-NEXT: vle8ff.v v8, (a0)2148; RV64-NEXT: csrr a0, vl2149; RV64-NEXT: sd a0, 0(a2)2150; RV64-NEXT: ret2151entry:2152 %a = call { <vscale x 4 x i8>, iXLen } @llvm.riscv.vleff.nxv4i8(2153 <vscale x 4 x i8> poison,2154 ptr %0,2155 iXLen %1)2156 %b = extractvalue { <vscale x 4 x i8>, iXLen } %a, 02157 %c = extractvalue { <vscale x 4 x i8>, iXLen } %a, 12158 store iXLen %c, ptr %22159 ret <vscale x 4 x i8> %b2160}2161 2162define <vscale x 4 x i8> @intrinsic_vleff_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3, ptr %4) nounwind {2163; RV32-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8:2164; RV32: # %bb.0: # %entry2165; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, mu2166; RV32-NEXT: vle8ff.v v8, (a0), v0.t2167; RV32-NEXT: csrr a0, vl2168; RV32-NEXT: sw a0, 0(a2)2169; RV32-NEXT: ret2170;2171; RV64-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8:2172; RV64: # %bb.0: # %entry2173; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu2174; RV64-NEXT: vle8ff.v v8, (a0), v0.t2175; RV64-NEXT: csrr a0, vl2176; RV64-NEXT: sd a0, 0(a2)2177; RV64-NEXT: ret2178entry:2179 %a = call { <vscale x 4 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv4i8(2180 <vscale x 4 x i8> %0,2181 ptr %1,2182 <vscale x 4 x i1> %2,2183 iXLen %3, iXLen 1)2184 %b = extractvalue { <vscale x 4 x i8>, iXLen } %a, 02185 %c = extractvalue { <vscale x 4 x i8>, iXLen } %a, 12186 store iXLen %c, ptr %42187 2188 ret <vscale x 4 x i8> %b2189}2190 2191define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(ptr %0, iXLen %1, ptr %2) nounwind {2192; RV32-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8:2193; RV32: # %bb.0: # %entry2194; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, ma2195; RV32-NEXT: vle8ff.v v8, (a0)2196; RV32-NEXT: csrr a0, vl2197; RV32-NEXT: sw a0, 0(a2)2198; RV32-NEXT: ret2199;2200; RV64-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8:2201; RV64: # %bb.0: # %entry2202; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma2203; RV64-NEXT: vle8ff.v v8, (a0)2204; RV64-NEXT: csrr a0, vl2205; RV64-NEXT: sd a0, 0(a2)2206; RV64-NEXT: ret2207entry:2208 %a = call { <vscale x 8 x i8>, iXLen } @llvm.riscv.vleff.nxv8i8(2209 <vscale x 8 x i8> poison,2210 ptr %0,2211 iXLen %1)2212 %b = extractvalue { <vscale x 8 x i8>, iXLen } %a, 02213 %c = extractvalue { <vscale x 8 x i8>, iXLen } %a, 12214 store iXLen %c, ptr %22215 ret <vscale x 8 x i8> %b2216}2217 2218define <vscale x 8 x i8> @intrinsic_vleff_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3, ptr %4) nounwind {2219; RV32-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8:2220; RV32: # %bb.0: # %entry2221; RV32-NEXT: vsetvli zero, a1, e8, m1, ta, mu2222; RV32-NEXT: vle8ff.v v8, (a0), v0.t2223; RV32-NEXT: csrr a0, vl2224; RV32-NEXT: sw a0, 0(a2)2225; RV32-NEXT: ret2226;2227; RV64-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8:2228; RV64: # %bb.0: # %entry2229; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, mu2230; RV64-NEXT: vle8ff.v v8, (a0), v0.t2231; RV64-NEXT: csrr a0, vl2232; RV64-NEXT: sd a0, 0(a2)2233; RV64-NEXT: ret2234entry:2235 %a = call { <vscale x 8 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv8i8(2236 <vscale x 8 x i8> %0,2237 ptr %1,2238 <vscale x 8 x i1> %2,2239 iXLen %3, iXLen 1)2240 %b = extractvalue { <vscale x 8 x i8>, iXLen } %a, 02241 %c = extractvalue { <vscale x 8 x i8>, iXLen } %a, 12242 store iXLen %c, ptr %42243 2244 ret <vscale x 8 x i8> %b2245}2246 2247define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(ptr %0, iXLen %1, ptr %2) nounwind {2248; RV32-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8:2249; RV32: # %bb.0: # %entry2250; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma2251; RV32-NEXT: vle8ff.v v8, (a0)2252; RV32-NEXT: csrr a0, vl2253; RV32-NEXT: sw a0, 0(a2)2254; RV32-NEXT: ret2255;2256; RV64-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8:2257; RV64: # %bb.0: # %entry2258; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma2259; RV64-NEXT: vle8ff.v v8, (a0)2260; RV64-NEXT: csrr a0, vl2261; RV64-NEXT: sd a0, 0(a2)2262; RV64-NEXT: ret2263entry:2264 %a = call { <vscale x 16 x i8>, iXLen } @llvm.riscv.vleff.nxv16i8(2265 <vscale x 16 x i8> poison,2266 ptr %0,2267 iXLen %1)2268 %b = extractvalue { <vscale x 16 x i8>, iXLen } %a, 02269 %c = extractvalue { <vscale x 16 x i8>, iXLen } %a, 12270 store iXLen %c, ptr %22271 ret <vscale x 16 x i8> %b2272}2273 2274define <vscale x 16 x i8> @intrinsic_vleff_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3, ptr %4) nounwind {2275; RV32-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8:2276; RV32: # %bb.0: # %entry2277; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, mu2278; RV32-NEXT: vle8ff.v v8, (a0), v0.t2279; RV32-NEXT: csrr a0, vl2280; RV32-NEXT: sw a0, 0(a2)2281; RV32-NEXT: ret2282;2283; RV64-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8:2284; RV64: # %bb.0: # %entry2285; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, mu2286; RV64-NEXT: vle8ff.v v8, (a0), v0.t2287; RV64-NEXT: csrr a0, vl2288; RV64-NEXT: sd a0, 0(a2)2289; RV64-NEXT: ret2290entry:2291 %a = call { <vscale x 16 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv16i8(2292 <vscale x 16 x i8> %0,2293 ptr %1,2294 <vscale x 16 x i1> %2,2295 iXLen %3, iXLen 1)2296 %b = extractvalue { <vscale x 16 x i8>, iXLen } %a, 02297 %c = extractvalue { <vscale x 16 x i8>, iXLen } %a, 12298 store iXLen %c, ptr %42299 2300 ret <vscale x 16 x i8> %b2301}2302 2303define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(ptr %0, iXLen %1, ptr %2) nounwind {2304; RV32-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8:2305; RV32: # %bb.0: # %entry2306; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma2307; RV32-NEXT: vle8ff.v v8, (a0)2308; RV32-NEXT: csrr a0, vl2309; RV32-NEXT: sw a0, 0(a2)2310; RV32-NEXT: ret2311;2312; RV64-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8:2313; RV64: # %bb.0: # %entry2314; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma2315; RV64-NEXT: vle8ff.v v8, (a0)2316; RV64-NEXT: csrr a0, vl2317; RV64-NEXT: sd a0, 0(a2)2318; RV64-NEXT: ret2319entry:2320 %a = call { <vscale x 32 x i8>, iXLen } @llvm.riscv.vleff.nxv32i8(2321 <vscale x 32 x i8> poison,2322 ptr %0,2323 iXLen %1)2324 %b = extractvalue { <vscale x 32 x i8>, iXLen } %a, 02325 %c = extractvalue { <vscale x 32 x i8>, iXLen } %a, 12326 store iXLen %c, ptr %22327 ret <vscale x 32 x i8> %b2328}2329 2330define <vscale x 32 x i8> @intrinsic_vleff_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3, ptr %4) nounwind {2331; RV32-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8:2332; RV32: # %bb.0: # %entry2333; RV32-NEXT: vsetvli zero, a1, e8, m4, ta, mu2334; RV32-NEXT: vle8ff.v v8, (a0), v0.t2335; RV32-NEXT: csrr a0, vl2336; RV32-NEXT: sw a0, 0(a2)2337; RV32-NEXT: ret2338;2339; RV64-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8:2340; RV64: # %bb.0: # %entry2341; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, mu2342; RV64-NEXT: vle8ff.v v8, (a0), v0.t2343; RV64-NEXT: csrr a0, vl2344; RV64-NEXT: sd a0, 0(a2)2345; RV64-NEXT: ret2346entry:2347 %a = call { <vscale x 32 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv32i8(2348 <vscale x 32 x i8> %0,2349 ptr %1,2350 <vscale x 32 x i1> %2,2351 iXLen %3, iXLen 1)2352 %b = extractvalue { <vscale x 32 x i8>, iXLen } %a, 02353 %c = extractvalue { <vscale x 32 x i8>, iXLen } %a, 12354 store iXLen %c, ptr %42355 2356 ret <vscale x 32 x i8> %b2357}2358 2359define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(ptr %0, iXLen %1, ptr %2) nounwind {2360; RV32-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8:2361; RV32: # %bb.0: # %entry2362; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma2363; RV32-NEXT: vle8ff.v v8, (a0)2364; RV32-NEXT: csrr a0, vl2365; RV32-NEXT: sw a0, 0(a2)2366; RV32-NEXT: ret2367;2368; RV64-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8:2369; RV64: # %bb.0: # %entry2370; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma2371; RV64-NEXT: vle8ff.v v8, (a0)2372; RV64-NEXT: csrr a0, vl2373; RV64-NEXT: sd a0, 0(a2)2374; RV64-NEXT: ret2375entry:2376 %a = call { <vscale x 64 x i8>, iXLen } @llvm.riscv.vleff.nxv64i8(2377 <vscale x 64 x i8> poison,2378 ptr %0,2379 iXLen %1)2380 %b = extractvalue { <vscale x 64 x i8>, iXLen } %a, 02381 %c = extractvalue { <vscale x 64 x i8>, iXLen } %a, 12382 store iXLen %c, ptr %22383 ret <vscale x 64 x i8> %b2384}2385 2386define <vscale x 64 x i8> @intrinsic_vleff_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3, ptr %4) nounwind {2387; RV32-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8:2388; RV32: # %bb.0: # %entry2389; RV32-NEXT: vsetvli zero, a1, e8, m8, ta, mu2390; RV32-NEXT: vle8ff.v v8, (a0), v0.t2391; RV32-NEXT: csrr a0, vl2392; RV32-NEXT: sw a0, 0(a2)2393; RV32-NEXT: ret2394;2395; RV64-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8:2396; RV64: # %bb.0: # %entry2397; RV64-NEXT: vsetvli zero, a1, e8, m8, ta, mu2398; RV64-NEXT: vle8ff.v v8, (a0), v0.t2399; RV64-NEXT: csrr a0, vl2400; RV64-NEXT: sd a0, 0(a2)2401; RV64-NEXT: ret2402entry:2403 %a = call { <vscale x 64 x i8>, iXLen } @llvm.riscv.vleff.mask.nxv64i8(2404 <vscale x 64 x i8> %0,2405 ptr %1,2406 <vscale x 64 x i1> %2,2407 iXLen %3, iXLen 1)2408 %b = extractvalue { <vscale x 64 x i8>, iXLen } %a, 02409 %c = extractvalue { <vscale x 64 x i8>, iXLen } %a, 12410 store iXLen %c, ptr %42411 2412 ret <vscale x 64 x i8> %b2413}2414 2415; Test with the VL output unused2416define <vscale x 1 x double> @intrinsic_vleff_dead_vl(ptr %0, iXLen %1, ptr %2) nounwind {2417; CHECK-LABEL: intrinsic_vleff_dead_vl:2418; CHECK: # %bb.0: # %entry2419; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma2420; CHECK-NEXT: vle64ff.v v8, (a0)2421; CHECK-NEXT: ret2422entry:2423 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.nxv1f64(2424 <vscale x 1 x double> poison,2425 ptr %0,2426 iXLen %1)2427 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 02428 ret <vscale x 1 x double> %b2429}2430 2431define <vscale x 1 x double> @intrinsic_vleff_mask_dead_vl(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2432; CHECK-LABEL: intrinsic_vleff_mask_dead_vl:2433; CHECK: # %bb.0: # %entry2434; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu2435; CHECK-NEXT: vle64ff.v v8, (a0), v0.t2436; CHECK-NEXT: ret2437entry:2438 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.mask.nxv1f64(2439 <vscale x 1 x double> %0,2440 ptr %1,2441 <vscale x 1 x i1> %2,2442 iXLen %3, iXLen 1)2443 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 02444 2445 ret <vscale x 1 x double> %b2446}2447 2448; Test with the loaded value unused2449define void @intrinsic_vleff_dead_value(ptr %0, iXLen %1, ptr %2) nounwind {2450; RV32-LABEL: intrinsic_vleff_dead_value:2451; RV32: # %bb.0: # %entry2452; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, ma2453; RV32-NEXT: vle64ff.v v8, (a0)2454; RV32-NEXT: csrr a0, vl2455; RV32-NEXT: sw a0, 0(a2)2456; RV32-NEXT: ret2457;2458; RV64-LABEL: intrinsic_vleff_dead_value:2459; RV64: # %bb.0: # %entry2460; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma2461; RV64-NEXT: vle64ff.v v8, (a0)2462; RV64-NEXT: csrr a0, vl2463; RV64-NEXT: sd a0, 0(a2)2464; RV64-NEXT: ret2465entry:2466 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.nxv1f64(2467 <vscale x 1 x double> poison,2468 ptr %0,2469 iXLen %1)2470 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 12471 store iXLen %b, ptr %22472 ret void2473}2474 2475define void @intrinsic_vleff_mask_dead_value(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3, ptr %4) nounwind {2476; RV32-LABEL: intrinsic_vleff_mask_dead_value:2477; RV32: # %bb.0: # %entry2478; RV32-NEXT: vsetvli zero, a1, e64, m1, ta, mu2479; RV32-NEXT: vle64ff.v v8, (a0), v0.t2480; RV32-NEXT: csrr a0, vl2481; RV32-NEXT: sw a0, 0(a2)2482; RV32-NEXT: ret2483;2484; RV64-LABEL: intrinsic_vleff_mask_dead_value:2485; RV64: # %bb.0: # %entry2486; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu2487; RV64-NEXT: vle64ff.v v8, (a0), v0.t2488; RV64-NEXT: csrr a0, vl2489; RV64-NEXT: sd a0, 0(a2)2490; RV64-NEXT: ret2491entry:2492 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.mask.nxv1f64(2493 <vscale x 1 x double> %0,2494 ptr %1,2495 <vscale x 1 x i1> %2,2496 iXLen %3, iXLen 1)2497 %b = extractvalue { <vscale x 1 x double>, iXLen } %a, 12498 store iXLen %b, ptr %42499 2500 ret void2501}2502 2503define void @intrinsic_vleff_dead_all(ptr %0, iXLen %1, ptr %2) nounwind {2504; CHECK-LABEL: intrinsic_vleff_dead_all:2505; CHECK: # %bb.0: # %entry2506; CHECK-NEXT: ret2507entry:2508 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.nxv1f64(2509 <vscale x 1 x double> poison,2510 ptr %0,2511 iXLen %1)2512 ret void2513}2514 2515define void @intrinsic_vleff_mask_dead_all(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2516; CHECK-LABEL: intrinsic_vleff_mask_dead_all:2517; CHECK: # %bb.0: # %entry2518; CHECK-NEXT: ret2519entry:2520 %a = call { <vscale x 1 x double>, iXLen } @llvm.riscv.vleff.mask.nxv1f64(2521 <vscale x 1 x double> %0,2522 ptr %1,2523 <vscale x 1 x i1> %2,2524 iXLen %3, iXLen 1)2525 2526 ret void2527}2528