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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(ptr %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vlm.v v0, (a0)12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(ptr %0, iXLen %1)15 ret <vscale x 1 x i1> %a16}17 18define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(ptr %0, iXLen %1) nounwind {19; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma22; CHECK-NEXT: vlm.v v0, (a0)23; CHECK-NEXT: ret24entry:25 %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(ptr %0, iXLen %1)26 ret <vscale x 2 x i1> %a27}28 29define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(ptr %0, iXLen %1) nounwind {30; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma33; CHECK-NEXT: vlm.v v0, (a0)34; CHECK-NEXT: ret35entry:36 %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(ptr %0, iXLen %1)37 ret <vscale x 4 x i1> %a38}39 40define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(ptr %0, iXLen %1) nounwind {41; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma44; CHECK-NEXT: vlm.v v0, (a0)45; CHECK-NEXT: ret46entry:47 %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(ptr %0, iXLen %1)48 ret <vscale x 8 x i1> %a49}50 51define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(ptr %0, iXLen %1) nounwind {52; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma55; CHECK-NEXT: vlm.v v0, (a0)56; CHECK-NEXT: ret57entry:58 %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(ptr %0, iXLen %1)59 ret <vscale x 16 x i1> %a60}61 62define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(ptr %0, iXLen %1) nounwind {63; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma66; CHECK-NEXT: vlm.v v0, (a0)67; CHECK-NEXT: ret68entry:69 %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(ptr %0, iXLen %1)70 ret <vscale x 32 x i1> %a71}72 73define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(ptr %0, iXLen %1) nounwind {74; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma77; CHECK-NEXT: vlm.v v0, (a0)78; CHECK-NEXT: ret79entry:80 %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(ptr %0, iXLen %1)81 ret <vscale x 64 x i1> %a82}83