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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s3 4define <vscale x 1 x i1> @sew1_srli(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {5; CHECK-LABEL: sew1_srli:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma8; CHECK-NEXT: vmand.mm v0, v0, v89; CHECK-NEXT: ret10 %vlmax = call i32 @llvm.vscale()11 %x = call <vscale x 1 x i1> @llvm.vp.and.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> splat (i1 true), i32 %vlmax)12 ret <vscale x 1 x i1> %x13}14 15define <vscale x 1 x i64> @sew64_srli(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {16; CHECK-LABEL: sew64_srli:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma19; CHECK-NEXT: vadd.vv v8, v8, v920; CHECK-NEXT: ret21 %vlmax = call i32 @llvm.vscale()22 %x = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %vlmax)23 ret <vscale x 1 x i64> %x24}25 26define <vscale x 8 x i64> @sew64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {27; CHECK-LABEL: sew64:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma30; CHECK-NEXT: vadd.vv v8, v8, v1631; CHECK-NEXT: ret32 %vscale = call i32 @llvm.vscale()33 %vlmax = shl i32 %vscale, 334 %x = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %vlmax)35 ret <vscale x 8 x i64> %x36}37 38define <vscale x 16 x i32> @sew32_sll(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {39; CHECK-LABEL: sew32_sll:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma42; CHECK-NEXT: vadd.vv v8, v8, v1643; CHECK-NEXT: ret44 %vscale = call i32 @llvm.vscale()45 %vlmax = shl i32 %vscale, 446 %x = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %vlmax)47 ret <vscale x 16 x i32> %x48}49