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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT:    vloxei32.v v9, (a0), v812; CHECK-NEXT:    vmv1r.v v8, v913; CHECK-NEXT:    ret14entry:15  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32(16    <vscale x 1 x i8> poison,17    ptr %0,18    <vscale x 1 x i32> %1,19    iXLen %2)20 21  ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i32:26; CHECK:       # %bb.0: # %entry27; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu28; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t29; CHECK-NEXT:    ret30entry:31  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32(32    <vscale x 1 x i8> %0,33    ptr %1,34    <vscale x 1 x i32> %2,35    <vscale x 1 x i1> %3,36    iXLen %4, iXLen 1)37 38  ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32:43; CHECK:       # %bb.0: # %entry44; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma45; CHECK-NEXT:    vloxei32.v v9, (a0), v846; CHECK-NEXT:    vmv1r.v v8, v947; CHECK-NEXT:    ret48entry:49  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32(50    <vscale x 2 x i8> poison,51    ptr %0,52    <vscale x 2 x i32> %1,53    iXLen %2)54 55  ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i32:60; CHECK:       # %bb.0: # %entry61; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu62; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t63; CHECK-NEXT:    ret64entry:65  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32(66    <vscale x 2 x i8> %0,67    ptr %1,68    <vscale x 2 x i32> %2,69    <vscale x 2 x i1> %3,70    iXLen %4, iXLen 1)71 72  ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32:77; CHECK:       # %bb.0: # %entry78; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma79; CHECK-NEXT:    vloxei32.v v10, (a0), v880; CHECK-NEXT:    vmv1r.v v8, v1081; CHECK-NEXT:    ret82entry:83  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32(84    <vscale x 4 x i8> poison,85    ptr %0,86    <vscale x 4 x i32> %1,87    iXLen %2)88 89  ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i32:94; CHECK:       # %bb.0: # %entry95; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu96; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t97; CHECK-NEXT:    ret98entry:99  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32(100    <vscale x 4 x i8> %0,101    ptr %1,102    <vscale x 4 x i32> %2,103    <vscale x 4 x i1> %3,104    iXLen %4, iXLen 1)105 106  ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32:111; CHECK:       # %bb.0: # %entry112; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma113; CHECK-NEXT:    vloxei32.v v12, (a0), v8114; CHECK-NEXT:    vmv.v.v v8, v12115; CHECK-NEXT:    ret116entry:117  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32(118    <vscale x 8 x i8> poison,119    ptr %0,120    <vscale x 8 x i32> %1,121    iXLen %2)122 123  ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i32:128; CHECK:       # %bb.0: # %entry129; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu130; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t131; CHECK-NEXT:    ret132entry:133  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32(134    <vscale x 8 x i8> %0,135    ptr %1,136    <vscale x 8 x i32> %2,137    <vscale x 8 x i1> %3,138    iXLen %4, iXLen 1)139 140  ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32:145; CHECK:       # %bb.0: # %entry146; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma147; CHECK-NEXT:    vloxei32.v v16, (a0), v8148; CHECK-NEXT:    vmv.v.v v8, v16149; CHECK-NEXT:    ret150entry:151  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32(152    <vscale x 16 x i8> poison,153    ptr %0,154    <vscale x 16 x i32> %1,155    iXLen %2)156 157  ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32:162; CHECK:       # %bb.0: # %entry163; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu164; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t165; CHECK-NEXT:    ret166entry:167  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32(168    <vscale x 16 x i8> %0,169    ptr %1,170    <vscale x 16 x i32> %2,171    <vscale x 16 x i1> %3,172    iXLen %4, iXLen 1)173 174  ret <vscale x 16 x i8> %a175}176 177define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32:179; CHECK:       # %bb.0: # %entry180; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma181; CHECK-NEXT:    vloxei32.v v9, (a0), v8182; CHECK-NEXT:    vmv1r.v v8, v9183; CHECK-NEXT:    ret184entry:185  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32(186    <vscale x 1 x i16> poison,187    ptr %0,188    <vscale x 1 x i32> %1,189    iXLen %2)190 191  ret <vscale x 1 x i16> %a192}193 194define <vscale x 1 x i16> @intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i32:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu198; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t199; CHECK-NEXT:    ret200entry:201  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32(202    <vscale x 1 x i16> %0,203    ptr %1,204    <vscale x 1 x i32> %2,205    <vscale x 1 x i1> %3,206    iXLen %4, iXLen 1)207 208  ret <vscale x 1 x i16> %a209}210 211define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32:213; CHECK:       # %bb.0: # %entry214; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma215; CHECK-NEXT:    vloxei32.v v9, (a0), v8216; CHECK-NEXT:    vmv1r.v v8, v9217; CHECK-NEXT:    ret218entry:219  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32(220    <vscale x 2 x i16> poison,221    ptr %0,222    <vscale x 2 x i32> %1,223    iXLen %2)224 225  ret <vscale x 2 x i16> %a226}227 228define <vscale x 2 x i16> @intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i32:230; CHECK:       # %bb.0: # %entry231; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu232; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t233; CHECK-NEXT:    ret234entry:235  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32(236    <vscale x 2 x i16> %0,237    ptr %1,238    <vscale x 2 x i32> %2,239    <vscale x 2 x i1> %3,240    iXLen %4, iXLen 1)241 242  ret <vscale x 2 x i16> %a243}244 245define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32:247; CHECK:       # %bb.0: # %entry248; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma249; CHECK-NEXT:    vloxei32.v v10, (a0), v8250; CHECK-NEXT:    vmv.v.v v8, v10251; CHECK-NEXT:    ret252entry:253  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32(254    <vscale x 4 x i16> poison,255    ptr %0,256    <vscale x 4 x i32> %1,257    iXLen %2)258 259  ret <vscale x 4 x i16> %a260}261 262define <vscale x 4 x i16> @intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i32:264; CHECK:       # %bb.0: # %entry265; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu266; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t267; CHECK-NEXT:    ret268entry:269  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32(270    <vscale x 4 x i16> %0,271    ptr %1,272    <vscale x 4 x i32> %2,273    <vscale x 4 x i1> %3,274    iXLen %4, iXLen 1)275 276  ret <vscale x 4 x i16> %a277}278 279define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32:281; CHECK:       # %bb.0: # %entry282; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma283; CHECK-NEXT:    vloxei32.v v12, (a0), v8284; CHECK-NEXT:    vmv.v.v v8, v12285; CHECK-NEXT:    ret286entry:287  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32(288    <vscale x 8 x i16> poison,289    ptr %0,290    <vscale x 8 x i32> %1,291    iXLen %2)292 293  ret <vscale x 8 x i16> %a294}295 296define <vscale x 8 x i16> @intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i32:298; CHECK:       # %bb.0: # %entry299; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu300; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t301; CHECK-NEXT:    ret302entry:303  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32(304    <vscale x 8 x i16> %0,305    ptr %1,306    <vscale x 8 x i32> %2,307    <vscale x 8 x i1> %3,308    iXLen %4, iXLen 1)309 310  ret <vscale x 8 x i16> %a311}312 313define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32:315; CHECK:       # %bb.0: # %entry316; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma317; CHECK-NEXT:    vloxei32.v v16, (a0), v8318; CHECK-NEXT:    vmv.v.v v8, v16319; CHECK-NEXT:    ret320entry:321  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32(322    <vscale x 16 x i16> poison,323    ptr %0,324    <vscale x 16 x i32> %1,325    iXLen %2)326 327  ret <vscale x 16 x i16> %a328}329 330define <vscale x 16 x i16> @intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32:332; CHECK:       # %bb.0: # %entry333; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu334; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t335; CHECK-NEXT:    ret336entry:337  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32(338    <vscale x 16 x i16> %0,339    ptr %1,340    <vscale x 16 x i32> %2,341    <vscale x 16 x i1> %3,342    iXLen %4, iXLen 1)343 344  ret <vscale x 16 x i16> %a345}346 347define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32:349; CHECK:       # %bb.0: # %entry350; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma351; CHECK-NEXT:    vloxei32.v v8, (a0), v8352; CHECK-NEXT:    ret353entry:354  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32(355    <vscale x 1 x i32> poison,356    ptr %0,357    <vscale x 1 x i32> %1,358    iXLen %2)359 360  ret <vscale x 1 x i32> %a361}362 363define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {364; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i32:365; CHECK:       # %bb.0: # %entry366; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu367; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t368; CHECK-NEXT:    ret369entry:370  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32(371    <vscale x 1 x i32> %0,372    ptr %1,373    <vscale x 1 x i32> %2,374    <vscale x 1 x i1> %3,375    iXLen %4, iXLen 1)376 377  ret <vscale x 1 x i32> %a378}379 380define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {381; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32:382; CHECK:       # %bb.0: # %entry383; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma384; CHECK-NEXT:    vloxei32.v v8, (a0), v8385; CHECK-NEXT:    ret386entry:387  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32(388    <vscale x 2 x i32> poison,389    ptr %0,390    <vscale x 2 x i32> %1,391    iXLen %2)392 393  ret <vscale x 2 x i32> %a394}395 396define <vscale x 2 x i32> @intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {397; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i32:398; CHECK:       # %bb.0: # %entry399; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu400; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t401; CHECK-NEXT:    ret402entry:403  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32(404    <vscale x 2 x i32> %0,405    ptr %1,406    <vscale x 2 x i32> %2,407    <vscale x 2 x i1> %3,408    iXLen %4, iXLen 1)409 410  ret <vscale x 2 x i32> %a411}412 413define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {414; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32:415; CHECK:       # %bb.0: # %entry416; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma417; CHECK-NEXT:    vloxei32.v v8, (a0), v8418; CHECK-NEXT:    ret419entry:420  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32(421    <vscale x 4 x i32> poison,422    ptr %0,423    <vscale x 4 x i32> %1,424    iXLen %2)425 426  ret <vscale x 4 x i32> %a427}428 429define <vscale x 4 x i32> @intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {430; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i32:431; CHECK:       # %bb.0: # %entry432; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu433; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t434; CHECK-NEXT:    ret435entry:436  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32(437    <vscale x 4 x i32> %0,438    ptr %1,439    <vscale x 4 x i32> %2,440    <vscale x 4 x i1> %3,441    iXLen %4, iXLen 1)442 443  ret <vscale x 4 x i32> %a444}445 446define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {447; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32:448; CHECK:       # %bb.0: # %entry449; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma450; CHECK-NEXT:    vloxei32.v v8, (a0), v8451; CHECK-NEXT:    ret452entry:453  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32(454    <vscale x 8 x i32> poison,455    ptr %0,456    <vscale x 8 x i32> %1,457    iXLen %2)458 459  ret <vscale x 8 x i32> %a460}461 462define <vscale x 8 x i32> @intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {463; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i32:464; CHECK:       # %bb.0: # %entry465; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu466; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t467; CHECK-NEXT:    ret468entry:469  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32(470    <vscale x 8 x i32> %0,471    ptr %1,472    <vscale x 8 x i32> %2,473    <vscale x 8 x i1> %3,474    iXLen %4, iXLen 1)475 476  ret <vscale x 8 x i32> %a477}478 479define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {480; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32:481; CHECK:       # %bb.0: # %entry482; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma483; CHECK-NEXT:    vloxei32.v v8, (a0), v8484; CHECK-NEXT:    ret485entry:486  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32(487    <vscale x 16 x i32> poison,488    ptr %0,489    <vscale x 16 x i32> %1,490    iXLen %2)491 492  ret <vscale x 16 x i32> %a493}494 495define <vscale x 16 x i32> @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {496; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32:497; CHECK:       # %bb.0: # %entry498; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu499; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t500; CHECK-NEXT:    ret501entry:502  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32(503    <vscale x 16 x i32> %0,504    ptr %1,505    <vscale x 16 x i32> %2,506    <vscale x 16 x i1> %3,507    iXLen %4, iXLen 1)508 509  ret <vscale x 16 x i32> %a510}511 512define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {513; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32:514; CHECK:       # %bb.0: # %entry515; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma516; CHECK-NEXT:    vloxei32.v v9, (a0), v8517; CHECK-NEXT:    vmv.v.v v8, v9518; CHECK-NEXT:    ret519entry:520  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(521    <vscale x 1 x i64> poison,522    ptr %0,523    <vscale x 1 x i32> %1,524    iXLen %2)525 526  ret <vscale x 1 x i64> %a527}528 529define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i32:531; CHECK:       # %bb.0: # %entry532; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu533; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t534; CHECK-NEXT:    ret535entry:536  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(537    <vscale x 1 x i64> %0,538    ptr %1,539    <vscale x 1 x i32> %2,540    <vscale x 1 x i1> %3,541    iXLen %4, iXLen 1)542 543  ret <vscale x 1 x i64> %a544}545 546define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {547; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32:548; CHECK:       # %bb.0: # %entry549; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma550; CHECK-NEXT:    vmv1r.v v10, v8551; CHECK-NEXT:    vloxei32.v v8, (a0), v10552; CHECK-NEXT:    ret553entry:554  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32(555    <vscale x 2 x i64> poison,556    ptr %0,557    <vscale x 2 x i32> %1,558    iXLen %2)559 560  ret <vscale x 2 x i64> %a561}562 563define <vscale x 2 x i64> @intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {564; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i32:565; CHECK:       # %bb.0: # %entry566; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu567; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t568; CHECK-NEXT:    ret569entry:570  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32(571    <vscale x 2 x i64> %0,572    ptr %1,573    <vscale x 2 x i32> %2,574    <vscale x 2 x i1> %3,575    iXLen %4, iXLen 1)576 577  ret <vscale x 2 x i64> %a578}579 580define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {581; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32:582; CHECK:       # %bb.0: # %entry583; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma584; CHECK-NEXT:    vmv2r.v v12, v8585; CHECK-NEXT:    vloxei32.v v8, (a0), v12586; CHECK-NEXT:    ret587entry:588  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32(589    <vscale x 4 x i64> poison,590    ptr %0,591    <vscale x 4 x i32> %1,592    iXLen %2)593 594  ret <vscale x 4 x i64> %a595}596 597define <vscale x 4 x i64> @intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {598; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i32:599; CHECK:       # %bb.0: # %entry600; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu601; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t602; CHECK-NEXT:    ret603entry:604  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32(605    <vscale x 4 x i64> %0,606    ptr %1,607    <vscale x 4 x i32> %2,608    <vscale x 4 x i1> %3,609    iXLen %4, iXLen 1)610 611  ret <vscale x 4 x i64> %a612}613 614define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {615; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32:616; CHECK:       # %bb.0: # %entry617; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma618; CHECK-NEXT:    vmv4r.v v16, v8619; CHECK-NEXT:    vloxei32.v v8, (a0), v16620; CHECK-NEXT:    ret621entry:622  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32(623    <vscale x 8 x i64> poison,624    ptr %0,625    <vscale x 8 x i32> %1,626    iXLen %2)627 628  ret <vscale x 8 x i64> %a629}630 631define <vscale x 8 x i64> @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {632; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i32:633; CHECK:       # %bb.0: # %entry634; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu635; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t636; CHECK-NEXT:    ret637entry:638  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32(639    <vscale x 8 x i64> %0,640    ptr %1,641    <vscale x 8 x i32> %2,642    <vscale x 8 x i1> %3,643    iXLen %4, iXLen 1)644 645  ret <vscale x 8 x i64> %a646}647 648define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {649; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32:650; CHECK:       # %bb.0: # %entry651; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma652; CHECK-NEXT:    vloxei32.v v9, (a0), v8653; CHECK-NEXT:    vmv1r.v v8, v9654; CHECK-NEXT:    ret655entry:656  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32(657    <vscale x 1 x half> poison,658    ptr %0,659    <vscale x 1 x i32> %1,660    iXLen %2)661 662  ret <vscale x 1 x half> %a663}664 665define <vscale x 1 x half> @intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {666; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i32:667; CHECK:       # %bb.0: # %entry668; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu669; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t670; CHECK-NEXT:    ret671entry:672  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32(673    <vscale x 1 x half> %0,674    ptr %1,675    <vscale x 1 x i32> %2,676    <vscale x 1 x i1> %3,677    iXLen %4, iXLen 1)678 679  ret <vscale x 1 x half> %a680}681 682define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {683; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32:684; CHECK:       # %bb.0: # %entry685; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma686; CHECK-NEXT:    vloxei32.v v9, (a0), v8687; CHECK-NEXT:    vmv1r.v v8, v9688; CHECK-NEXT:    ret689entry:690  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32(691    <vscale x 2 x half> poison,692    ptr %0,693    <vscale x 2 x i32> %1,694    iXLen %2)695 696  ret <vscale x 2 x half> %a697}698 699define <vscale x 2 x half> @intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {700; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i32:701; CHECK:       # %bb.0: # %entry702; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu703; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t704; CHECK-NEXT:    ret705entry:706  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32(707    <vscale x 2 x half> %0,708    ptr %1,709    <vscale x 2 x i32> %2,710    <vscale x 2 x i1> %3,711    iXLen %4, iXLen 1)712 713  ret <vscale x 2 x half> %a714}715 716define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {717; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32:718; CHECK:       # %bb.0: # %entry719; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma720; CHECK-NEXT:    vloxei32.v v10, (a0), v8721; CHECK-NEXT:    vmv.v.v v8, v10722; CHECK-NEXT:    ret723entry:724  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32(725    <vscale x 4 x half> poison,726    ptr %0,727    <vscale x 4 x i32> %1,728    iXLen %2)729 730  ret <vscale x 4 x half> %a731}732 733define <vscale x 4 x half> @intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {734; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i32:735; CHECK:       # %bb.0: # %entry736; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu737; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t738; CHECK-NEXT:    ret739entry:740  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32(741    <vscale x 4 x half> %0,742    ptr %1,743    <vscale x 4 x i32> %2,744    <vscale x 4 x i1> %3,745    iXLen %4, iXLen 1)746 747  ret <vscale x 4 x half> %a748}749 750define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {751; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32:752; CHECK:       # %bb.0: # %entry753; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma754; CHECK-NEXT:    vloxei32.v v12, (a0), v8755; CHECK-NEXT:    vmv.v.v v8, v12756; CHECK-NEXT:    ret757entry:758  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32(759    <vscale x 8 x half> poison,760    ptr %0,761    <vscale x 8 x i32> %1,762    iXLen %2)763 764  ret <vscale x 8 x half> %a765}766 767define <vscale x 8 x half> @intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {768; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i32:769; CHECK:       # %bb.0: # %entry770; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu771; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t772; CHECK-NEXT:    ret773entry:774  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32(775    <vscale x 8 x half> %0,776    ptr %1,777    <vscale x 8 x i32> %2,778    <vscale x 8 x i1> %3,779    iXLen %4, iXLen 1)780 781  ret <vscale x 8 x half> %a782}783 784define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {785; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32:786; CHECK:       # %bb.0: # %entry787; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma788; CHECK-NEXT:    vloxei32.v v16, (a0), v8789; CHECK-NEXT:    vmv.v.v v8, v16790; CHECK-NEXT:    ret791entry:792  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32(793    <vscale x 16 x half> poison,794    ptr %0,795    <vscale x 16 x i32> %1,796    iXLen %2)797 798  ret <vscale x 16 x half> %a799}800 801define <vscale x 16 x half> @intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {802; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32:803; CHECK:       # %bb.0: # %entry804; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu805; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t806; CHECK-NEXT:    ret807entry:808  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32(809    <vscale x 16 x half> %0,810    ptr %1,811    <vscale x 16 x i32> %2,812    <vscale x 16 x i1> %3,813    iXLen %4, iXLen 1)814 815  ret <vscale x 16 x half> %a816}817 818define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {819; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32:820; CHECK:       # %bb.0: # %entry821; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma822; CHECK-NEXT:    vloxei32.v v8, (a0), v8823; CHECK-NEXT:    ret824entry:825  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32(826    <vscale x 1 x float> poison,827    ptr %0,828    <vscale x 1 x i32> %1,829    iXLen %2)830 831  ret <vscale x 1 x float> %a832}833 834define <vscale x 1 x float> @intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {835; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i32:836; CHECK:       # %bb.0: # %entry837; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu838; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t839; CHECK-NEXT:    ret840entry:841  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32(842    <vscale x 1 x float> %0,843    ptr %1,844    <vscale x 1 x i32> %2,845    <vscale x 1 x i1> %3,846    iXLen %4, iXLen 1)847 848  ret <vscale x 1 x float> %a849}850 851define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {852; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32:853; CHECK:       # %bb.0: # %entry854; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma855; CHECK-NEXT:    vloxei32.v v8, (a0), v8856; CHECK-NEXT:    ret857entry:858  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32(859    <vscale x 2 x float> poison,860    ptr %0,861    <vscale x 2 x i32> %1,862    iXLen %2)863 864  ret <vscale x 2 x float> %a865}866 867define <vscale x 2 x float> @intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {868; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i32:869; CHECK:       # %bb.0: # %entry870; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu871; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t872; CHECK-NEXT:    ret873entry:874  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32(875    <vscale x 2 x float> %0,876    ptr %1,877    <vscale x 2 x i32> %2,878    <vscale x 2 x i1> %3,879    iXLen %4, iXLen 1)880 881  ret <vscale x 2 x float> %a882}883 884define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {885; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32:886; CHECK:       # %bb.0: # %entry887; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma888; CHECK-NEXT:    vloxei32.v v8, (a0), v8889; CHECK-NEXT:    ret890entry:891  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32(892    <vscale x 4 x float> poison,893    ptr %0,894    <vscale x 4 x i32> %1,895    iXLen %2)896 897  ret <vscale x 4 x float> %a898}899 900define <vscale x 4 x float> @intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {901; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i32:902; CHECK:       # %bb.0: # %entry903; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu904; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t905; CHECK-NEXT:    ret906entry:907  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32(908    <vscale x 4 x float> %0,909    ptr %1,910    <vscale x 4 x i32> %2,911    <vscale x 4 x i1> %3,912    iXLen %4, iXLen 1)913 914  ret <vscale x 4 x float> %a915}916 917define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {918; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32:919; CHECK:       # %bb.0: # %entry920; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma921; CHECK-NEXT:    vloxei32.v v8, (a0), v8922; CHECK-NEXT:    ret923entry:924  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32(925    <vscale x 8 x float> poison,926    ptr %0,927    <vscale x 8 x i32> %1,928    iXLen %2)929 930  ret <vscale x 8 x float> %a931}932 933define <vscale x 8 x float> @intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {934; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i32:935; CHECK:       # %bb.0: # %entry936; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu937; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t938; CHECK-NEXT:    ret939entry:940  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32(941    <vscale x 8 x float> %0,942    ptr %1,943    <vscale x 8 x i32> %2,944    <vscale x 8 x i1> %3,945    iXLen %4, iXLen 1)946 947  ret <vscale x 8 x float> %a948}949 950define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {951; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32:952; CHECK:       # %bb.0: # %entry953; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma954; CHECK-NEXT:    vloxei32.v v8, (a0), v8955; CHECK-NEXT:    ret956entry:957  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32(958    <vscale x 16 x float> poison,959    ptr %0,960    <vscale x 16 x i32> %1,961    iXLen %2)962 963  ret <vscale x 16 x float> %a964}965 966define <vscale x 16 x float> @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {967; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32:968; CHECK:       # %bb.0: # %entry969; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu970; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t971; CHECK-NEXT:    ret972entry:973  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32(974    <vscale x 16 x float> %0,975    ptr %1,976    <vscale x 16 x i32> %2,977    <vscale x 16 x i1> %3,978    iXLen %4, iXLen 1)979 980  ret <vscale x 16 x float> %a981}982 983define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {984; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32:985; CHECK:       # %bb.0: # %entry986; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma987; CHECK-NEXT:    vloxei32.v v9, (a0), v8988; CHECK-NEXT:    vmv.v.v v8, v9989; CHECK-NEXT:    ret990entry:991  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32(992    <vscale x 1 x double> poison,993    ptr %0,994    <vscale x 1 x i32> %1,995    iXLen %2)996 997  ret <vscale x 1 x double> %a998}999 1000define <vscale x 1 x double> @intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1001; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i32:1002; CHECK:       # %bb.0: # %entry1003; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1004; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t1005; CHECK-NEXT:    ret1006entry:1007  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32(1008    <vscale x 1 x double> %0,1009    ptr %1,1010    <vscale x 1 x i32> %2,1011    <vscale x 1 x i1> %3,1012    iXLen %4, iXLen 1)1013 1014  ret <vscale x 1 x double> %a1015}1016 1017define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1018; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32:1019; CHECK:       # %bb.0: # %entry1020; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1021; CHECK-NEXT:    vmv1r.v v10, v81022; CHECK-NEXT:    vloxei32.v v8, (a0), v101023; CHECK-NEXT:    ret1024entry:1025  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32(1026    <vscale x 2 x double> poison,1027    ptr %0,1028    <vscale x 2 x i32> %1,1029    iXLen %2)1030 1031  ret <vscale x 2 x double> %a1032}1033 1034define <vscale x 2 x double> @intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1035; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i32:1036; CHECK:       # %bb.0: # %entry1037; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1038; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t1039; CHECK-NEXT:    ret1040entry:1041  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32(1042    <vscale x 2 x double> %0,1043    ptr %1,1044    <vscale x 2 x i32> %2,1045    <vscale x 2 x i1> %3,1046    iXLen %4, iXLen 1)1047 1048  ret <vscale x 2 x double> %a1049}1050 1051define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1052; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32:1053; CHECK:       # %bb.0: # %entry1054; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1055; CHECK-NEXT:    vmv2r.v v12, v81056; CHECK-NEXT:    vloxei32.v v8, (a0), v121057; CHECK-NEXT:    ret1058entry:1059  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32(1060    <vscale x 4 x double> poison,1061    ptr %0,1062    <vscale x 4 x i32> %1,1063    iXLen %2)1064 1065  ret <vscale x 4 x double> %a1066}1067 1068define <vscale x 4 x double> @intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1069; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i32:1070; CHECK:       # %bb.0: # %entry1071; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1072; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t1073; CHECK-NEXT:    ret1074entry:1075  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32(1076    <vscale x 4 x double> %0,1077    ptr %1,1078    <vscale x 4 x i32> %2,1079    <vscale x 4 x i1> %3,1080    iXLen %4, iXLen 1)1081 1082  ret <vscale x 4 x double> %a1083}1084 1085define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1086; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32:1087; CHECK:       # %bb.0: # %entry1088; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1089; CHECK-NEXT:    vmv4r.v v16, v81090; CHECK-NEXT:    vloxei32.v v8, (a0), v161091; CHECK-NEXT:    ret1092entry:1093  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32(1094    <vscale x 8 x double> poison,1095    ptr %0,1096    <vscale x 8 x i32> %1,1097    iXLen %2)1098 1099  ret <vscale x 8 x double> %a1100}1101 1102define <vscale x 8 x double> @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1103; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32:1104; CHECK:       # %bb.0: # %entry1105; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1106; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t1107; CHECK-NEXT:    ret1108entry:1109  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32(1110    <vscale x 8 x double> %0,1111    ptr %1,1112    <vscale x 8 x i32> %2,1113    <vscale x 8 x i1> %3,1114    iXLen %4, iXLen 1)1115 1116  ret <vscale x 8 x double> %a1117}1118 1119define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1120; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16:1121; CHECK:       # %bb.0: # %entry1122; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma1123; CHECK-NEXT:    vloxei16.v v9, (a0), v81124; CHECK-NEXT:    vmv1r.v v8, v91125; CHECK-NEXT:    ret1126entry:1127  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16(1128    <vscale x 1 x i8> poison,1129    ptr %0,1130    <vscale x 1 x i16> %1,1131    iXLen %2)1132 1133  ret <vscale x 1 x i8> %a1134}1135 1136define <vscale x 1 x i8> @intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1137; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i16:1138; CHECK:       # %bb.0: # %entry1139; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu1140; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1141; CHECK-NEXT:    ret1142entry:1143  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16(1144    <vscale x 1 x i8> %0,1145    ptr %1,1146    <vscale x 1 x i16> %2,1147    <vscale x 1 x i1> %3,1148    iXLen %4, iXLen 1)1149 1150  ret <vscale x 1 x i8> %a1151}1152 1153define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1154; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16:1155; CHECK:       # %bb.0: # %entry1156; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma1157; CHECK-NEXT:    vloxei16.v v9, (a0), v81158; CHECK-NEXT:    vmv1r.v v8, v91159; CHECK-NEXT:    ret1160entry:1161  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16(1162    <vscale x 2 x i8> poison,1163    ptr %0,1164    <vscale x 2 x i16> %1,1165    iXLen %2)1166 1167  ret <vscale x 2 x i8> %a1168}1169 1170define <vscale x 2 x i8> @intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1171; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i16:1172; CHECK:       # %bb.0: # %entry1173; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu1174; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1175; CHECK-NEXT:    ret1176entry:1177  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16(1178    <vscale x 2 x i8> %0,1179    ptr %1,1180    <vscale x 2 x i16> %2,1181    <vscale x 2 x i1> %3,1182    iXLen %4, iXLen 1)1183 1184  ret <vscale x 2 x i8> %a1185}1186 1187define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1188; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16:1189; CHECK:       # %bb.0: # %entry1190; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma1191; CHECK-NEXT:    vloxei16.v v9, (a0), v81192; CHECK-NEXT:    vmv1r.v v8, v91193; CHECK-NEXT:    ret1194entry:1195  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16(1196    <vscale x 4 x i8> poison,1197    ptr %0,1198    <vscale x 4 x i16> %1,1199    iXLen %2)1200 1201  ret <vscale x 4 x i8> %a1202}1203 1204define <vscale x 4 x i8> @intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1205; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i16:1206; CHECK:       # %bb.0: # %entry1207; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu1208; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1209; CHECK-NEXT:    ret1210entry:1211  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16(1212    <vscale x 4 x i8> %0,1213    ptr %1,1214    <vscale x 4 x i16> %2,1215    <vscale x 4 x i1> %3,1216    iXLen %4, iXLen 1)1217 1218  ret <vscale x 4 x i8> %a1219}1220 1221define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1222; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16:1223; CHECK:       # %bb.0: # %entry1224; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma1225; CHECK-NEXT:    vloxei16.v v10, (a0), v81226; CHECK-NEXT:    vmv.v.v v8, v101227; CHECK-NEXT:    ret1228entry:1229  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16(1230    <vscale x 8 x i8> poison,1231    ptr %0,1232    <vscale x 8 x i16> %1,1233    iXLen %2)1234 1235  ret <vscale x 8 x i8> %a1236}1237 1238define <vscale x 8 x i8> @intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1239; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i16:1240; CHECK:       # %bb.0: # %entry1241; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu1242; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t1243; CHECK-NEXT:    ret1244entry:1245  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16(1246    <vscale x 8 x i8> %0,1247    ptr %1,1248    <vscale x 8 x i16> %2,1249    <vscale x 8 x i1> %3,1250    iXLen %4, iXLen 1)1251 1252  ret <vscale x 8 x i8> %a1253}1254 1255define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1256; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16:1257; CHECK:       # %bb.0: # %entry1258; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma1259; CHECK-NEXT:    vloxei16.v v12, (a0), v81260; CHECK-NEXT:    vmv.v.v v8, v121261; CHECK-NEXT:    ret1262entry:1263  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16(1264    <vscale x 16 x i8> poison,1265    ptr %0,1266    <vscale x 16 x i16> %1,1267    iXLen %2)1268 1269  ret <vscale x 16 x i8> %a1270}1271 1272define <vscale x 16 x i8> @intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1273; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i16:1274; CHECK:       # %bb.0: # %entry1275; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu1276; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t1277; CHECK-NEXT:    ret1278entry:1279  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16(1280    <vscale x 16 x i8> %0,1281    ptr %1,1282    <vscale x 16 x i16> %2,1283    <vscale x 16 x i1> %3,1284    iXLen %4, iXLen 1)1285 1286  ret <vscale x 16 x i8> %a1287}1288 1289define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1290; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16:1291; CHECK:       # %bb.0: # %entry1292; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma1293; CHECK-NEXT:    vloxei16.v v16, (a0), v81294; CHECK-NEXT:    vmv.v.v v8, v161295; CHECK-NEXT:    ret1296entry:1297  %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16(1298    <vscale x 32 x i8> poison,1299    ptr %0,1300    <vscale x 32 x i16> %1,1301    iXLen %2)1302 1303  ret <vscale x 32 x i8> %a1304}1305 1306define <vscale x 32 x i8> @intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1307; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16:1308; CHECK:       # %bb.0: # %entry1309; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu1310; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t1311; CHECK-NEXT:    ret1312entry:1313  %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16(1314    <vscale x 32 x i8> %0,1315    ptr %1,1316    <vscale x 32 x i16> %2,1317    <vscale x 32 x i1> %3,1318    iXLen %4, iXLen 1)1319 1320  ret <vscale x 32 x i8> %a1321}1322 1323define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1324; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16:1325; CHECK:       # %bb.0: # %entry1326; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1327; CHECK-NEXT:    vloxei16.v v8, (a0), v81328; CHECK-NEXT:    ret1329entry:1330  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16(1331    <vscale x 1 x i16> poison,1332    ptr %0,1333    <vscale x 1 x i16> %1,1334    iXLen %2)1335 1336  ret <vscale x 1 x i16> %a1337}1338 1339define <vscale x 1 x i16> @intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1340; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i16:1341; CHECK:       # %bb.0: # %entry1342; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1343; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1344; CHECK-NEXT:    ret1345entry:1346  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16(1347    <vscale x 1 x i16> %0,1348    ptr %1,1349    <vscale x 1 x i16> %2,1350    <vscale x 1 x i1> %3,1351    iXLen %4, iXLen 1)1352 1353  ret <vscale x 1 x i16> %a1354}1355 1356define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1357; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16:1358; CHECK:       # %bb.0: # %entry1359; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1360; CHECK-NEXT:    vloxei16.v v8, (a0), v81361; CHECK-NEXT:    ret1362entry:1363  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16(1364    <vscale x 2 x i16> poison,1365    ptr %0,1366    <vscale x 2 x i16> %1,1367    iXLen %2)1368 1369  ret <vscale x 2 x i16> %a1370}1371 1372define <vscale x 2 x i16> @intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1373; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i16:1374; CHECK:       # %bb.0: # %entry1375; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1376; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1377; CHECK-NEXT:    ret1378entry:1379  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16(1380    <vscale x 2 x i16> %0,1381    ptr %1,1382    <vscale x 2 x i16> %2,1383    <vscale x 2 x i1> %3,1384    iXLen %4, iXLen 1)1385 1386  ret <vscale x 2 x i16> %a1387}1388 1389define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1390; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16:1391; CHECK:       # %bb.0: # %entry1392; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1393; CHECK-NEXT:    vloxei16.v v8, (a0), v81394; CHECK-NEXT:    ret1395entry:1396  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16(1397    <vscale x 4 x i16> poison,1398    ptr %0,1399    <vscale x 4 x i16> %1,1400    iXLen %2)1401 1402  ret <vscale x 4 x i16> %a1403}1404 1405define <vscale x 4 x i16> @intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1406; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i16:1407; CHECK:       # %bb.0: # %entry1408; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1409; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1410; CHECK-NEXT:    ret1411entry:1412  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16(1413    <vscale x 4 x i16> %0,1414    ptr %1,1415    <vscale x 4 x i16> %2,1416    <vscale x 4 x i1> %3,1417    iXLen %4, iXLen 1)1418 1419  ret <vscale x 4 x i16> %a1420}1421 1422define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1423; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16:1424; CHECK:       # %bb.0: # %entry1425; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1426; CHECK-NEXT:    vloxei16.v v8, (a0), v81427; CHECK-NEXT:    ret1428entry:1429  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16(1430    <vscale x 8 x i16> poison,1431    ptr %0,1432    <vscale x 8 x i16> %1,1433    iXLen %2)1434 1435  ret <vscale x 8 x i16> %a1436}1437 1438define <vscale x 8 x i16> @intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1439; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i16:1440; CHECK:       # %bb.0: # %entry1441; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1442; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t1443; CHECK-NEXT:    ret1444entry:1445  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16(1446    <vscale x 8 x i16> %0,1447    ptr %1,1448    <vscale x 8 x i16> %2,1449    <vscale x 8 x i1> %3,1450    iXLen %4, iXLen 1)1451 1452  ret <vscale x 8 x i16> %a1453}1454 1455define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1456; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16:1457; CHECK:       # %bb.0: # %entry1458; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1459; CHECK-NEXT:    vloxei16.v v8, (a0), v81460; CHECK-NEXT:    ret1461entry:1462  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16(1463    <vscale x 16 x i16> poison,1464    ptr %0,1465    <vscale x 16 x i16> %1,1466    iXLen %2)1467 1468  ret <vscale x 16 x i16> %a1469}1470 1471define <vscale x 16 x i16> @intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1472; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i16:1473; CHECK:       # %bb.0: # %entry1474; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1475; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t1476; CHECK-NEXT:    ret1477entry:1478  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16(1479    <vscale x 16 x i16> %0,1480    ptr %1,1481    <vscale x 16 x i16> %2,1482    <vscale x 16 x i1> %3,1483    iXLen %4, iXLen 1)1484 1485  ret <vscale x 16 x i16> %a1486}1487 1488define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1489; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16:1490; CHECK:       # %bb.0: # %entry1491; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1492; CHECK-NEXT:    vloxei16.v v8, (a0), v81493; CHECK-NEXT:    ret1494entry:1495  %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16(1496    <vscale x 32 x i16> poison,1497    ptr %0,1498    <vscale x 32 x i16> %1,1499    iXLen %2)1500 1501  ret <vscale x 32 x i16> %a1502}1503 1504define <vscale x 32 x i16> @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1505; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16:1506; CHECK:       # %bb.0: # %entry1507; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1508; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t1509; CHECK-NEXT:    ret1510entry:1511  %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16(1512    <vscale x 32 x i16> %0,1513    ptr %1,1514    <vscale x 32 x i16> %2,1515    <vscale x 32 x i1> %3,1516    iXLen %4, iXLen 1)1517 1518  ret <vscale x 32 x i16> %a1519}1520 1521define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1522; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16:1523; CHECK:       # %bb.0: # %entry1524; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1525; CHECK-NEXT:    vloxei16.v v9, (a0), v81526; CHECK-NEXT:    vmv1r.v v8, v91527; CHECK-NEXT:    ret1528entry:1529  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(1530    <vscale x 1 x i32> poison,1531    ptr %0,1532    <vscale x 1 x i16> %1,1533    iXLen %2)1534 1535  ret <vscale x 1 x i32> %a1536}1537 1538define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1539; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16:1540; CHECK:       # %bb.0: # %entry1541; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1542; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1543; CHECK-NEXT:    ret1544entry:1545  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(1546    <vscale x 1 x i32> %0,1547    ptr %1,1548    <vscale x 1 x i16> %2,1549    <vscale x 1 x i1> %3,1550    iXLen %4, iXLen 1)1551 1552  ret <vscale x 1 x i32> %a1553}1554 1555define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1556; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16:1557; CHECK:       # %bb.0: # %entry1558; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1559; CHECK-NEXT:    vloxei16.v v9, (a0), v81560; CHECK-NEXT:    vmv.v.v v8, v91561; CHECK-NEXT:    ret1562entry:1563  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16(1564    <vscale x 2 x i32> poison,1565    ptr %0,1566    <vscale x 2 x i16> %1,1567    iXLen %2)1568 1569  ret <vscale x 2 x i32> %a1570}1571 1572define <vscale x 2 x i32> @intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1573; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i16:1574; CHECK:       # %bb.0: # %entry1575; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1576; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1577; CHECK-NEXT:    ret1578entry:1579  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16(1580    <vscale x 2 x i32> %0,1581    ptr %1,1582    <vscale x 2 x i16> %2,1583    <vscale x 2 x i1> %3,1584    iXLen %4, iXLen 1)1585 1586  ret <vscale x 2 x i32> %a1587}1588 1589define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1590; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16:1591; CHECK:       # %bb.0: # %entry1592; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1593; CHECK-NEXT:    vmv1r.v v10, v81594; CHECK-NEXT:    vloxei16.v v8, (a0), v101595; CHECK-NEXT:    ret1596entry:1597  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16(1598    <vscale x 4 x i32> poison,1599    ptr %0,1600    <vscale x 4 x i16> %1,1601    iXLen %2)1602 1603  ret <vscale x 4 x i32> %a1604}1605 1606define <vscale x 4 x i32> @intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1607; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i16:1608; CHECK:       # %bb.0: # %entry1609; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1610; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t1611; CHECK-NEXT:    ret1612entry:1613  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16(1614    <vscale x 4 x i32> %0,1615    ptr %1,1616    <vscale x 4 x i16> %2,1617    <vscale x 4 x i1> %3,1618    iXLen %4, iXLen 1)1619 1620  ret <vscale x 4 x i32> %a1621}1622 1623define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1624; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16:1625; CHECK:       # %bb.0: # %entry1626; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1627; CHECK-NEXT:    vmv2r.v v12, v81628; CHECK-NEXT:    vloxei16.v v8, (a0), v121629; CHECK-NEXT:    ret1630entry:1631  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16(1632    <vscale x 8 x i32> poison,1633    ptr %0,1634    <vscale x 8 x i16> %1,1635    iXLen %2)1636 1637  ret <vscale x 8 x i32> %a1638}1639 1640define <vscale x 8 x i32> @intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1641; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i16:1642; CHECK:       # %bb.0: # %entry1643; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1644; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t1645; CHECK-NEXT:    ret1646entry:1647  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16(1648    <vscale x 8 x i32> %0,1649    ptr %1,1650    <vscale x 8 x i16> %2,1651    <vscale x 8 x i1> %3,1652    iXLen %4, iXLen 1)1653 1654  ret <vscale x 8 x i32> %a1655}1656 1657define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1658; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16:1659; CHECK:       # %bb.0: # %entry1660; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1661; CHECK-NEXT:    vmv4r.v v16, v81662; CHECK-NEXT:    vloxei16.v v8, (a0), v161663; CHECK-NEXT:    ret1664entry:1665  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16(1666    <vscale x 16 x i32> poison,1667    ptr %0,1668    <vscale x 16 x i16> %1,1669    iXLen %2)1670 1671  ret <vscale x 16 x i32> %a1672}1673 1674define <vscale x 16 x i32> @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1675; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16:1676; CHECK:       # %bb.0: # %entry1677; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1678; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t1679; CHECK-NEXT:    ret1680entry:1681  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16(1682    <vscale x 16 x i32> %0,1683    ptr %1,1684    <vscale x 16 x i16> %2,1685    <vscale x 16 x i1> %3,1686    iXLen %4, iXLen 1)1687 1688  ret <vscale x 16 x i32> %a1689}1690 1691define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1692; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16:1693; CHECK:       # %bb.0: # %entry1694; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1695; CHECK-NEXT:    vloxei16.v v9, (a0), v81696; CHECK-NEXT:    vmv.v.v v8, v91697; CHECK-NEXT:    ret1698entry:1699  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16(1700    <vscale x 1 x i64> poison,1701    ptr %0,1702    <vscale x 1 x i16> %1,1703    iXLen %2)1704 1705  ret <vscale x 1 x i64> %a1706}1707 1708define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1709; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i16:1710; CHECK:       # %bb.0: # %entry1711; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1712; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1713; CHECK-NEXT:    ret1714entry:1715  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16(1716    <vscale x 1 x i64> %0,1717    ptr %1,1718    <vscale x 1 x i16> %2,1719    <vscale x 1 x i1> %3,1720    iXLen %4, iXLen 1)1721 1722  ret <vscale x 1 x i64> %a1723}1724 1725define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1726; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16:1727; CHECK:       # %bb.0: # %entry1728; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1729; CHECK-NEXT:    vmv1r.v v10, v81730; CHECK-NEXT:    vloxei16.v v8, (a0), v101731; CHECK-NEXT:    ret1732entry:1733  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16(1734    <vscale x 2 x i64> poison,1735    ptr %0,1736    <vscale x 2 x i16> %1,1737    iXLen %2)1738 1739  ret <vscale x 2 x i64> %a1740}1741 1742define <vscale x 2 x i64> @intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1743; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i16:1744; CHECK:       # %bb.0: # %entry1745; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1746; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t1747; CHECK-NEXT:    ret1748entry:1749  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16(1750    <vscale x 2 x i64> %0,1751    ptr %1,1752    <vscale x 2 x i16> %2,1753    <vscale x 2 x i1> %3,1754    iXLen %4, iXLen 1)1755 1756  ret <vscale x 2 x i64> %a1757}1758 1759define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1760; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16:1761; CHECK:       # %bb.0: # %entry1762; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1763; CHECK-NEXT:    vmv1r.v v12, v81764; CHECK-NEXT:    vloxei16.v v8, (a0), v121765; CHECK-NEXT:    ret1766entry:1767  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16(1768    <vscale x 4 x i64> poison,1769    ptr %0,1770    <vscale x 4 x i16> %1,1771    iXLen %2)1772 1773  ret <vscale x 4 x i64> %a1774}1775 1776define <vscale x 4 x i64> @intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1777; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i16:1778; CHECK:       # %bb.0: # %entry1779; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1780; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t1781; CHECK-NEXT:    ret1782entry:1783  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16(1784    <vscale x 4 x i64> %0,1785    ptr %1,1786    <vscale x 4 x i16> %2,1787    <vscale x 4 x i1> %3,1788    iXLen %4, iXLen 1)1789 1790  ret <vscale x 4 x i64> %a1791}1792 1793define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1794; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16:1795; CHECK:       # %bb.0: # %entry1796; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1797; CHECK-NEXT:    vmv2r.v v16, v81798; CHECK-NEXT:    vloxei16.v v8, (a0), v161799; CHECK-NEXT:    ret1800entry:1801  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16(1802    <vscale x 8 x i64> poison,1803    ptr %0,1804    <vscale x 8 x i16> %1,1805    iXLen %2)1806 1807  ret <vscale x 8 x i64> %a1808}1809 1810define <vscale x 8 x i64> @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1811; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i16:1812; CHECK:       # %bb.0: # %entry1813; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1814; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t1815; CHECK-NEXT:    ret1816entry:1817  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16(1818    <vscale x 8 x i64> %0,1819    ptr %1,1820    <vscale x 8 x i16> %2,1821    <vscale x 8 x i1> %3,1822    iXLen %4, iXLen 1)1823 1824  ret <vscale x 8 x i64> %a1825}1826 1827define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1828; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16:1829; CHECK:       # %bb.0: # %entry1830; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1831; CHECK-NEXT:    vloxei16.v v8, (a0), v81832; CHECK-NEXT:    ret1833entry:1834  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16(1835    <vscale x 1 x half> poison,1836    ptr %0,1837    <vscale x 1 x i16> %1,1838    iXLen %2)1839 1840  ret <vscale x 1 x half> %a1841}1842 1843define <vscale x 1 x half> @intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1844; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i16:1845; CHECK:       # %bb.0: # %entry1846; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1847; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1848; CHECK-NEXT:    ret1849entry:1850  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16(1851    <vscale x 1 x half> %0,1852    ptr %1,1853    <vscale x 1 x i16> %2,1854    <vscale x 1 x i1> %3,1855    iXLen %4, iXLen 1)1856 1857  ret <vscale x 1 x half> %a1858}1859 1860define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1861; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16:1862; CHECK:       # %bb.0: # %entry1863; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1864; CHECK-NEXT:    vloxei16.v v8, (a0), v81865; CHECK-NEXT:    ret1866entry:1867  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16(1868    <vscale x 2 x half> poison,1869    ptr %0,1870    <vscale x 2 x i16> %1,1871    iXLen %2)1872 1873  ret <vscale x 2 x half> %a1874}1875 1876define <vscale x 2 x half> @intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1877; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i16:1878; CHECK:       # %bb.0: # %entry1879; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1880; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1881; CHECK-NEXT:    ret1882entry:1883  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16(1884    <vscale x 2 x half> %0,1885    ptr %1,1886    <vscale x 2 x i16> %2,1887    <vscale x 2 x i1> %3,1888    iXLen %4, iXLen 1)1889 1890  ret <vscale x 2 x half> %a1891}1892 1893define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1894; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16:1895; CHECK:       # %bb.0: # %entry1896; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1897; CHECK-NEXT:    vloxei16.v v8, (a0), v81898; CHECK-NEXT:    ret1899entry:1900  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16(1901    <vscale x 4 x half> poison,1902    ptr %0,1903    <vscale x 4 x i16> %1,1904    iXLen %2)1905 1906  ret <vscale x 4 x half> %a1907}1908 1909define <vscale x 4 x half> @intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1910; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i16:1911; CHECK:       # %bb.0: # %entry1912; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1913; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t1914; CHECK-NEXT:    ret1915entry:1916  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16(1917    <vscale x 4 x half> %0,1918    ptr %1,1919    <vscale x 4 x i16> %2,1920    <vscale x 4 x i1> %3,1921    iXLen %4, iXLen 1)1922 1923  ret <vscale x 4 x half> %a1924}1925 1926define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1927; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16:1928; CHECK:       # %bb.0: # %entry1929; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1930; CHECK-NEXT:    vloxei16.v v8, (a0), v81931; CHECK-NEXT:    ret1932entry:1933  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16(1934    <vscale x 8 x half> poison,1935    ptr %0,1936    <vscale x 8 x i16> %1,1937    iXLen %2)1938 1939  ret <vscale x 8 x half> %a1940}1941 1942define <vscale x 8 x half> @intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1943; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i16:1944; CHECK:       # %bb.0: # %entry1945; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1946; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t1947; CHECK-NEXT:    ret1948entry:1949  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16(1950    <vscale x 8 x half> %0,1951    ptr %1,1952    <vscale x 8 x i16> %2,1953    <vscale x 8 x i1> %3,1954    iXLen %4, iXLen 1)1955 1956  ret <vscale x 8 x half> %a1957}1958 1959define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1960; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16:1961; CHECK:       # %bb.0: # %entry1962; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1963; CHECK-NEXT:    vloxei16.v v8, (a0), v81964; CHECK-NEXT:    ret1965entry:1966  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16(1967    <vscale x 16 x half> poison,1968    ptr %0,1969    <vscale x 16 x i16> %1,1970    iXLen %2)1971 1972  ret <vscale x 16 x half> %a1973}1974 1975define <vscale x 16 x half> @intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1976; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i16:1977; CHECK:       # %bb.0: # %entry1978; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1979; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t1980; CHECK-NEXT:    ret1981entry:1982  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16(1983    <vscale x 16 x half> %0,1984    ptr %1,1985    <vscale x 16 x i16> %2,1986    <vscale x 16 x i1> %3,1987    iXLen %4, iXLen 1)1988 1989  ret <vscale x 16 x half> %a1990}1991 1992define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1993; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16:1994; CHECK:       # %bb.0: # %entry1995; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1996; CHECK-NEXT:    vloxei16.v v8, (a0), v81997; CHECK-NEXT:    ret1998entry:1999  %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16(2000    <vscale x 32 x half> poison,2001    ptr %0,2002    <vscale x 32 x i16> %1,2003    iXLen %2)2004 2005  ret <vscale x 32 x half> %a2006}2007 2008define <vscale x 32 x half> @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2009; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16:2010; CHECK:       # %bb.0: # %entry2011; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2012; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t2013; CHECK-NEXT:    ret2014entry:2015  %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16(2016    <vscale x 32 x half> %0,2017    ptr %1,2018    <vscale x 32 x i16> %2,2019    <vscale x 32 x i1> %3,2020    iXLen %4, iXLen 1)2021 2022  ret <vscale x 32 x half> %a2023}2024 2025define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2026; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16:2027; CHECK:       # %bb.0: # %entry2028; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2029; CHECK-NEXT:    vloxei16.v v9, (a0), v82030; CHECK-NEXT:    vmv1r.v v8, v92031; CHECK-NEXT:    ret2032entry:2033  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(2034    <vscale x 1 x float> poison,2035    ptr %0,2036    <vscale x 1 x i16> %1,2037    iXLen %2)2038 2039  ret <vscale x 1 x float> %a2040}2041 2042define <vscale x 1 x float> @intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2043; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i16:2044; CHECK:       # %bb.0: # %entry2045; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2046; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t2047; CHECK-NEXT:    ret2048entry:2049  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16(2050    <vscale x 1 x float> %0,2051    ptr %1,2052    <vscale x 1 x i16> %2,2053    <vscale x 1 x i1> %3,2054    iXLen %4, iXLen 1)2055 2056  ret <vscale x 1 x float> %a2057}2058 2059define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2060; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16:2061; CHECK:       # %bb.0: # %entry2062; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2063; CHECK-NEXT:    vloxei16.v v9, (a0), v82064; CHECK-NEXT:    vmv.v.v v8, v92065; CHECK-NEXT:    ret2066entry:2067  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16(2068    <vscale x 2 x float> poison,2069    ptr %0,2070    <vscale x 2 x i16> %1,2071    iXLen %2)2072 2073  ret <vscale x 2 x float> %a2074}2075 2076define <vscale x 2 x float> @intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2077; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i16:2078; CHECK:       # %bb.0: # %entry2079; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2080; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t2081; CHECK-NEXT:    ret2082entry:2083  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16(2084    <vscale x 2 x float> %0,2085    ptr %1,2086    <vscale x 2 x i16> %2,2087    <vscale x 2 x i1> %3,2088    iXLen %4, iXLen 1)2089 2090  ret <vscale x 2 x float> %a2091}2092 2093define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2094; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16:2095; CHECK:       # %bb.0: # %entry2096; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2097; CHECK-NEXT:    vmv1r.v v10, v82098; CHECK-NEXT:    vloxei16.v v8, (a0), v102099; CHECK-NEXT:    ret2100entry:2101  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16(2102    <vscale x 4 x float> poison,2103    ptr %0,2104    <vscale x 4 x i16> %1,2105    iXLen %2)2106 2107  ret <vscale x 4 x float> %a2108}2109 2110define <vscale x 4 x float> @intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2111; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i16:2112; CHECK:       # %bb.0: # %entry2113; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2114; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t2115; CHECK-NEXT:    ret2116entry:2117  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16(2118    <vscale x 4 x float> %0,2119    ptr %1,2120    <vscale x 4 x i16> %2,2121    <vscale x 4 x i1> %3,2122    iXLen %4, iXLen 1)2123 2124  ret <vscale x 4 x float> %a2125}2126 2127define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2128; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16:2129; CHECK:       # %bb.0: # %entry2130; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2131; CHECK-NEXT:    vmv2r.v v12, v82132; CHECK-NEXT:    vloxei16.v v8, (a0), v122133; CHECK-NEXT:    ret2134entry:2135  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16(2136    <vscale x 8 x float> poison,2137    ptr %0,2138    <vscale x 8 x i16> %1,2139    iXLen %2)2140 2141  ret <vscale x 8 x float> %a2142}2143 2144define <vscale x 8 x float> @intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2145; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i16:2146; CHECK:       # %bb.0: # %entry2147; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2148; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t2149; CHECK-NEXT:    ret2150entry:2151  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16(2152    <vscale x 8 x float> %0,2153    ptr %1,2154    <vscale x 8 x i16> %2,2155    <vscale x 8 x i1> %3,2156    iXLen %4, iXLen 1)2157 2158  ret <vscale x 8 x float> %a2159}2160 2161define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {2162; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16:2163; CHECK:       # %bb.0: # %entry2164; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2165; CHECK-NEXT:    vmv4r.v v16, v82166; CHECK-NEXT:    vloxei16.v v8, (a0), v162167; CHECK-NEXT:    ret2168entry:2169  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16(2170    <vscale x 16 x float> poison,2171    ptr %0,2172    <vscale x 16 x i16> %1,2173    iXLen %2)2174 2175  ret <vscale x 16 x float> %a2176}2177 2178define <vscale x 16 x float> @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2179; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16:2180; CHECK:       # %bb.0: # %entry2181; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2182; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t2183; CHECK-NEXT:    ret2184entry:2185  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16(2186    <vscale x 16 x float> %0,2187    ptr %1,2188    <vscale x 16 x i16> %2,2189    <vscale x 16 x i1> %3,2190    iXLen %4, iXLen 1)2191 2192  ret <vscale x 16 x float> %a2193}2194 2195define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2196; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16:2197; CHECK:       # %bb.0: # %entry2198; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2199; CHECK-NEXT:    vloxei16.v v9, (a0), v82200; CHECK-NEXT:    vmv.v.v v8, v92201; CHECK-NEXT:    ret2202entry:2203  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16(2204    <vscale x 1 x double> poison,2205    ptr %0,2206    <vscale x 1 x i16> %1,2207    iXLen %2)2208 2209  ret <vscale x 1 x double> %a2210}2211 2212define <vscale x 1 x double> @intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2213; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i16:2214; CHECK:       # %bb.0: # %entry2215; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2216; CHECK-NEXT:    vloxei16.v v8, (a0), v9, v0.t2217; CHECK-NEXT:    ret2218entry:2219  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16(2220    <vscale x 1 x double> %0,2221    ptr %1,2222    <vscale x 1 x i16> %2,2223    <vscale x 1 x i1> %3,2224    iXLen %4, iXLen 1)2225 2226  ret <vscale x 1 x double> %a2227}2228 2229define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2230; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16:2231; CHECK:       # %bb.0: # %entry2232; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2233; CHECK-NEXT:    vmv1r.v v10, v82234; CHECK-NEXT:    vloxei16.v v8, (a0), v102235; CHECK-NEXT:    ret2236entry:2237  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16(2238    <vscale x 2 x double> poison,2239    ptr %0,2240    <vscale x 2 x i16> %1,2241    iXLen %2)2242 2243  ret <vscale x 2 x double> %a2244}2245 2246define <vscale x 2 x double> @intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2247; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i16:2248; CHECK:       # %bb.0: # %entry2249; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu2250; CHECK-NEXT:    vloxei16.v v8, (a0), v10, v0.t2251; CHECK-NEXT:    ret2252entry:2253  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16(2254    <vscale x 2 x double> %0,2255    ptr %1,2256    <vscale x 2 x i16> %2,2257    <vscale x 2 x i1> %3,2258    iXLen %4, iXLen 1)2259 2260  ret <vscale x 2 x double> %a2261}2262 2263define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2264; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16:2265; CHECK:       # %bb.0: # %entry2266; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2267; CHECK-NEXT:    vmv1r.v v12, v82268; CHECK-NEXT:    vloxei16.v v8, (a0), v122269; CHECK-NEXT:    ret2270entry:2271  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16(2272    <vscale x 4 x double> poison,2273    ptr %0,2274    <vscale x 4 x i16> %1,2275    iXLen %2)2276 2277  ret <vscale x 4 x double> %a2278}2279 2280define <vscale x 4 x double> @intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2281; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i16:2282; CHECK:       # %bb.0: # %entry2283; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu2284; CHECK-NEXT:    vloxei16.v v8, (a0), v12, v0.t2285; CHECK-NEXT:    ret2286entry:2287  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16(2288    <vscale x 4 x double> %0,2289    ptr %1,2290    <vscale x 4 x i16> %2,2291    <vscale x 4 x i1> %3,2292    iXLen %4, iXLen 1)2293 2294  ret <vscale x 4 x double> %a2295}2296 2297define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2298; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16:2299; CHECK:       # %bb.0: # %entry2300; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2301; CHECK-NEXT:    vmv2r.v v16, v82302; CHECK-NEXT:    vloxei16.v v8, (a0), v162303; CHECK-NEXT:    ret2304entry:2305  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16(2306    <vscale x 8 x double> poison,2307    ptr %0,2308    <vscale x 8 x i16> %1,2309    iXLen %2)2310 2311  ret <vscale x 8 x double> %a2312}2313 2314define <vscale x 8 x double> @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2315; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16:2316; CHECK:       # %bb.0: # %entry2317; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu2318; CHECK-NEXT:    vloxei16.v v8, (a0), v16, v0.t2319; CHECK-NEXT:    ret2320entry:2321  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16(2322    <vscale x 8 x double> %0,2323    ptr %1,2324    <vscale x 8 x i16> %2,2325    <vscale x 8 x i1> %3,2326    iXLen %4, iXLen 1)2327 2328  ret <vscale x 8 x double> %a2329}2330 2331define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2332; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8:2333; CHECK:       # %bb.0: # %entry2334; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma2335; CHECK-NEXT:    vloxei8.v v8, (a0), v82336; CHECK-NEXT:    ret2337entry:2338  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8(2339    <vscale x 1 x i8> poison,2340    ptr %0,2341    <vscale x 1 x i8> %1,2342    iXLen %2)2343 2344  ret <vscale x 1 x i8> %a2345}2346 2347define <vscale x 1 x i8> @intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2348; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i8:2349; CHECK:       # %bb.0: # %entry2350; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu2351; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2352; CHECK-NEXT:    ret2353entry:2354  %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8(2355    <vscale x 1 x i8> %0,2356    ptr %1,2357    <vscale x 1 x i8> %2,2358    <vscale x 1 x i1> %3,2359    iXLen %4, iXLen 1)2360 2361  ret <vscale x 1 x i8> %a2362}2363 2364define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2365; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8:2366; CHECK:       # %bb.0: # %entry2367; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma2368; CHECK-NEXT:    vloxei8.v v8, (a0), v82369; CHECK-NEXT:    ret2370entry:2371  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8(2372    <vscale x 2 x i8> poison,2373    ptr %0,2374    <vscale x 2 x i8> %1,2375    iXLen %2)2376 2377  ret <vscale x 2 x i8> %a2378}2379 2380define <vscale x 2 x i8> @intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2381; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i8:2382; CHECK:       # %bb.0: # %entry2383; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu2384; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2385; CHECK-NEXT:    ret2386entry:2387  %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8(2388    <vscale x 2 x i8> %0,2389    ptr %1,2390    <vscale x 2 x i8> %2,2391    <vscale x 2 x i1> %3,2392    iXLen %4, iXLen 1)2393 2394  ret <vscale x 2 x i8> %a2395}2396 2397define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2398; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8:2399; CHECK:       # %bb.0: # %entry2400; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma2401; CHECK-NEXT:    vloxei8.v v8, (a0), v82402; CHECK-NEXT:    ret2403entry:2404  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8(2405    <vscale x 4 x i8> poison,2406    ptr %0,2407    <vscale x 4 x i8> %1,2408    iXLen %2)2409 2410  ret <vscale x 4 x i8> %a2411}2412 2413define <vscale x 4 x i8> @intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2414; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i8:2415; CHECK:       # %bb.0: # %entry2416; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu2417; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2418; CHECK-NEXT:    ret2419entry:2420  %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8(2421    <vscale x 4 x i8> %0,2422    ptr %1,2423    <vscale x 4 x i8> %2,2424    <vscale x 4 x i1> %3,2425    iXLen %4, iXLen 1)2426 2427  ret <vscale x 4 x i8> %a2428}2429 2430define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2431; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8:2432; CHECK:       # %bb.0: # %entry2433; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma2434; CHECK-NEXT:    vloxei8.v v8, (a0), v82435; CHECK-NEXT:    ret2436entry:2437  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8(2438    <vscale x 8 x i8> poison,2439    ptr %0,2440    <vscale x 8 x i8> %1,2441    iXLen %2)2442 2443  ret <vscale x 8 x i8> %a2444}2445 2446define <vscale x 8 x i8> @intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2447; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i8:2448; CHECK:       # %bb.0: # %entry2449; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu2450; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2451; CHECK-NEXT:    ret2452entry:2453  %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8(2454    <vscale x 8 x i8> %0,2455    ptr %1,2456    <vscale x 8 x i8> %2,2457    <vscale x 8 x i1> %3,2458    iXLen %4, iXLen 1)2459 2460  ret <vscale x 8 x i8> %a2461}2462 2463define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2464; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8:2465; CHECK:       # %bb.0: # %entry2466; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma2467; CHECK-NEXT:    vloxei8.v v8, (a0), v82468; CHECK-NEXT:    ret2469entry:2470  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8(2471    <vscale x 16 x i8> poison,2472    ptr %0,2473    <vscale x 16 x i8> %1,2474    iXLen %2)2475 2476  ret <vscale x 16 x i8> %a2477}2478 2479define <vscale x 16 x i8> @intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2480; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i8:2481; CHECK:       # %bb.0: # %entry2482; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu2483; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t2484; CHECK-NEXT:    ret2485entry:2486  %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8(2487    <vscale x 16 x i8> %0,2488    ptr %1,2489    <vscale x 16 x i8> %2,2490    <vscale x 16 x i1> %3,2491    iXLen %4, iXLen 1)2492 2493  ret <vscale x 16 x i8> %a2494}2495 2496define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2497; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8:2498; CHECK:       # %bb.0: # %entry2499; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma2500; CHECK-NEXT:    vloxei8.v v8, (a0), v82501; CHECK-NEXT:    ret2502entry:2503  %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8(2504    <vscale x 32 x i8> poison,2505    ptr %0,2506    <vscale x 32 x i8> %1,2507    iXLen %2)2508 2509  ret <vscale x 32 x i8> %a2510}2511 2512define <vscale x 32 x i8> @intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2513; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i8:2514; CHECK:       # %bb.0: # %entry2515; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu2516; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t2517; CHECK-NEXT:    ret2518entry:2519  %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8(2520    <vscale x 32 x i8> %0,2521    ptr %1,2522    <vscale x 32 x i8> %2,2523    <vscale x 32 x i1> %3,2524    iXLen %4, iXLen 1)2525 2526  ret <vscale x 32 x i8> %a2527}2528 2529define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(ptr %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {2530; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8:2531; CHECK:       # %bb.0: # %entry2532; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma2533; CHECK-NEXT:    vloxei8.v v8, (a0), v82534; CHECK-NEXT:    ret2535entry:2536  %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8(2537    <vscale x 64 x i8> poison,2538    ptr %0,2539    <vscale x 64 x i8> %1,2540    iXLen %2)2541 2542  ret <vscale x 64 x i8> %a2543}2544 2545define <vscale x 64 x i8> @intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {2546; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8:2547; CHECK:       # %bb.0: # %entry2548; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu2549; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t2550; CHECK-NEXT:    ret2551entry:2552  %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8(2553    <vscale x 64 x i8> %0,2554    ptr %1,2555    <vscale x 64 x i8> %2,2556    <vscale x 64 x i1> %3,2557    iXLen %4, iXLen 1)2558 2559  ret <vscale x 64 x i8> %a2560}2561 2562define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2563; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8:2564; CHECK:       # %bb.0: # %entry2565; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2566; CHECK-NEXT:    vloxei8.v v9, (a0), v82567; CHECK-NEXT:    vmv1r.v v8, v92568; CHECK-NEXT:    ret2569entry:2570  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8(2571    <vscale x 1 x i16> poison,2572    ptr %0,2573    <vscale x 1 x i8> %1,2574    iXLen %2)2575 2576  ret <vscale x 1 x i16> %a2577}2578 2579define <vscale x 1 x i16> @intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2580; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i8:2581; CHECK:       # %bb.0: # %entry2582; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu2583; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2584; CHECK-NEXT:    ret2585entry:2586  %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8(2587    <vscale x 1 x i16> %0,2588    ptr %1,2589    <vscale x 1 x i8> %2,2590    <vscale x 1 x i1> %3,2591    iXLen %4, iXLen 1)2592 2593  ret <vscale x 1 x i16> %a2594}2595 2596define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2597; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8:2598; CHECK:       # %bb.0: # %entry2599; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2600; CHECK-NEXT:    vloxei8.v v9, (a0), v82601; CHECK-NEXT:    vmv1r.v v8, v92602; CHECK-NEXT:    ret2603entry:2604  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8(2605    <vscale x 2 x i16> poison,2606    ptr %0,2607    <vscale x 2 x i8> %1,2608    iXLen %2)2609 2610  ret <vscale x 2 x i16> %a2611}2612 2613define <vscale x 2 x i16> @intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2614; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i8:2615; CHECK:       # %bb.0: # %entry2616; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu2617; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2618; CHECK-NEXT:    ret2619entry:2620  %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8(2621    <vscale x 2 x i16> %0,2622    ptr %1,2623    <vscale x 2 x i8> %2,2624    <vscale x 2 x i1> %3,2625    iXLen %4, iXLen 1)2626 2627  ret <vscale x 2 x i16> %a2628}2629 2630define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2631; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8:2632; CHECK:       # %bb.0: # %entry2633; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2634; CHECK-NEXT:    vloxei8.v v9, (a0), v82635; CHECK-NEXT:    vmv.v.v v8, v92636; CHECK-NEXT:    ret2637entry:2638  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8(2639    <vscale x 4 x i16> poison,2640    ptr %0,2641    <vscale x 4 x i8> %1,2642    iXLen %2)2643 2644  ret <vscale x 4 x i16> %a2645}2646 2647define <vscale x 4 x i16> @intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2648; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i8:2649; CHECK:       # %bb.0: # %entry2650; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu2651; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2652; CHECK-NEXT:    ret2653entry:2654  %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8(2655    <vscale x 4 x i16> %0,2656    ptr %1,2657    <vscale x 4 x i8> %2,2658    <vscale x 4 x i1> %3,2659    iXLen %4, iXLen 1)2660 2661  ret <vscale x 4 x i16> %a2662}2663 2664define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2665; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8:2666; CHECK:       # %bb.0: # %entry2667; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2668; CHECK-NEXT:    vmv1r.v v10, v82669; CHECK-NEXT:    vloxei8.v v8, (a0), v102670; CHECK-NEXT:    ret2671entry:2672  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8(2673    <vscale x 8 x i16> poison,2674    ptr %0,2675    <vscale x 8 x i8> %1,2676    iXLen %2)2677 2678  ret <vscale x 8 x i16> %a2679}2680 2681define <vscale x 8 x i16> @intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2682; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i8:2683; CHECK:       # %bb.0: # %entry2684; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu2685; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t2686; CHECK-NEXT:    ret2687entry:2688  %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8(2689    <vscale x 8 x i16> %0,2690    ptr %1,2691    <vscale x 8 x i8> %2,2692    <vscale x 8 x i1> %3,2693    iXLen %4, iXLen 1)2694 2695  ret <vscale x 8 x i16> %a2696}2697 2698define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2699; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8:2700; CHECK:       # %bb.0: # %entry2701; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2702; CHECK-NEXT:    vmv2r.v v12, v82703; CHECK-NEXT:    vloxei8.v v8, (a0), v122704; CHECK-NEXT:    ret2705entry:2706  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8(2707    <vscale x 16 x i16> poison,2708    ptr %0,2709    <vscale x 16 x i8> %1,2710    iXLen %2)2711 2712  ret <vscale x 16 x i16> %a2713}2714 2715define <vscale x 16 x i16> @intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2716; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i8:2717; CHECK:       # %bb.0: # %entry2718; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu2719; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t2720; CHECK-NEXT:    ret2721entry:2722  %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8(2723    <vscale x 16 x i16> %0,2724    ptr %1,2725    <vscale x 16 x i8> %2,2726    <vscale x 16 x i1> %3,2727    iXLen %4, iXLen 1)2728 2729  ret <vscale x 16 x i16> %a2730}2731 2732define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2733; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8:2734; CHECK:       # %bb.0: # %entry2735; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2736; CHECK-NEXT:    vmv4r.v v16, v82737; CHECK-NEXT:    vloxei8.v v8, (a0), v162738; CHECK-NEXT:    ret2739entry:2740  %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8(2741    <vscale x 32 x i16> poison,2742    ptr %0,2743    <vscale x 32 x i8> %1,2744    iXLen %2)2745 2746  ret <vscale x 32 x i16> %a2747}2748 2749define <vscale x 32 x i16> @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2750; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8:2751; CHECK:       # %bb.0: # %entry2752; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2753; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t2754; CHECK-NEXT:    ret2755entry:2756  %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8(2757    <vscale x 32 x i16> %0,2758    ptr %1,2759    <vscale x 32 x i8> %2,2760    <vscale x 32 x i1> %3,2761    iXLen %4, iXLen 1)2762 2763  ret <vscale x 32 x i16> %a2764}2765 2766define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2767; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8:2768; CHECK:       # %bb.0: # %entry2769; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2770; CHECK-NEXT:    vloxei8.v v9, (a0), v82771; CHECK-NEXT:    vmv1r.v v8, v92772; CHECK-NEXT:    ret2773entry:2774  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8(2775    <vscale x 1 x i32> poison,2776    ptr %0,2777    <vscale x 1 x i8> %1,2778    iXLen %2)2779 2780  ret <vscale x 1 x i32> %a2781}2782 2783define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2784; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i8:2785; CHECK:       # %bb.0: # %entry2786; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2787; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2788; CHECK-NEXT:    ret2789entry:2790  %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8(2791    <vscale x 1 x i32> %0,2792    ptr %1,2793    <vscale x 1 x i8> %2,2794    <vscale x 1 x i1> %3,2795    iXLen %4, iXLen 1)2796 2797  ret <vscale x 1 x i32> %a2798}2799 2800define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2801; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8:2802; CHECK:       # %bb.0: # %entry2803; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2804; CHECK-NEXT:    vloxei8.v v9, (a0), v82805; CHECK-NEXT:    vmv.v.v v8, v92806; CHECK-NEXT:    ret2807entry:2808  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8(2809    <vscale x 2 x i32> poison,2810    ptr %0,2811    <vscale x 2 x i8> %1,2812    iXLen %2)2813 2814  ret <vscale x 2 x i32> %a2815}2816 2817define <vscale x 2 x i32> @intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2818; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i8:2819; CHECK:       # %bb.0: # %entry2820; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2821; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2822; CHECK-NEXT:    ret2823entry:2824  %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8(2825    <vscale x 2 x i32> %0,2826    ptr %1,2827    <vscale x 2 x i8> %2,2828    <vscale x 2 x i1> %3,2829    iXLen %4, iXLen 1)2830 2831  ret <vscale x 2 x i32> %a2832}2833 2834define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2835; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8:2836; CHECK:       # %bb.0: # %entry2837; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2838; CHECK-NEXT:    vmv1r.v v10, v82839; CHECK-NEXT:    vloxei8.v v8, (a0), v102840; CHECK-NEXT:    ret2841entry:2842  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8(2843    <vscale x 4 x i32> poison,2844    ptr %0,2845    <vscale x 4 x i8> %1,2846    iXLen %2)2847 2848  ret <vscale x 4 x i32> %a2849}2850 2851define <vscale x 4 x i32> @intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2852; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i8:2853; CHECK:       # %bb.0: # %entry2854; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2855; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t2856; CHECK-NEXT:    ret2857entry:2858  %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8(2859    <vscale x 4 x i32> %0,2860    ptr %1,2861    <vscale x 4 x i8> %2,2862    <vscale x 4 x i1> %3,2863    iXLen %4, iXLen 1)2864 2865  ret <vscale x 4 x i32> %a2866}2867 2868define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2869; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8:2870; CHECK:       # %bb.0: # %entry2871; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2872; CHECK-NEXT:    vmv1r.v v12, v82873; CHECK-NEXT:    vloxei8.v v8, (a0), v122874; CHECK-NEXT:    ret2875entry:2876  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8(2877    <vscale x 8 x i32> poison,2878    ptr %0,2879    <vscale x 8 x i8> %1,2880    iXLen %2)2881 2882  ret <vscale x 8 x i32> %a2883}2884 2885define <vscale x 8 x i32> @intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2886; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i8:2887; CHECK:       # %bb.0: # %entry2888; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2889; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t2890; CHECK-NEXT:    ret2891entry:2892  %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8(2893    <vscale x 8 x i32> %0,2894    ptr %1,2895    <vscale x 8 x i8> %2,2896    <vscale x 8 x i1> %3,2897    iXLen %4, iXLen 1)2898 2899  ret <vscale x 8 x i32> %a2900}2901 2902define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2903; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8:2904; CHECK:       # %bb.0: # %entry2905; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2906; CHECK-NEXT:    vmv2r.v v16, v82907; CHECK-NEXT:    vloxei8.v v8, (a0), v162908; CHECK-NEXT:    ret2909entry:2910  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8(2911    <vscale x 16 x i32> poison,2912    ptr %0,2913    <vscale x 16 x i8> %1,2914    iXLen %2)2915 2916  ret <vscale x 16 x i32> %a2917}2918 2919define <vscale x 16 x i32> @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2920; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8:2921; CHECK:       # %bb.0: # %entry2922; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2923; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t2924; CHECK-NEXT:    ret2925entry:2926  %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8(2927    <vscale x 16 x i32> %0,2928    ptr %1,2929    <vscale x 16 x i8> %2,2930    <vscale x 16 x i1> %3,2931    iXLen %4, iXLen 1)2932 2933  ret <vscale x 16 x i32> %a2934}2935 2936define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2937; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8:2938; CHECK:       # %bb.0: # %entry2939; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2940; CHECK-NEXT:    vloxei8.v v9, (a0), v82941; CHECK-NEXT:    vmv.v.v v8, v92942; CHECK-NEXT:    ret2943entry:2944  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8(2945    <vscale x 1 x i64> poison,2946    ptr %0,2947    <vscale x 1 x i8> %1,2948    iXLen %2)2949 2950  ret <vscale x 1 x i64> %a2951}2952 2953define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2954; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i8:2955; CHECK:       # %bb.0: # %entry2956; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2957; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t2958; CHECK-NEXT:    ret2959entry:2960  %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8(2961    <vscale x 1 x i64> %0,2962    ptr %1,2963    <vscale x 1 x i8> %2,2964    <vscale x 1 x i1> %3,2965    iXLen %4, iXLen 1)2966 2967  ret <vscale x 1 x i64> %a2968}2969 2970define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2971; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8:2972; CHECK:       # %bb.0: # %entry2973; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2974; CHECK-NEXT:    vmv1r.v v10, v82975; CHECK-NEXT:    vloxei8.v v8, (a0), v102976; CHECK-NEXT:    ret2977entry:2978  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8(2979    <vscale x 2 x i64> poison,2980    ptr %0,2981    <vscale x 2 x i8> %1,2982    iXLen %2)2983 2984  ret <vscale x 2 x i64> %a2985}2986 2987define <vscale x 2 x i64> @intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2988; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i8:2989; CHECK:       # %bb.0: # %entry2990; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu2991; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t2992; CHECK-NEXT:    ret2993entry:2994  %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8(2995    <vscale x 2 x i64> %0,2996    ptr %1,2997    <vscale x 2 x i8> %2,2998    <vscale x 2 x i1> %3,2999    iXLen %4, iXLen 1)3000 3001  ret <vscale x 2 x i64> %a3002}3003 3004define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3005; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8:3006; CHECK:       # %bb.0: # %entry3007; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3008; CHECK-NEXT:    vmv1r.v v12, v83009; CHECK-NEXT:    vloxei8.v v8, (a0), v123010; CHECK-NEXT:    ret3011entry:3012  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8(3013    <vscale x 4 x i64> poison,3014    ptr %0,3015    <vscale x 4 x i8> %1,3016    iXLen %2)3017 3018  ret <vscale x 4 x i64> %a3019}3020 3021define <vscale x 4 x i64> @intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3022; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i8:3023; CHECK:       # %bb.0: # %entry3024; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3025; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t3026; CHECK-NEXT:    ret3027entry:3028  %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8(3029    <vscale x 4 x i64> %0,3030    ptr %1,3031    <vscale x 4 x i8> %2,3032    <vscale x 4 x i1> %3,3033    iXLen %4, iXLen 1)3034 3035  ret <vscale x 4 x i64> %a3036}3037 3038define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3039; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8:3040; CHECK:       # %bb.0: # %entry3041; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3042; CHECK-NEXT:    vmv1r.v v16, v83043; CHECK-NEXT:    vloxei8.v v8, (a0), v163044; CHECK-NEXT:    ret3045entry:3046  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8(3047    <vscale x 8 x i64> poison,3048    ptr %0,3049    <vscale x 8 x i8> %1,3050    iXLen %2)3051 3052  ret <vscale x 8 x i64> %a3053}3054 3055define <vscale x 8 x i64> @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3056; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i8:3057; CHECK:       # %bb.0: # %entry3058; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3059; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t3060; CHECK-NEXT:    ret3061entry:3062  %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8(3063    <vscale x 8 x i64> %0,3064    ptr %1,3065    <vscale x 8 x i8> %2,3066    <vscale x 8 x i1> %3,3067    iXLen %4, iXLen 1)3068 3069  ret <vscale x 8 x i64> %a3070}3071 3072define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3073; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8:3074; CHECK:       # %bb.0: # %entry3075; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma3076; CHECK-NEXT:    vloxei8.v v9, (a0), v83077; CHECK-NEXT:    vmv1r.v v8, v93078; CHECK-NEXT:    ret3079entry:3080  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8(3081    <vscale x 1 x half> poison,3082    ptr %0,3083    <vscale x 1 x i8> %1,3084    iXLen %2)3085 3086  ret <vscale x 1 x half> %a3087}3088 3089define <vscale x 1 x half> @intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3090; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i8:3091; CHECK:       # %bb.0: # %entry3092; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu3093; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3094; CHECK-NEXT:    ret3095entry:3096  %a = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8(3097    <vscale x 1 x half> %0,3098    ptr %1,3099    <vscale x 1 x i8> %2,3100    <vscale x 1 x i1> %3,3101    iXLen %4, iXLen 1)3102 3103  ret <vscale x 1 x half> %a3104}3105 3106define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3107; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8:3108; CHECK:       # %bb.0: # %entry3109; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma3110; CHECK-NEXT:    vloxei8.v v9, (a0), v83111; CHECK-NEXT:    vmv1r.v v8, v93112; CHECK-NEXT:    ret3113entry:3114  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8(3115    <vscale x 2 x half> poison,3116    ptr %0,3117    <vscale x 2 x i8> %1,3118    iXLen %2)3119 3120  ret <vscale x 2 x half> %a3121}3122 3123define <vscale x 2 x half> @intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3124; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i8:3125; CHECK:       # %bb.0: # %entry3126; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu3127; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3128; CHECK-NEXT:    ret3129entry:3130  %a = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8(3131    <vscale x 2 x half> %0,3132    ptr %1,3133    <vscale x 2 x i8> %2,3134    <vscale x 2 x i1> %3,3135    iXLen %4, iXLen 1)3136 3137  ret <vscale x 2 x half> %a3138}3139 3140define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3141; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8:3142; CHECK:       # %bb.0: # %entry3143; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma3144; CHECK-NEXT:    vloxei8.v v9, (a0), v83145; CHECK-NEXT:    vmv.v.v v8, v93146; CHECK-NEXT:    ret3147entry:3148  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8(3149    <vscale x 4 x half> poison,3150    ptr %0,3151    <vscale x 4 x i8> %1,3152    iXLen %2)3153 3154  ret <vscale x 4 x half> %a3155}3156 3157define <vscale x 4 x half> @intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3158; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i8:3159; CHECK:       # %bb.0: # %entry3160; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu3161; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3162; CHECK-NEXT:    ret3163entry:3164  %a = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8(3165    <vscale x 4 x half> %0,3166    ptr %1,3167    <vscale x 4 x i8> %2,3168    <vscale x 4 x i1> %3,3169    iXLen %4, iXLen 1)3170 3171  ret <vscale x 4 x half> %a3172}3173 3174define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3175; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8:3176; CHECK:       # %bb.0: # %entry3177; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma3178; CHECK-NEXT:    vmv1r.v v10, v83179; CHECK-NEXT:    vloxei8.v v8, (a0), v103180; CHECK-NEXT:    ret3181entry:3182  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8(3183    <vscale x 8 x half> poison,3184    ptr %0,3185    <vscale x 8 x i8> %1,3186    iXLen %2)3187 3188  ret <vscale x 8 x half> %a3189}3190 3191define <vscale x 8 x half> @intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3192; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i8:3193; CHECK:       # %bb.0: # %entry3194; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu3195; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t3196; CHECK-NEXT:    ret3197entry:3198  %a = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8(3199    <vscale x 8 x half> %0,3200    ptr %1,3201    <vscale x 8 x i8> %2,3202    <vscale x 8 x i1> %3,3203    iXLen %4, iXLen 1)3204 3205  ret <vscale x 8 x half> %a3206}3207 3208define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3209; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8:3210; CHECK:       # %bb.0: # %entry3211; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma3212; CHECK-NEXT:    vmv2r.v v12, v83213; CHECK-NEXT:    vloxei8.v v8, (a0), v123214; CHECK-NEXT:    ret3215entry:3216  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8(3217    <vscale x 16 x half> poison,3218    ptr %0,3219    <vscale x 16 x i8> %1,3220    iXLen %2)3221 3222  ret <vscale x 16 x half> %a3223}3224 3225define <vscale x 16 x half> @intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3226; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i8:3227; CHECK:       # %bb.0: # %entry3228; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu3229; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t3230; CHECK-NEXT:    ret3231entry:3232  %a = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8(3233    <vscale x 16 x half> %0,3234    ptr %1,3235    <vscale x 16 x i8> %2,3236    <vscale x 16 x i1> %3,3237    iXLen %4, iXLen 1)3238 3239  ret <vscale x 16 x half> %a3240}3241 3242define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {3243; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8:3244; CHECK:       # %bb.0: # %entry3245; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma3246; CHECK-NEXT:    vmv4r.v v16, v83247; CHECK-NEXT:    vloxei8.v v8, (a0), v163248; CHECK-NEXT:    ret3249entry:3250  %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8(3251    <vscale x 32 x half> poison,3252    ptr %0,3253    <vscale x 32 x i8> %1,3254    iXLen %2)3255 3256  ret <vscale x 32 x half> %a3257}3258 3259define <vscale x 32 x half> @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {3260; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8:3261; CHECK:       # %bb.0: # %entry3262; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu3263; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t3264; CHECK-NEXT:    ret3265entry:3266  %a = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8(3267    <vscale x 32 x half> %0,3268    ptr %1,3269    <vscale x 32 x i8> %2,3270    <vscale x 32 x i1> %3,3271    iXLen %4, iXLen 1)3272 3273  ret <vscale x 32 x half> %a3274}3275 3276define <vscale x 1 x bfloat> @intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {3277; CHECK-LABEL: intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i32:3278; CHECK:       # %bb.0: # %entry3279; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma3280; CHECK-NEXT:    vloxei32.v v9, (a0), v83281; CHECK-NEXT:    vmv1r.v v8, v93282; CHECK-NEXT:    ret3283entry:3284  %a = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.nxv1i32(3285    <vscale x 1 x bfloat> poison,3286    ptr %0,3287    <vscale x 1 x i32> %1,3288    iXLen %2)3289 3290  ret <vscale x 1 x bfloat> %a3291}3292 3293define <vscale x 1 x bfloat> @intrinsic_vloxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3294; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32:3295; CHECK:       # %bb.0: # %entry3296; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu3297; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t3298; CHECK-NEXT:    ret3299entry:3300  %a = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i32(3301    <vscale x 1 x bfloat> %0,3302    ptr %1,3303    <vscale x 1 x i32> %2,3304    <vscale x 1 x i1> %3,3305    iXLen %4, iXLen 1)3306 3307  ret <vscale x 1 x bfloat> %a3308}3309 3310define <vscale x 2 x bfloat> @intrinsic_vloxei_v_nxv2bf16_nxv2bf16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {3311; CHECK-LABEL: intrinsic_vloxei_v_nxv2bf16_nxv2bf16_nxv2i32:3312; CHECK:       # %bb.0: # %entry3313; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma3314; CHECK-NEXT:    vloxei32.v v9, (a0), v83315; CHECK-NEXT:    vmv1r.v v8, v93316; CHECK-NEXT:    ret3317entry:3318  %a = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.nxv2i32(3319    <vscale x 2 x bfloat> poison,3320    ptr %0,3321    <vscale x 2 x i32> %1,3322    iXLen %2)3323 3324  ret <vscale x 2 x bfloat> %a3325}3326 3327define <vscale x 2 x bfloat> @intrinsic_vloxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3328; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32:3329; CHECK:       # %bb.0: # %entry3330; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu3331; CHECK-NEXT:    vloxei32.v v8, (a0), v9, v0.t3332; CHECK-NEXT:    ret3333entry:3334  %a = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i32(3335    <vscale x 2 x bfloat> %0,3336    ptr %1,3337    <vscale x 2 x i32> %2,3338    <vscale x 2 x i1> %3,3339    iXLen %4, iXLen 1)3340 3341  ret <vscale x 2 x bfloat> %a3342}3343 3344define <vscale x 4 x bfloat> @intrinsic_vloxei_v_nxv4bf16_nxv4bf16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {3345; CHECK-LABEL: intrinsic_vloxei_v_nxv4bf16_nxv4bf16_nxv4i32:3346; CHECK:       # %bb.0: # %entry3347; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma3348; CHECK-NEXT:    vloxei32.v v10, (a0), v83349; CHECK-NEXT:    vmv.v.v v8, v103350; CHECK-NEXT:    ret3351entry:3352  %a = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.nxv4i32(3353    <vscale x 4 x bfloat> poison,3354    ptr %0,3355    <vscale x 4 x i32> %1,3356    iXLen %2)3357 3358  ret <vscale x 4 x bfloat> %a3359}3360 3361define <vscale x 4 x bfloat> @intrinsic_vloxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3362; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32:3363; CHECK:       # %bb.0: # %entry3364; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu3365; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t3366; CHECK-NEXT:    ret3367entry:3368  %a = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i32(3369    <vscale x 4 x bfloat> %0,3370    ptr %1,3371    <vscale x 4 x i32> %2,3372    <vscale x 4 x i1> %3,3373    iXLen %4, iXLen 1)3374 3375  ret <vscale x 4 x bfloat> %a3376}3377 3378define <vscale x 8 x bfloat> @intrinsic_vloxei_v_nxv8bf16_nxv8bf16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {3379; CHECK-LABEL: intrinsic_vloxei_v_nxv8bf16_nxv8bf16_nxv8i32:3380; CHECK:       # %bb.0: # %entry3381; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma3382; CHECK-NEXT:    vloxei32.v v12, (a0), v83383; CHECK-NEXT:    vmv.v.v v8, v123384; CHECK-NEXT:    ret3385entry:3386  %a = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.nxv8i32(3387    <vscale x 8 x bfloat> poison,3388    ptr %0,3389    <vscale x 8 x i32> %1,3390    iXLen %2)3391 3392  ret <vscale x 8 x bfloat> %a3393}3394 3395define <vscale x 8 x bfloat> @intrinsic_vloxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3396; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32:3397; CHECK:       # %bb.0: # %entry3398; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu3399; CHECK-NEXT:    vloxei32.v v8, (a0), v12, v0.t3400; CHECK-NEXT:    ret3401entry:3402  %a = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i32(3403    <vscale x 8 x bfloat> %0,3404    ptr %1,3405    <vscale x 8 x i32> %2,3406    <vscale x 8 x i1> %3,3407    iXLen %4, iXLen 1)3408 3409  ret <vscale x 8 x bfloat> %a3410}3411 3412define <vscale x 16 x bfloat> @intrinsic_vloxei_v_nxv16bf16_nxv16bf16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {3413; CHECK-LABEL: intrinsic_vloxei_v_nxv16bf16_nxv16bf16_nxv16i32:3414; CHECK:       # %bb.0: # %entry3415; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma3416; CHECK-NEXT:    vloxei32.v v16, (a0), v83417; CHECK-NEXT:    vmv.v.v v8, v163418; CHECK-NEXT:    ret3419entry:3420  %a = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.nxv16i32(3421    <vscale x 16 x bfloat> poison,3422    ptr %0,3423    <vscale x 16 x i32> %1,3424    iXLen %2)3425 3426  ret <vscale x 16 x bfloat> %a3427}3428 3429define <vscale x 16 x bfloat> @intrinsic_vloxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3430; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32:3431; CHECK:       # %bb.0: # %entry3432; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu3433; CHECK-NEXT:    vloxei32.v v8, (a0), v16, v0.t3434; CHECK-NEXT:    ret3435entry:3436  %a = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i32(3437    <vscale x 16 x bfloat> %0,3438    ptr %1,3439    <vscale x 16 x i32> %2,3440    <vscale x 16 x i1> %3,3441    iXLen %4, iXLen 1)3442 3443  ret <vscale x 16 x bfloat> %a3444}3445 3446define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3447; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8:3448; CHECK:       # %bb.0: # %entry3449; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma3450; CHECK-NEXT:    vloxei8.v v9, (a0), v83451; CHECK-NEXT:    vmv1r.v v8, v93452; CHECK-NEXT:    ret3453entry:3454  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8(3455    <vscale x 1 x float> poison,3456    ptr %0,3457    <vscale x 1 x i8> %1,3458    iXLen %2)3459 3460  ret <vscale x 1 x float> %a3461}3462 3463define <vscale x 1 x float> @intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3464; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i8:3465; CHECK:       # %bb.0: # %entry3466; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu3467; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3468; CHECK-NEXT:    ret3469entry:3470  %a = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8(3471    <vscale x 1 x float> %0,3472    ptr %1,3473    <vscale x 1 x i8> %2,3474    <vscale x 1 x i1> %3,3475    iXLen %4, iXLen 1)3476 3477  ret <vscale x 1 x float> %a3478}3479 3480define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3481; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8:3482; CHECK:       # %bb.0: # %entry3483; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma3484; CHECK-NEXT:    vloxei8.v v9, (a0), v83485; CHECK-NEXT:    vmv.v.v v8, v93486; CHECK-NEXT:    ret3487entry:3488  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8(3489    <vscale x 2 x float> poison,3490    ptr %0,3491    <vscale x 2 x i8> %1,3492    iXLen %2)3493 3494  ret <vscale x 2 x float> %a3495}3496 3497define <vscale x 2 x float> @intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3498; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i8:3499; CHECK:       # %bb.0: # %entry3500; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu3501; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3502; CHECK-NEXT:    ret3503entry:3504  %a = call <vscale x 2 x float> @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8(3505    <vscale x 2 x float> %0,3506    ptr %1,3507    <vscale x 2 x i8> %2,3508    <vscale x 2 x i1> %3,3509    iXLen %4, iXLen 1)3510 3511  ret <vscale x 2 x float> %a3512}3513 3514define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3515; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8:3516; CHECK:       # %bb.0: # %entry3517; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3518; CHECK-NEXT:    vmv1r.v v10, v83519; CHECK-NEXT:    vloxei8.v v8, (a0), v103520; CHECK-NEXT:    ret3521entry:3522  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8(3523    <vscale x 4 x float> poison,3524    ptr %0,3525    <vscale x 4 x i8> %1,3526    iXLen %2)3527 3528  ret <vscale x 4 x float> %a3529}3530 3531define <vscale x 4 x float> @intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3532; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i8:3533; CHECK:       # %bb.0: # %entry3534; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu3535; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t3536; CHECK-NEXT:    ret3537entry:3538  %a = call <vscale x 4 x float> @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8(3539    <vscale x 4 x float> %0,3540    ptr %1,3541    <vscale x 4 x i8> %2,3542    <vscale x 4 x i1> %3,3543    iXLen %4, iXLen 1)3544 3545  ret <vscale x 4 x float> %a3546}3547 3548define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3549; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8:3550; CHECK:       # %bb.0: # %entry3551; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma3552; CHECK-NEXT:    vmv1r.v v12, v83553; CHECK-NEXT:    vloxei8.v v8, (a0), v123554; CHECK-NEXT:    ret3555entry:3556  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8(3557    <vscale x 8 x float> poison,3558    ptr %0,3559    <vscale x 8 x i8> %1,3560    iXLen %2)3561 3562  ret <vscale x 8 x float> %a3563}3564 3565define <vscale x 8 x float> @intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3566; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i8:3567; CHECK:       # %bb.0: # %entry3568; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu3569; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t3570; CHECK-NEXT:    ret3571entry:3572  %a = call <vscale x 8 x float> @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8(3573    <vscale x 8 x float> %0,3574    ptr %1,3575    <vscale x 8 x i8> %2,3576    <vscale x 8 x i1> %3,3577    iXLen %4, iXLen 1)3578 3579  ret <vscale x 8 x float> %a3580}3581 3582define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3583; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8:3584; CHECK:       # %bb.0: # %entry3585; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma3586; CHECK-NEXT:    vmv2r.v v16, v83587; CHECK-NEXT:    vloxei8.v v8, (a0), v163588; CHECK-NEXT:    ret3589entry:3590  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8(3591    <vscale x 16 x float> poison,3592    ptr %0,3593    <vscale x 16 x i8> %1,3594    iXLen %2)3595 3596  ret <vscale x 16 x float> %a3597}3598 3599define <vscale x 16 x float> @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3600; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8:3601; CHECK:       # %bb.0: # %entry3602; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu3603; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t3604; CHECK-NEXT:    ret3605entry:3606  %a = call <vscale x 16 x float> @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8(3607    <vscale x 16 x float> %0,3608    ptr %1,3609    <vscale x 16 x i8> %2,3610    <vscale x 16 x i1> %3,3611    iXLen %4, iXLen 1)3612 3613  ret <vscale x 16 x float> %a3614}3615 3616define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3617; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8:3618; CHECK:       # %bb.0: # %entry3619; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma3620; CHECK-NEXT:    vloxei8.v v9, (a0), v83621; CHECK-NEXT:    vmv.v.v v8, v93622; CHECK-NEXT:    ret3623entry:3624  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8(3625    <vscale x 1 x double> poison,3626    ptr %0,3627    <vscale x 1 x i8> %1,3628    iXLen %2)3629 3630  ret <vscale x 1 x double> %a3631}3632 3633define <vscale x 1 x double> @intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3634; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i8:3635; CHECK:       # %bb.0: # %entry3636; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu3637; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t3638; CHECK-NEXT:    ret3639entry:3640  %a = call <vscale x 1 x double> @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8(3641    <vscale x 1 x double> %0,3642    ptr %1,3643    <vscale x 1 x i8> %2,3644    <vscale x 1 x i1> %3,3645    iXLen %4, iXLen 1)3646 3647  ret <vscale x 1 x double> %a3648}3649 3650define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3651; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8:3652; CHECK:       # %bb.0: # %entry3653; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3654; CHECK-NEXT:    vmv1r.v v10, v83655; CHECK-NEXT:    vloxei8.v v8, (a0), v103656; CHECK-NEXT:    ret3657entry:3658  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8(3659    <vscale x 2 x double> poison,3660    ptr %0,3661    <vscale x 2 x i8> %1,3662    iXLen %2)3663 3664  ret <vscale x 2 x double> %a3665}3666 3667define <vscale x 2 x double> @intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3668; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i8:3669; CHECK:       # %bb.0: # %entry3670; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu3671; CHECK-NEXT:    vloxei8.v v8, (a0), v10, v0.t3672; CHECK-NEXT:    ret3673entry:3674  %a = call <vscale x 2 x double> @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8(3675    <vscale x 2 x double> %0,3676    ptr %1,3677    <vscale x 2 x i8> %2,3678    <vscale x 2 x i1> %3,3679    iXLen %4, iXLen 1)3680 3681  ret <vscale x 2 x double> %a3682}3683 3684define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3685; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8:3686; CHECK:       # %bb.0: # %entry3687; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3688; CHECK-NEXT:    vmv1r.v v12, v83689; CHECK-NEXT:    vloxei8.v v8, (a0), v123690; CHECK-NEXT:    ret3691entry:3692  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8(3693    <vscale x 4 x double> poison,3694    ptr %0,3695    <vscale x 4 x i8> %1,3696    iXLen %2)3697 3698  ret <vscale x 4 x double> %a3699}3700 3701define <vscale x 4 x double> @intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3702; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i8:3703; CHECK:       # %bb.0: # %entry3704; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3705; CHECK-NEXT:    vloxei8.v v8, (a0), v12, v0.t3706; CHECK-NEXT:    ret3707entry:3708  %a = call <vscale x 4 x double> @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8(3709    <vscale x 4 x double> %0,3710    ptr %1,3711    <vscale x 4 x i8> %2,3712    <vscale x 4 x i1> %3,3713    iXLen %4, iXLen 1)3714 3715  ret <vscale x 4 x double> %a3716}3717 3718define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3719; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8:3720; CHECK:       # %bb.0: # %entry3721; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3722; CHECK-NEXT:    vmv1r.v v16, v83723; CHECK-NEXT:    vloxei8.v v8, (a0), v163724; CHECK-NEXT:    ret3725entry:3726  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8(3727    <vscale x 8 x double> poison,3728    ptr %0,3729    <vscale x 8 x i8> %1,3730    iXLen %2)3731 3732  ret <vscale x 8 x double> %a3733}3734 3735define <vscale x 8 x double> @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3736; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8:3737; CHECK:       # %bb.0: # %entry3738; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3739; CHECK-NEXT:    vloxei8.v v8, (a0), v16, v0.t3740; CHECK-NEXT:    ret3741entry:3742  %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8(3743    <vscale x 8 x double> %0,3744    ptr %1,3745    <vscale x 8 x i8> %2,3746    <vscale x 8 x i1> %3,3747    iXLen %4, iXLen 1)3748 3749  ret <vscale x 8 x double> %a3750}3751