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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i64> @intrinsic_vlse_v_nxv1i64_nxv1i64(ptr %0, iXLen %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma11; CHECK-NEXT: vlse64.v v8, (a0), a112; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i64> @llvm.riscv.vlse.nxv1i64(15 <vscale x 1 x i64> poison,16 ptr %0,17 iXLen %1,18 iXLen %2)19 20 ret <vscale x 1 x i64> %a21}22 23define <vscale x 1 x i64> @intrinsic_vlse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu27; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i64> @llvm.riscv.vlse.mask.nxv1i64(31 <vscale x 1 x i64> %0,32 ptr %1,33 iXLen %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i64> %a38}39 40define <vscale x 2 x i64> @intrinsic_vlse_v_nxv2i64_nxv2i64(ptr %0, iXLen %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma44; CHECK-NEXT: vlse64.v v8, (a0), a145; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i64> @llvm.riscv.vlse.nxv2i64(48 <vscale x 2 x i64> poison,49 ptr %0,50 iXLen %1,51 iXLen %2)52 53 ret <vscale x 2 x i64> %a54}55 56define <vscale x 2 x i64> @intrinsic_vlse_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i64_nxv2i64:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu60; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i64> @llvm.riscv.vlse.mask.nxv2i64(64 <vscale x 2 x i64> %0,65 ptr %1,66 iXLen %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i64> %a71}72 73define <vscale x 4 x i64> @intrinsic_vlse_v_nxv4i64_nxv4i64(ptr %0, iXLen %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma77; CHECK-NEXT: vlse64.v v8, (a0), a178; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i64> @llvm.riscv.vlse.nxv4i64(81 <vscale x 4 x i64> poison,82 ptr %0,83 iXLen %1,84 iXLen %2)85 86 ret <vscale x 4 x i64> %a87}88 89define <vscale x 4 x i64> @intrinsic_vlse_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i64_nxv4i64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu93; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i64> @llvm.riscv.vlse.mask.nxv4i64(97 <vscale x 4 x i64> %0,98 ptr %1,99 iXLen %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i64> %a104}105 106define <vscale x 8 x i64> @intrinsic_vlse_v_nxv8i64_nxv8i64(ptr %0, iXLen %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma110; CHECK-NEXT: vlse64.v v8, (a0), a1111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i64> @llvm.riscv.vlse.nxv8i64(114 <vscale x 8 x i64> poison,115 ptr %0,116 iXLen %1,117 iXLen %2)118 119 ret <vscale x 8 x i64> %a120}121 122define <vscale x 8 x i64> @intrinsic_vlse_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i64_nxv8i64:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu126; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i64> @llvm.riscv.vlse.mask.nxv8i64(130 <vscale x 8 x i64> %0,131 ptr %1,132 iXLen %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x i64> %a137}138 139define <vscale x 1 x double> @intrinsic_vlse_v_nxv1f64_nxv1f64(ptr %0, iXLen %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma143; CHECK-NEXT: vlse64.v v8, (a0), a1144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 1 x double> @llvm.riscv.vlse.nxv1f64(147 <vscale x 1 x double> poison,148 ptr %0,149 iXLen %1,150 iXLen %2)151 152 ret <vscale x 1 x double> %a153}154 155define <vscale x 1 x double> @intrinsic_vlse_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f64_nxv1f64:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu159; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 1 x double> @llvm.riscv.vlse.mask.nxv1f64(163 <vscale x 1 x double> %0,164 ptr %1,165 iXLen %2,166 <vscale x 1 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 1 x double> %a170}171 172define <vscale x 2 x double> @intrinsic_vlse_v_nxv2f64_nxv2f64(ptr %0, iXLen %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma176; CHECK-NEXT: vlse64.v v8, (a0), a1177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 2 x double> @llvm.riscv.vlse.nxv2f64(180 <vscale x 2 x double> poison,181 ptr %0,182 iXLen %1,183 iXLen %2)184 185 ret <vscale x 2 x double> %a186}187 188define <vscale x 2 x double> @intrinsic_vlse_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f64_nxv2f64:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu192; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 2 x double> @llvm.riscv.vlse.mask.nxv2f64(196 <vscale x 2 x double> %0,197 ptr %1,198 iXLen %2,199 <vscale x 2 x i1> %3,200 iXLen %4, iXLen 1)201 202 ret <vscale x 2 x double> %a203}204 205define <vscale x 4 x double> @intrinsic_vlse_v_nxv4f64_nxv4f64(ptr %0, iXLen %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma209; CHECK-NEXT: vlse64.v v8, (a0), a1210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 4 x double> @llvm.riscv.vlse.nxv4f64(213 <vscale x 4 x double> poison,214 ptr %0,215 iXLen %1,216 iXLen %2)217 218 ret <vscale x 4 x double> %a219}220 221define <vscale x 4 x double> @intrinsic_vlse_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f64_nxv4f64:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu225; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 4 x double> @llvm.riscv.vlse.mask.nxv4f64(229 <vscale x 4 x double> %0,230 ptr %1,231 iXLen %2,232 <vscale x 4 x i1> %3,233 iXLen %4, iXLen 1)234 235 ret <vscale x 4 x double> %a236}237 238define <vscale x 8 x double> @intrinsic_vlse_v_nxv8f64_nxv8f64(ptr %0, iXLen %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma242; CHECK-NEXT: vlse64.v v8, (a0), a1243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 8 x double> @llvm.riscv.vlse.nxv8f64(246 <vscale x 8 x double> poison,247 ptr %0,248 iXLen %1,249 iXLen %2)250 251 ret <vscale x 8 x double> %a252}253 254define <vscale x 8 x double> @intrinsic_vlse_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f64_nxv8f64:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu258; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 8 x double> @llvm.riscv.vlse.mask.nxv8f64(262 <vscale x 8 x double> %0,263 ptr %1,264 iXLen %2,265 <vscale x 8 x i1> %3,266 iXLen %4, iXLen 1)267 268 ret <vscale x 8 x double> %a269}270 271define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(ptr %0, iXLen %1, iXLen %2) nounwind {272; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma275; CHECK-NEXT: vlse32.v v8, (a0), a1276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(279 <vscale x 1 x i32> poison,280 ptr %0,281 iXLen %1,282 iXLen %2)283 284 ret <vscale x 1 x i32> %a285}286 287define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu291; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(295 <vscale x 1 x i32> %0,296 ptr %1,297 iXLen %2,298 <vscale x 1 x i1> %3,299 iXLen %4, iXLen 1)300 301 ret <vscale x 1 x i32> %a302}303 304define <vscale x 2 x i32> @intrinsic_vlse_v_nxv2i32_nxv2i32(ptr %0, iXLen %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma308; CHECK-NEXT: vlse32.v v8, (a0), a1309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 2 x i32> @llvm.riscv.vlse.nxv2i32(312 <vscale x 2 x i32> poison,313 ptr %0,314 iXLen %1,315 iXLen %2)316 317 ret <vscale x 2 x i32> %a318}319 320define <vscale x 2 x i32> @intrinsic_vlse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu324; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 2 x i32> @llvm.riscv.vlse.mask.nxv2i32(328 <vscale x 2 x i32> %0,329 ptr %1,330 iXLen %2,331 <vscale x 2 x i1> %3,332 iXLen %4, iXLen 1)333 334 ret <vscale x 2 x i32> %a335}336 337define <vscale x 4 x i32> @intrinsic_vlse_v_nxv4i32_nxv4i32(ptr %0, iXLen %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma341; CHECK-NEXT: vlse32.v v8, (a0), a1342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 4 x i32> @llvm.riscv.vlse.nxv4i32(345 <vscale x 4 x i32> poison,346 ptr %0,347 iXLen %1,348 iXLen %2)349 350 ret <vscale x 4 x i32> %a351}352 353define <vscale x 4 x i32> @intrinsic_vlse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu357; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 4 x i32> @llvm.riscv.vlse.mask.nxv4i32(361 <vscale x 4 x i32> %0,362 ptr %1,363 iXLen %2,364 <vscale x 4 x i1> %3,365 iXLen %4, iXLen 1)366 367 ret <vscale x 4 x i32> %a368}369 370define <vscale x 8 x i32> @intrinsic_vlse_v_nxv8i32_nxv8i32(ptr %0, iXLen %1, iXLen %2) nounwind {371; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma374; CHECK-NEXT: vlse32.v v8, (a0), a1375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 8 x i32> @llvm.riscv.vlse.nxv8i32(378 <vscale x 8 x i32> poison,379 ptr %0,380 iXLen %1,381 iXLen %2)382 383 ret <vscale x 8 x i32> %a384}385 386define <vscale x 8 x i32> @intrinsic_vlse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu390; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 8 x i32> @llvm.riscv.vlse.mask.nxv8i32(394 <vscale x 8 x i32> %0,395 ptr %1,396 iXLen %2,397 <vscale x 8 x i1> %3,398 iXLen %4, iXLen 1)399 400 ret <vscale x 8 x i32> %a401}402 403define <vscale x 16 x i32> @intrinsic_vlse_v_nxv16i32_nxv16i32(ptr %0, iXLen %1, iXLen %2) nounwind {404; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma407; CHECK-NEXT: vlse32.v v8, (a0), a1408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 16 x i32> @llvm.riscv.vlse.nxv16i32(411 <vscale x 16 x i32> poison,412 ptr %0,413 iXLen %1,414 iXLen %2)415 416 ret <vscale x 16 x i32> %a417}418 419define <vscale x 16 x i32> @intrinsic_vlse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu423; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 16 x i32> @llvm.riscv.vlse.mask.nxv16i32(427 <vscale x 16 x i32> %0,428 ptr %1,429 iXLen %2,430 <vscale x 16 x i1> %3,431 iXLen %4, iXLen 1)432 433 ret <vscale x 16 x i32> %a434}435 436define <vscale x 1 x float> @intrinsic_vlse_v_nxv1f32_nxv1f32(ptr %0, iXLen %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma440; CHECK-NEXT: vlse32.v v8, (a0), a1441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32(444 <vscale x 1 x float> poison,445 ptr %0,446 iXLen %1,447 iXLen %2)448 449 ret <vscale x 1 x float> %a450}451 452define <vscale x 1 x float> @intrinsic_vlse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu456; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32(460 <vscale x 1 x float> %0,461 ptr %1,462 iXLen %2,463 <vscale x 1 x i1> %3,464 iXLen %4, iXLen 1)465 466 ret <vscale x 1 x float> %a467}468 469define <vscale x 2 x float> @intrinsic_vlse_v_nxv2f32_nxv2f32(ptr %0, iXLen %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma473; CHECK-NEXT: vlse32.v v8, (a0), a1474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 2 x float> @llvm.riscv.vlse.nxv2f32(477 <vscale x 2 x float> poison,478 ptr %0,479 iXLen %1,480 iXLen %2)481 482 ret <vscale x 2 x float> %a483}484 485define <vscale x 2 x float> @intrinsic_vlse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu489; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 2 x float> @llvm.riscv.vlse.mask.nxv2f32(493 <vscale x 2 x float> %0,494 ptr %1,495 iXLen %2,496 <vscale x 2 x i1> %3,497 iXLen %4, iXLen 1)498 499 ret <vscale x 2 x float> %a500}501 502define <vscale x 4 x float> @intrinsic_vlse_v_nxv4f32_nxv4f32(ptr %0, iXLen %1, iXLen %2) nounwind {503; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma506; CHECK-NEXT: vlse32.v v8, (a0), a1507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 4 x float> @llvm.riscv.vlse.nxv4f32(510 <vscale x 4 x float> poison,511 ptr %0,512 iXLen %1,513 iXLen %2)514 515 ret <vscale x 4 x float> %a516}517 518define <vscale x 4 x float> @intrinsic_vlse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu522; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 4 x float> @llvm.riscv.vlse.mask.nxv4f32(526 <vscale x 4 x float> %0,527 ptr %1,528 iXLen %2,529 <vscale x 4 x i1> %3,530 iXLen %4, iXLen 1)531 532 ret <vscale x 4 x float> %a533}534 535define <vscale x 8 x float> @intrinsic_vlse_v_nxv8f32_nxv8f32(ptr %0, iXLen %1, iXLen %2) nounwind {536; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma539; CHECK-NEXT: vlse32.v v8, (a0), a1540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 8 x float> @llvm.riscv.vlse.nxv8f32(543 <vscale x 8 x float> poison,544 ptr %0,545 iXLen %1,546 iXLen %2)547 548 ret <vscale x 8 x float> %a549}550 551define <vscale x 8 x float> @intrinsic_vlse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu555; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 8 x float> @llvm.riscv.vlse.mask.nxv8f32(559 <vscale x 8 x float> %0,560 ptr %1,561 iXLen %2,562 <vscale x 8 x i1> %3,563 iXLen %4, iXLen 1)564 565 ret <vscale x 8 x float> %a566}567 568define <vscale x 16 x float> @intrinsic_vlse_v_nxv16f32_nxv16f32(ptr %0, iXLen %1, iXLen %2) nounwind {569; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma572; CHECK-NEXT: vlse32.v v8, (a0), a1573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 16 x float> @llvm.riscv.vlse.nxv16f32(576 <vscale x 16 x float> poison,577 ptr %0,578 iXLen %1,579 iXLen %2)580 581 ret <vscale x 16 x float> %a582}583 584define <vscale x 16 x float> @intrinsic_vlse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu588; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 16 x float> @llvm.riscv.vlse.mask.nxv16f32(592 <vscale x 16 x float> %0,593 ptr %1,594 iXLen %2,595 <vscale x 16 x i1> %3,596 iXLen %4, iXLen 1)597 598 ret <vscale x 16 x float> %a599}600 601define <vscale x 1 x i16> @intrinsic_vlse_v_nxv1i16_nxv1i16(ptr %0, iXLen %1, iXLen %2) nounwind {602; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma605; CHECK-NEXT: vlse16.v v8, (a0), a1606; CHECK-NEXT: ret607entry:608 %a = call <vscale x 1 x i16> @llvm.riscv.vlse.nxv1i16(609 <vscale x 1 x i16> poison,610 ptr %0,611 iXLen %1,612 iXLen %2)613 614 ret <vscale x 1 x i16> %a615}616 617define <vscale x 1 x i16> @intrinsic_vlse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {618; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu621; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t622; CHECK-NEXT: ret623entry:624 %a = call <vscale x 1 x i16> @llvm.riscv.vlse.mask.nxv1i16(625 <vscale x 1 x i16> %0,626 ptr %1,627 iXLen %2,628 <vscale x 1 x i1> %3,629 iXLen %4, iXLen 1)630 631 ret <vscale x 1 x i16> %a632}633 634define <vscale x 2 x i16> @intrinsic_vlse_v_nxv2i16_nxv2i16(ptr %0, iXLen %1, iXLen %2) nounwind {635; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma638; CHECK-NEXT: vlse16.v v8, (a0), a1639; CHECK-NEXT: ret640entry:641 %a = call <vscale x 2 x i16> @llvm.riscv.vlse.nxv2i16(642 <vscale x 2 x i16> poison,643 ptr %0,644 iXLen %1,645 iXLen %2)646 647 ret <vscale x 2 x i16> %a648}649 650define <vscale x 2 x i16> @intrinsic_vlse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {651; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu654; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 2 x i16> @llvm.riscv.vlse.mask.nxv2i16(658 <vscale x 2 x i16> %0,659 ptr %1,660 iXLen %2,661 <vscale x 2 x i1> %3,662 iXLen %4, iXLen 1)663 664 ret <vscale x 2 x i16> %a665}666 667define <vscale x 4 x i16> @intrinsic_vlse_v_nxv4i16_nxv4i16(ptr %0, iXLen %1, iXLen %2) nounwind {668; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma671; CHECK-NEXT: vlse16.v v8, (a0), a1672; CHECK-NEXT: ret673entry:674 %a = call <vscale x 4 x i16> @llvm.riscv.vlse.nxv4i16(675 <vscale x 4 x i16> poison,676 ptr %0,677 iXLen %1,678 iXLen %2)679 680 ret <vscale x 4 x i16> %a681}682 683define <vscale x 4 x i16> @intrinsic_vlse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {684; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu687; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t688; CHECK-NEXT: ret689entry:690 %a = call <vscale x 4 x i16> @llvm.riscv.vlse.mask.nxv4i16(691 <vscale x 4 x i16> %0,692 ptr %1,693 iXLen %2,694 <vscale x 4 x i1> %3,695 iXLen %4, iXLen 1)696 697 ret <vscale x 4 x i16> %a698}699 700define <vscale x 8 x i16> @intrinsic_vlse_v_nxv8i16_nxv8i16(ptr %0, iXLen %1, iXLen %2) nounwind {701; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma704; CHECK-NEXT: vlse16.v v8, (a0), a1705; CHECK-NEXT: ret706entry:707 %a = call <vscale x 8 x i16> @llvm.riscv.vlse.nxv8i16(708 <vscale x 8 x i16> poison,709 ptr %0,710 iXLen %1,711 iXLen %2)712 713 ret <vscale x 8 x i16> %a714}715 716define <vscale x 8 x i16> @intrinsic_vlse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {717; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16:718; CHECK: # %bb.0: # %entry719; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu720; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t721; CHECK-NEXT: ret722entry:723 %a = call <vscale x 8 x i16> @llvm.riscv.vlse.mask.nxv8i16(724 <vscale x 8 x i16> %0,725 ptr %1,726 iXLen %2,727 <vscale x 8 x i1> %3,728 iXLen %4, iXLen 1)729 730 ret <vscale x 8 x i16> %a731}732 733define <vscale x 16 x i16> @intrinsic_vlse_v_nxv16i16_nxv16i16(ptr %0, iXLen %1, iXLen %2) nounwind {734; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma737; CHECK-NEXT: vlse16.v v8, (a0), a1738; CHECK-NEXT: ret739entry:740 %a = call <vscale x 16 x i16> @llvm.riscv.vlse.nxv16i16(741 <vscale x 16 x i16> poison,742 ptr %0,743 iXLen %1,744 iXLen %2)745 746 ret <vscale x 16 x i16> %a747}748 749define <vscale x 16 x i16> @intrinsic_vlse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {750; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu753; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t754; CHECK-NEXT: ret755entry:756 %a = call <vscale x 16 x i16> @llvm.riscv.vlse.mask.nxv16i16(757 <vscale x 16 x i16> %0,758 ptr %1,759 iXLen %2,760 <vscale x 16 x i1> %3,761 iXLen %4, iXLen 1)762 763 ret <vscale x 16 x i16> %a764}765 766define <vscale x 32 x i16> @intrinsic_vlse_v_nxv32i16_nxv32i16(ptr %0, iXLen %1, iXLen %2) nounwind {767; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma770; CHECK-NEXT: vlse16.v v8, (a0), a1771; CHECK-NEXT: ret772entry:773 %a = call <vscale x 32 x i16> @llvm.riscv.vlse.nxv32i16(774 <vscale x 32 x i16> poison,775 ptr %0,776 iXLen %1,777 iXLen %2)778 779 ret <vscale x 32 x i16> %a780}781 782define <vscale x 32 x i16> @intrinsic_vlse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {783; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu786; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t787; CHECK-NEXT: ret788entry:789 %a = call <vscale x 32 x i16> @llvm.riscv.vlse.mask.nxv32i16(790 <vscale x 32 x i16> %0,791 ptr %1,792 iXLen %2,793 <vscale x 32 x i1> %3,794 iXLen %4, iXLen 1)795 796 ret <vscale x 32 x i16> %a797}798 799define <vscale x 1 x half> @intrinsic_vlse_v_nxv1f16_nxv1f16(ptr %0, iXLen %1, iXLen %2) nounwind {800; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma803; CHECK-NEXT: vlse16.v v8, (a0), a1804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16(807 <vscale x 1 x half> poison,808 ptr %0,809 iXLen %1,810 iXLen %2)811 812 ret <vscale x 1 x half> %a813}814 815define <vscale x 1 x half> @intrinsic_vlse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {816; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu819; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t820; CHECK-NEXT: ret821entry:822 %a = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16(823 <vscale x 1 x half> %0,824 ptr %1,825 iXLen %2,826 <vscale x 1 x i1> %3,827 iXLen %4, iXLen 1)828 829 ret <vscale x 1 x half> %a830}831 832define <vscale x 2 x half> @intrinsic_vlse_v_nxv2f16_nxv2f16(ptr %0, iXLen %1, iXLen %2) nounwind {833; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma836; CHECK-NEXT: vlse16.v v8, (a0), a1837; CHECK-NEXT: ret838entry:839 %a = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16(840 <vscale x 2 x half> poison,841 ptr %0,842 iXLen %1,843 iXLen %2)844 845 ret <vscale x 2 x half> %a846}847 848define <vscale x 2 x half> @intrinsic_vlse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {849; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16:850; CHECK: # %bb.0: # %entry851; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu852; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t853; CHECK-NEXT: ret854entry:855 %a = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16(856 <vscale x 2 x half> %0,857 ptr %1,858 iXLen %2,859 <vscale x 2 x i1> %3,860 iXLen %4, iXLen 1)861 862 ret <vscale x 2 x half> %a863}864 865define <vscale x 4 x half> @intrinsic_vlse_v_nxv4f16_nxv4f16(ptr %0, iXLen %1, iXLen %2) nounwind {866; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma869; CHECK-NEXT: vlse16.v v8, (a0), a1870; CHECK-NEXT: ret871entry:872 %a = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16(873 <vscale x 4 x half> poison,874 ptr %0,875 iXLen %1,876 iXLen %2)877 878 ret <vscale x 4 x half> %a879}880 881define <vscale x 4 x half> @intrinsic_vlse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {882; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16:883; CHECK: # %bb.0: # %entry884; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu885; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t886; CHECK-NEXT: ret887entry:888 %a = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16(889 <vscale x 4 x half> %0,890 ptr %1,891 iXLen %2,892 <vscale x 4 x i1> %3,893 iXLen %4, iXLen 1)894 895 ret <vscale x 4 x half> %a896}897 898define <vscale x 8 x half> @intrinsic_vlse_v_nxv8f16_nxv8f16(ptr %0, iXLen %1, iXLen %2) nounwind {899; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma902; CHECK-NEXT: vlse16.v v8, (a0), a1903; CHECK-NEXT: ret904entry:905 %a = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16(906 <vscale x 8 x half> poison,907 ptr %0,908 iXLen %1,909 iXLen %2)910 911 ret <vscale x 8 x half> %a912}913 914define <vscale x 8 x half> @intrinsic_vlse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {915; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu918; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t919; CHECK-NEXT: ret920entry:921 %a = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16(922 <vscale x 8 x half> %0,923 ptr %1,924 iXLen %2,925 <vscale x 8 x i1> %3,926 iXLen %4, iXLen 1)927 928 ret <vscale x 8 x half> %a929}930 931define <vscale x 16 x half> @intrinsic_vlse_v_nxv16f16_nxv16f16(ptr %0, iXLen %1, iXLen %2) nounwind {932; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma935; CHECK-NEXT: vlse16.v v8, (a0), a1936; CHECK-NEXT: ret937entry:938 %a = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16(939 <vscale x 16 x half> poison,940 ptr %0,941 iXLen %1,942 iXLen %2)943 944 ret <vscale x 16 x half> %a945}946 947define <vscale x 16 x half> @intrinsic_vlse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {948; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu951; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t952; CHECK-NEXT: ret953entry:954 %a = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16(955 <vscale x 16 x half> %0,956 ptr %1,957 iXLen %2,958 <vscale x 16 x i1> %3,959 iXLen %4, iXLen 1)960 961 ret <vscale x 16 x half> %a962}963 964define <vscale x 32 x half> @intrinsic_vlse_v_nxv32f16_nxv32f16(ptr %0, iXLen %1, iXLen %2) nounwind {965; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma968; CHECK-NEXT: vlse16.v v8, (a0), a1969; CHECK-NEXT: ret970entry:971 %a = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16(972 <vscale x 32 x half> poison,973 ptr %0,974 iXLen %1,975 iXLen %2)976 977 ret <vscale x 32 x half> %a978}979 980define <vscale x 32 x half> @intrinsic_vlse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {981; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16:982; CHECK: # %bb.0: # %entry983; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu984; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t985; CHECK-NEXT: ret986entry:987 %a = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16(988 <vscale x 32 x half> %0,989 ptr %1,990 iXLen %2,991 <vscale x 32 x i1> %3,992 iXLen %4, iXLen 1)993 994 ret <vscale x 32 x half> %a995}996 997define <vscale x 1 x bfloat> @intrinsic_vlse_v_nxv1bf16_nxv1bf16(ptr %0, iXLen %1, iXLen %2) nounwind {998; CHECK-LABEL: intrinsic_vlse_v_nxv1bf16_nxv1bf16:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma1001; CHECK-NEXT: vlse16.v v8, (a0), a11002; CHECK-NEXT: ret1003entry:1004 %a = call <vscale x 1 x bfloat> @llvm.riscv.vlse.nxv1bf16(1005 <vscale x 1 x bfloat> poison,1006 ptr %0,1007 iXLen %1,1008 iXLen %2)1009 1010 ret <vscale x 1 x bfloat> %a1011}1012 1013define <vscale x 1 x bfloat> @intrinsic_vlse_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1014; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1bf16_nxv1bf16:1015; CHECK: # %bb.0: # %entry1016; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu1017; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1018; CHECK-NEXT: ret1019entry:1020 %a = call <vscale x 1 x bfloat> @llvm.riscv.vlse.mask.nxv1bf16(1021 <vscale x 1 x bfloat> %0,1022 ptr %1,1023 iXLen %2,1024 <vscale x 1 x i1> %3,1025 iXLen %4, iXLen 1)1026 1027 ret <vscale x 1 x bfloat> %a1028}1029 1030define <vscale x 2 x bfloat> @intrinsic_vlse_v_nxv2bf16_nxv2bf16(ptr %0, iXLen %1, iXLen %2) nounwind {1031; CHECK-LABEL: intrinsic_vlse_v_nxv2bf16_nxv2bf16:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma1034; CHECK-NEXT: vlse16.v v8, (a0), a11035; CHECK-NEXT: ret1036entry:1037 %a = call <vscale x 2 x bfloat> @llvm.riscv.vlse.nxv2bf16(1038 <vscale x 2 x bfloat> poison,1039 ptr %0,1040 iXLen %1,1041 iXLen %2)1042 1043 ret <vscale x 2 x bfloat> %a1044}1045 1046define <vscale x 2 x bfloat> @intrinsic_vlse_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1047; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2bf16_nxv2bf16:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu1050; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1051; CHECK-NEXT: ret1052entry:1053 %a = call <vscale x 2 x bfloat> @llvm.riscv.vlse.mask.nxv2bf16(1054 <vscale x 2 x bfloat> %0,1055 ptr %1,1056 iXLen %2,1057 <vscale x 2 x i1> %3,1058 iXLen %4, iXLen 1)1059 1060 ret <vscale x 2 x bfloat> %a1061}1062 1063define <vscale x 4 x bfloat> @intrinsic_vlse_v_nxv4bf16_nxv4bf16(ptr %0, iXLen %1, iXLen %2) nounwind {1064; CHECK-LABEL: intrinsic_vlse_v_nxv4bf16_nxv4bf16:1065; CHECK: # %bb.0: # %entry1066; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma1067; CHECK-NEXT: vlse16.v v8, (a0), a11068; CHECK-NEXT: ret1069entry:1070 %a = call <vscale x 4 x bfloat> @llvm.riscv.vlse.nxv4bf16(1071 <vscale x 4 x bfloat> poison,1072 ptr %0,1073 iXLen %1,1074 iXLen %2)1075 1076 ret <vscale x 4 x bfloat> %a1077}1078 1079define <vscale x 4 x bfloat> @intrinsic_vlse_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1080; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4bf16_nxv4bf16:1081; CHECK: # %bb.0: # %entry1082; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu1083; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1084; CHECK-NEXT: ret1085entry:1086 %a = call <vscale x 4 x bfloat> @llvm.riscv.vlse.mask.nxv4bf16(1087 <vscale x 4 x bfloat> %0,1088 ptr %1,1089 iXLen %2,1090 <vscale x 4 x i1> %3,1091 iXLen %4, iXLen 1)1092 1093 ret <vscale x 4 x bfloat> %a1094}1095 1096define <vscale x 8 x bfloat> @intrinsic_vlse_v_nxv8bf16_nxv8bf16(ptr %0, iXLen %1, iXLen %2) nounwind {1097; CHECK-LABEL: intrinsic_vlse_v_nxv8bf16_nxv8bf16:1098; CHECK: # %bb.0: # %entry1099; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma1100; CHECK-NEXT: vlse16.v v8, (a0), a11101; CHECK-NEXT: ret1102entry:1103 %a = call <vscale x 8 x bfloat> @llvm.riscv.vlse.nxv8bf16(1104 <vscale x 8 x bfloat> poison,1105 ptr %0,1106 iXLen %1,1107 iXLen %2)1108 1109 ret <vscale x 8 x bfloat> %a1110}1111 1112define <vscale x 8 x bfloat> @intrinsic_vlse_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1113; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8bf16_nxv8bf16:1114; CHECK: # %bb.0: # %entry1115; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu1116; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1117; CHECK-NEXT: ret1118entry:1119 %a = call <vscale x 8 x bfloat> @llvm.riscv.vlse.mask.nxv8bf16(1120 <vscale x 8 x bfloat> %0,1121 ptr %1,1122 iXLen %2,1123 <vscale x 8 x i1> %3,1124 iXLen %4, iXLen 1)1125 1126 ret <vscale x 8 x bfloat> %a1127}1128 1129define <vscale x 16 x bfloat> @intrinsic_vlse_v_nxv16bf16_nxv16bf16(ptr %0, iXLen %1, iXLen %2) nounwind {1130; CHECK-LABEL: intrinsic_vlse_v_nxv16bf16_nxv16bf16:1131; CHECK: # %bb.0: # %entry1132; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma1133; CHECK-NEXT: vlse16.v v8, (a0), a11134; CHECK-NEXT: ret1135entry:1136 %a = call <vscale x 16 x bfloat> @llvm.riscv.vlse.nxv16bf16(1137 <vscale x 16 x bfloat> poison,1138 ptr %0,1139 iXLen %1,1140 iXLen %2)1141 1142 ret <vscale x 16 x bfloat> %a1143}1144 1145define <vscale x 16 x bfloat> @intrinsic_vlse_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1146; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16bf16_nxv16bf16:1147; CHECK: # %bb.0: # %entry1148; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu1149; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1150; CHECK-NEXT: ret1151entry:1152 %a = call <vscale x 16 x bfloat> @llvm.riscv.vlse.mask.nxv16bf16(1153 <vscale x 16 x bfloat> %0,1154 ptr %1,1155 iXLen %2,1156 <vscale x 16 x i1> %3,1157 iXLen %4, iXLen 1)1158 1159 ret <vscale x 16 x bfloat> %a1160}1161 1162define <vscale x 32 x bfloat> @intrinsic_vlse_v_nxv32bf16_nxv32bf16(ptr %0, iXLen %1, iXLen %2) nounwind {1163; CHECK-LABEL: intrinsic_vlse_v_nxv32bf16_nxv32bf16:1164; CHECK: # %bb.0: # %entry1165; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1166; CHECK-NEXT: vlse16.v v8, (a0), a11167; CHECK-NEXT: ret1168entry:1169 %a = call <vscale x 32 x bfloat> @llvm.riscv.vlse.nxv32bf16(1170 <vscale x 32 x bfloat> poison,1171 ptr %0,1172 iXLen %1,1173 iXLen %2)1174 1175 ret <vscale x 32 x bfloat> %a1176}1177 1178define <vscale x 32 x bfloat> @intrinsic_vlse_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1179; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32bf16_nxv32bf16:1180; CHECK: # %bb.0: # %entry1181; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu1182; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t1183; CHECK-NEXT: ret1184entry:1185 %a = call <vscale x 32 x bfloat> @llvm.riscv.vlse.mask.nxv32bf16(1186 <vscale x 32 x bfloat> %0,1187 ptr %1,1188 iXLen %2,1189 <vscale x 32 x i1> %3,1190 iXLen %4, iXLen 1)1191 1192 ret <vscale x 32 x bfloat> %a1193}1194 1195define <vscale x 1 x i8> @intrinsic_vlse_v_nxv1i8_nxv1i8(ptr %0, iXLen %1, iXLen %2) nounwind {1196; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8:1197; CHECK: # %bb.0: # %entry1198; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma1199; CHECK-NEXT: vlse8.v v8, (a0), a11200; CHECK-NEXT: ret1201entry:1202 %a = call <vscale x 1 x i8> @llvm.riscv.vlse.nxv1i8(1203 <vscale x 1 x i8> poison,1204 ptr %0,1205 iXLen %1,1206 iXLen %2)1207 1208 ret <vscale x 1 x i8> %a1209}1210 1211define <vscale x 1 x i8> @intrinsic_vlse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1212; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8:1213; CHECK: # %bb.0: # %entry1214; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu1215; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1216; CHECK-NEXT: ret1217entry:1218 %a = call <vscale x 1 x i8> @llvm.riscv.vlse.mask.nxv1i8(1219 <vscale x 1 x i8> %0,1220 ptr %1,1221 iXLen %2,1222 <vscale x 1 x i1> %3,1223 iXLen %4, iXLen 1)1224 1225 ret <vscale x 1 x i8> %a1226}1227 1228define <vscale x 2 x i8> @intrinsic_vlse_v_nxv2i8_nxv2i8(ptr %0, iXLen %1, iXLen %2) nounwind {1229; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8:1230; CHECK: # %bb.0: # %entry1231; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma1232; CHECK-NEXT: vlse8.v v8, (a0), a11233; CHECK-NEXT: ret1234entry:1235 %a = call <vscale x 2 x i8> @llvm.riscv.vlse.nxv2i8(1236 <vscale x 2 x i8> poison,1237 ptr %0,1238 iXLen %1,1239 iXLen %2)1240 1241 ret <vscale x 2 x i8> %a1242}1243 1244define <vscale x 2 x i8> @intrinsic_vlse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1245; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8:1246; CHECK: # %bb.0: # %entry1247; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu1248; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1249; CHECK-NEXT: ret1250entry:1251 %a = call <vscale x 2 x i8> @llvm.riscv.vlse.mask.nxv2i8(1252 <vscale x 2 x i8> %0,1253 ptr %1,1254 iXLen %2,1255 <vscale x 2 x i1> %3,1256 iXLen %4, iXLen 1)1257 1258 ret <vscale x 2 x i8> %a1259}1260 1261define <vscale x 4 x i8> @intrinsic_vlse_v_nxv4i8_nxv4i8(ptr %0, iXLen %1, iXLen %2) nounwind {1262; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8:1263; CHECK: # %bb.0: # %entry1264; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma1265; CHECK-NEXT: vlse8.v v8, (a0), a11266; CHECK-NEXT: ret1267entry:1268 %a = call <vscale x 4 x i8> @llvm.riscv.vlse.nxv4i8(1269 <vscale x 4 x i8> poison,1270 ptr %0,1271 iXLen %1,1272 iXLen %2)1273 1274 ret <vscale x 4 x i8> %a1275}1276 1277define <vscale x 4 x i8> @intrinsic_vlse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1278; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8:1279; CHECK: # %bb.0: # %entry1280; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu1281; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1282; CHECK-NEXT: ret1283entry:1284 %a = call <vscale x 4 x i8> @llvm.riscv.vlse.mask.nxv4i8(1285 <vscale x 4 x i8> %0,1286 ptr %1,1287 iXLen %2,1288 <vscale x 4 x i1> %3,1289 iXLen %4, iXLen 1)1290 1291 ret <vscale x 4 x i8> %a1292}1293 1294define <vscale x 8 x i8> @intrinsic_vlse_v_nxv8i8_nxv8i8(ptr %0, iXLen %1, iXLen %2) nounwind {1295; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma1298; CHECK-NEXT: vlse8.v v8, (a0), a11299; CHECK-NEXT: ret1300entry:1301 %a = call <vscale x 8 x i8> @llvm.riscv.vlse.nxv8i8(1302 <vscale x 8 x i8> poison,1303 ptr %0,1304 iXLen %1,1305 iXLen %2)1306 1307 ret <vscale x 8 x i8> %a1308}1309 1310define <vscale x 8 x i8> @intrinsic_vlse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1311; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8:1312; CHECK: # %bb.0: # %entry1313; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu1314; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1315; CHECK-NEXT: ret1316entry:1317 %a = call <vscale x 8 x i8> @llvm.riscv.vlse.mask.nxv8i8(1318 <vscale x 8 x i8> %0,1319 ptr %1,1320 iXLen %2,1321 <vscale x 8 x i1> %3,1322 iXLen %4, iXLen 1)1323 1324 ret <vscale x 8 x i8> %a1325}1326 1327define <vscale x 16 x i8> @intrinsic_vlse_v_nxv16i8_nxv16i8(ptr %0, iXLen %1, iXLen %2) nounwind {1328; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma1331; CHECK-NEXT: vlse8.v v8, (a0), a11332; CHECK-NEXT: ret1333entry:1334 %a = call <vscale x 16 x i8> @llvm.riscv.vlse.nxv16i8(1335 <vscale x 16 x i8> poison,1336 ptr %0,1337 iXLen %1,1338 iXLen %2)1339 1340 ret <vscale x 16 x i8> %a1341}1342 1343define <vscale x 16 x i8> @intrinsic_vlse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1344; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8:1345; CHECK: # %bb.0: # %entry1346; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu1347; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1348; CHECK-NEXT: ret1349entry:1350 %a = call <vscale x 16 x i8> @llvm.riscv.vlse.mask.nxv16i8(1351 <vscale x 16 x i8> %0,1352 ptr %1,1353 iXLen %2,1354 <vscale x 16 x i1> %3,1355 iXLen %4, iXLen 1)1356 1357 ret <vscale x 16 x i8> %a1358}1359 1360define <vscale x 32 x i8> @intrinsic_vlse_v_nxv32i8_nxv32i8(ptr %0, iXLen %1, iXLen %2) nounwind {1361; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8:1362; CHECK: # %bb.0: # %entry1363; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma1364; CHECK-NEXT: vlse8.v v8, (a0), a11365; CHECK-NEXT: ret1366entry:1367 %a = call <vscale x 32 x i8> @llvm.riscv.vlse.nxv32i8(1368 <vscale x 32 x i8> poison,1369 ptr %0,1370 iXLen %1,1371 iXLen %2)1372 1373 ret <vscale x 32 x i8> %a1374}1375 1376define <vscale x 32 x i8> @intrinsic_vlse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1377; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8:1378; CHECK: # %bb.0: # %entry1379; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu1380; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1381; CHECK-NEXT: ret1382entry:1383 %a = call <vscale x 32 x i8> @llvm.riscv.vlse.mask.nxv32i8(1384 <vscale x 32 x i8> %0,1385 ptr %1,1386 iXLen %2,1387 <vscale x 32 x i1> %3,1388 iXLen %4, iXLen 1)1389 1390 ret <vscale x 32 x i8> %a1391}1392 1393define <vscale x 64 x i8> @intrinsic_vlse_v_nxv64i8_nxv64i8(ptr %0, iXLen %1, iXLen %2) nounwind {1394; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8:1395; CHECK: # %bb.0: # %entry1396; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma1397; CHECK-NEXT: vlse8.v v8, (a0), a11398; CHECK-NEXT: ret1399entry:1400 %a = call <vscale x 64 x i8> @llvm.riscv.vlse.nxv64i8(1401 <vscale x 64 x i8> poison,1402 ptr %0,1403 iXLen %1,1404 iXLen %2)1405 1406 ret <vscale x 64 x i8> %a1407}1408 1409define <vscale x 64 x i8> @intrinsic_vlse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {1410; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8:1411; CHECK: # %bb.0: # %entry1412; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu1413; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t1414; CHECK-NEXT: ret1415entry:1416 %a = call <vscale x 64 x i8> @llvm.riscv.vlse.mask.nxv64i8(1417 <vscale x 64 x i8> %0,1418 ptr %1,1419 iXLen %2,1420 <vscale x 64 x i1> %3,1421 iXLen %4, iXLen 1)1422 1423 ret <vscale x 64 x i8> %a1424}1425