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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+zve64x \3; RUN: -verify-machineinstrs < %s | FileCheck %s4 5define void @test_vlseg2ff_dead_value(ptr %base, i32 %vl, ptr %outvl) {6; CHECK-LABEL: test_vlseg2ff_dead_value:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma9; CHECK-NEXT: vlseg2e16ff.v v8, (a0)10; CHECK-NEXT: csrr a0, vl11; CHECK-NEXT: sw a0, 0(a2)12; CHECK-NEXT: ret13entry:14 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i32 %vl, i32 4)15 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} %0, 116 store i32 %1, ptr %outvl17 ret void18}19 20define void @test_vlseg2ff_mask_dead_value(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i32 %vl, <vscale x 16 x i1> %mask, ptr %outvl) {21; CHECK-LABEL: test_vlseg2ff_mask_dead_value:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu24; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t25; CHECK-NEXT: csrr a0, vl26; CHECK-NEXT: sw a0, 0(a2)27; CHECK-NEXT: ret28entry:29 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1, i32 4)30 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} %0, 131 store i32 %1, ptr %outvl32 ret void33}34 35define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(ptr %base, i32 %vl) {36; CHECK-LABEL: test_vlseg2ff_dead_vl:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma39; CHECK-NEXT: vlseg2e16ff.v v4, (a0)40; CHECK-NEXT: ret41entry:42 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i32 %vl, i32 4)43 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} %0, 044 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 1)45 ret <vscale x 16 x i16> %246}47 48define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i32 %vl, <vscale x 16 x i1> %mask) {49; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:50; CHECK: # %bb.0: # %entry51; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu52; CHECK-NEXT: vmv4r.v v4, v853; CHECK-NEXT: vmv4r.v v8, v1254; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t55; CHECK-NEXT: ret56entry:57 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1, i32 4)58 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} %0, 059 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 1)60 ret <vscale x 16 x i16> %261}62 63define void @test_vlseg2ff_dead_all(ptr %base, i32 %vl) {64; CHECK-LABEL: test_vlseg2ff_dead_all:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: ret67entry:68 tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i32 %vl, i32 4)69 ret void70}71 72define void @test_vlseg2ff_mask_dead_all(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i32 %vl, <vscale x 16 x i1> %mask) {73; CHECK-LABEL: test_vlseg2ff_mask_dead_all:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: ret76entry:77 tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i32} @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl, i32 1, i32 4)78 ret void79}80