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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs \3; RUN: < %s | FileCheck %s4 5; The intrinsics are not supported with RV32.6 7define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {8; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vluxei64.v v9, (a0), v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64(16 <vscale x 1 x i8> poison,17 ptr %0,18 <vscale x 1 x i64> %1,19 i64 %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {25; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i64:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu28; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64(32 <vscale x 1 x i8> %0,33 ptr %1,34 <vscale x 1 x i64> %2,35 <vscale x 1 x i1> %3,36 i64 %4, i64 1)37 38 ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {42; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i64:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma45; CHECK-NEXT: vluxei64.v v10, (a0), v846; CHECK-NEXT: vmv1r.v v8, v1047; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64(50 <vscale x 2 x i8> poison,51 ptr %0,52 <vscale x 2 x i64> %1,53 i64 %2)54 55 ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {59; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i64:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu62; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64(66 <vscale x 2 x i8> %0,67 ptr %1,68 <vscale x 2 x i64> %2,69 <vscale x 2 x i1> %3,70 i64 %4, i64 1)71 72 ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {76; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i64:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma79; CHECK-NEXT: vluxei64.v v12, (a0), v880; CHECK-NEXT: vmv1r.v v8, v1281; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64(84 <vscale x 4 x i8> poison,85 ptr %0,86 <vscale x 4 x i64> %1,87 i64 %2)88 89 ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {93; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i64:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu96; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64(100 <vscale x 4 x i8> %0,101 ptr %1,102 <vscale x 4 x i64> %2,103 <vscale x 4 x i1> %3,104 i64 %4, i64 1)105 106 ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {110; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i64:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma113; CHECK-NEXT: vluxei64.v v16, (a0), v8114; CHECK-NEXT: vmv.v.v v8, v16115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64(118 <vscale x 8 x i8> poison,119 ptr %0,120 <vscale x 8 x i64> %1,121 i64 %2)122 123 ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {127; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i64:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu130; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64(134 <vscale x 8 x i8> %0,135 ptr %1,136 <vscale x 8 x i64> %2,137 <vscale x 8 x i1> %3,138 i64 %4, i64 1)139 140 ret <vscale x 8 x i8> %a141}142 143define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {144; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i64:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma147; CHECK-NEXT: vluxei64.v v9, (a0), v8148; CHECK-NEXT: vmv1r.v v8, v9149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64(152 <vscale x 1 x i16> poison,153 ptr %0,154 <vscale x 1 x i64> %1,155 i64 %2)156 157 ret <vscale x 1 x i16> %a158}159 160define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {161; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i64:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu164; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64(168 <vscale x 1 x i16> %0,169 ptr %1,170 <vscale x 1 x i64> %2,171 <vscale x 1 x i1> %3,172 i64 %4, i64 1)173 174 ret <vscale x 1 x i16> %a175}176 177define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {178; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i64:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma181; CHECK-NEXT: vluxei64.v v10, (a0), v8182; CHECK-NEXT: vmv1r.v v8, v10183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64(186 <vscale x 2 x i16> poison,187 ptr %0,188 <vscale x 2 x i64> %1,189 i64 %2)190 191 ret <vscale x 2 x i16> %a192}193 194define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {195; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i64:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu198; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64(202 <vscale x 2 x i16> %0,203 ptr %1,204 <vscale x 2 x i64> %2,205 <vscale x 2 x i1> %3,206 i64 %4, i64 1)207 208 ret <vscale x 2 x i16> %a209}210 211define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {212; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i64:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma215; CHECK-NEXT: vluxei64.v v12, (a0), v8216; CHECK-NEXT: vmv.v.v v8, v12217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64(220 <vscale x 4 x i16> poison,221 ptr %0,222 <vscale x 4 x i64> %1,223 i64 %2)224 225 ret <vscale x 4 x i16> %a226}227 228define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {229; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i64:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu232; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64(236 <vscale x 4 x i16> %0,237 ptr %1,238 <vscale x 4 x i64> %2,239 <vscale x 4 x i1> %3,240 i64 %4, i64 1)241 242 ret <vscale x 4 x i16> %a243}244 245define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {246; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i64:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma249; CHECK-NEXT: vluxei64.v v16, (a0), v8250; CHECK-NEXT: vmv.v.v v8, v16251; CHECK-NEXT: ret252entry:253 %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64(254 <vscale x 8 x i16> poison,255 ptr %0,256 <vscale x 8 x i64> %1,257 i64 %2)258 259 ret <vscale x 8 x i16> %a260}261 262define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {263; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i64:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu266; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64(270 <vscale x 8 x i16> %0,271 ptr %1,272 <vscale x 8 x i64> %2,273 <vscale x 8 x i1> %3,274 i64 %4, i64 1)275 276 ret <vscale x 8 x i16> %a277}278 279define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {280; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i64:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma283; CHECK-NEXT: vluxei64.v v9, (a0), v8284; CHECK-NEXT: vmv1r.v v8, v9285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64(288 <vscale x 1 x i32> poison,289 ptr %0,290 <vscale x 1 x i64> %1,291 i64 %2)292 293 ret <vscale x 1 x i32> %a294}295 296define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {297; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i64:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu300; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64(304 <vscale x 1 x i32> %0,305 ptr %1,306 <vscale x 1 x i64> %2,307 <vscale x 1 x i1> %3,308 i64 %4, i64 1)309 310 ret <vscale x 1 x i32> %a311}312 313define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {314; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i64:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma317; CHECK-NEXT: vluxei64.v v10, (a0), v8318; CHECK-NEXT: vmv.v.v v8, v10319; CHECK-NEXT: ret320entry:321 %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64(322 <vscale x 2 x i32> poison,323 ptr %0,324 <vscale x 2 x i64> %1,325 i64 %2)326 327 ret <vscale x 2 x i32> %a328}329 330define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {331; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i64:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu334; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64(338 <vscale x 2 x i32> %0,339 ptr %1,340 <vscale x 2 x i64> %2,341 <vscale x 2 x i1> %3,342 i64 %4, i64 1)343 344 ret <vscale x 2 x i32> %a345}346 347define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {348; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i64:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma351; CHECK-NEXT: vluxei64.v v12, (a0), v8352; CHECK-NEXT: vmv.v.v v8, v12353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64(356 <vscale x 4 x i32> poison,357 ptr %0,358 <vscale x 4 x i64> %1,359 i64 %2)360 361 ret <vscale x 4 x i32> %a362}363 364define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {365; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i64:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu368; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64(372 <vscale x 4 x i32> %0,373 ptr %1,374 <vscale x 4 x i64> %2,375 <vscale x 4 x i1> %3,376 i64 %4, i64 1)377 378 ret <vscale x 4 x i32> %a379}380 381define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {382; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i64:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma385; CHECK-NEXT: vluxei64.v v16, (a0), v8386; CHECK-NEXT: vmv.v.v v8, v16387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64(390 <vscale x 8 x i32> poison,391 ptr %0,392 <vscale x 8 x i64> %1,393 i64 %2)394 395 ret <vscale x 8 x i32> %a396}397 398define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {399; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i64:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu402; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64(406 <vscale x 8 x i32> %0,407 ptr %1,408 <vscale x 8 x i64> %2,409 <vscale x 8 x i1> %3,410 i64 %4, i64 1)411 412 ret <vscale x 8 x i32> %a413}414 415define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {416; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i64:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma419; CHECK-NEXT: vluxei64.v v8, (a0), v8420; CHECK-NEXT: ret421entry:422 %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64(423 <vscale x 1 x i64> poison,424 ptr %0,425 <vscale x 1 x i64> %1,426 i64 %2)427 428 ret <vscale x 1 x i64> %a429}430 431define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {432; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i64:433; CHECK: # %bb.0: # %entry434; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu435; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t436; CHECK-NEXT: ret437entry:438 %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64(439 <vscale x 1 x i64> %0,440 ptr %1,441 <vscale x 1 x i64> %2,442 <vscale x 1 x i1> %3,443 i64 %4, i64 1)444 445 ret <vscale x 1 x i64> %a446}447 448define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {449; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i64:450; CHECK: # %bb.0: # %entry451; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma452; CHECK-NEXT: vluxei64.v v8, (a0), v8453; CHECK-NEXT: ret454entry:455 %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64(456 <vscale x 2 x i64> poison,457 ptr %0,458 <vscale x 2 x i64> %1,459 i64 %2)460 461 ret <vscale x 2 x i64> %a462}463 464define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {465; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i64:466; CHECK: # %bb.0: # %entry467; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu468; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t469; CHECK-NEXT: ret470entry:471 %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64(472 <vscale x 2 x i64> %0,473 ptr %1,474 <vscale x 2 x i64> %2,475 <vscale x 2 x i1> %3,476 i64 %4, i64 1)477 478 ret <vscale x 2 x i64> %a479}480 481define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {482; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i64:483; CHECK: # %bb.0: # %entry484; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma485; CHECK-NEXT: vluxei64.v v8, (a0), v8486; CHECK-NEXT: ret487entry:488 %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64(489 <vscale x 4 x i64> poison,490 ptr %0,491 <vscale x 4 x i64> %1,492 i64 %2)493 494 ret <vscale x 4 x i64> %a495}496 497define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {498; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i64:499; CHECK: # %bb.0: # %entry500; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu501; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t502; CHECK-NEXT: ret503entry:504 %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64(505 <vscale x 4 x i64> %0,506 ptr %1,507 <vscale x 4 x i64> %2,508 <vscale x 4 x i1> %3,509 i64 %4, i64 1)510 511 ret <vscale x 4 x i64> %a512}513 514define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {515; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i64:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma518; CHECK-NEXT: vluxei64.v v8, (a0), v8519; CHECK-NEXT: ret520entry:521 %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64(522 <vscale x 8 x i64> poison,523 ptr %0,524 <vscale x 8 x i64> %1,525 i64 %2)526 527 ret <vscale x 8 x i64> %a528}529 530define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {531; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i64:532; CHECK: # %bb.0: # %entry533; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu534; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t535; CHECK-NEXT: ret536entry:537 %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64(538 <vscale x 8 x i64> %0,539 ptr %1,540 <vscale x 8 x i64> %2,541 <vscale x 8 x i1> %3,542 i64 %4, i64 1)543 544 ret <vscale x 8 x i64> %a545}546 547define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {548; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i64:549; CHECK: # %bb.0: # %entry550; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma551; CHECK-NEXT: vluxei64.v v9, (a0), v8552; CHECK-NEXT: vmv1r.v v8, v9553; CHECK-NEXT: ret554entry:555 %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64(556 <vscale x 1 x half> poison,557 ptr %0,558 <vscale x 1 x i64> %1,559 i64 %2)560 561 ret <vscale x 1 x half> %a562}563 564define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {565; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i64:566; CHECK: # %bb.0: # %entry567; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu568; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t569; CHECK-NEXT: ret570entry:571 %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64(572 <vscale x 1 x half> %0,573 ptr %1,574 <vscale x 1 x i64> %2,575 <vscale x 1 x i1> %3,576 i64 %4, i64 1)577 578 ret <vscale x 1 x half> %a579}580 581define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {582; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i64:583; CHECK: # %bb.0: # %entry584; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma585; CHECK-NEXT: vluxei64.v v10, (a0), v8586; CHECK-NEXT: vmv1r.v v8, v10587; CHECK-NEXT: ret588entry:589 %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64(590 <vscale x 2 x half> poison,591 ptr %0,592 <vscale x 2 x i64> %1,593 i64 %2)594 595 ret <vscale x 2 x half> %a596}597 598define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {599; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i64:600; CHECK: # %bb.0: # %entry601; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu602; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t603; CHECK-NEXT: ret604entry:605 %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64(606 <vscale x 2 x half> %0,607 ptr %1,608 <vscale x 2 x i64> %2,609 <vscale x 2 x i1> %3,610 i64 %4, i64 1)611 612 ret <vscale x 2 x half> %a613}614 615define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {616; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i64:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma619; CHECK-NEXT: vluxei64.v v12, (a0), v8620; CHECK-NEXT: vmv.v.v v8, v12621; CHECK-NEXT: ret622entry:623 %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64(624 <vscale x 4 x half> poison,625 ptr %0,626 <vscale x 4 x i64> %1,627 i64 %2)628 629 ret <vscale x 4 x half> %a630}631 632define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {633; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i64:634; CHECK: # %bb.0: # %entry635; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu636; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t637; CHECK-NEXT: ret638entry:639 %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64(640 <vscale x 4 x half> %0,641 ptr %1,642 <vscale x 4 x i64> %2,643 <vscale x 4 x i1> %3,644 i64 %4, i64 1)645 646 ret <vscale x 4 x half> %a647}648 649define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {650; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i64:651; CHECK: # %bb.0: # %entry652; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma653; CHECK-NEXT: vluxei64.v v16, (a0), v8654; CHECK-NEXT: vmv.v.v v8, v16655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64(658 <vscale x 8 x half> poison,659 ptr %0,660 <vscale x 8 x i64> %1,661 i64 %2)662 663 ret <vscale x 8 x half> %a664}665 666define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {667; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i64:668; CHECK: # %bb.0: # %entry669; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu670; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t671; CHECK-NEXT: ret672entry:673 %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64(674 <vscale x 8 x half> %0,675 ptr %1,676 <vscale x 8 x i64> %2,677 <vscale x 8 x i1> %3,678 i64 %4, i64 1)679 680 ret <vscale x 8 x half> %a681}682 683define <vscale x 1 x bfloat> @intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {684; CHECK-LABEL: intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i64:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma687; CHECK-NEXT: vluxei64.v v9, (a0), v8688; CHECK-NEXT: vmv1r.v v8, v9689; CHECK-NEXT: ret690entry:691 %a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.nxv1i64(692 <vscale x 1 x bfloat> poison,693 ptr %0,694 <vscale x 1 x i64> %1,695 i64 %2)696 697 ret <vscale x 1 x bfloat> %a698}699 700define <vscale x 1 x bfloat> @intrinsic_vluxei_mask_v_nxv1bf16_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {701; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1bf16_nxv1bf16_nxv1i64:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu704; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t705; CHECK-NEXT: ret706entry:707 %a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i64(708 <vscale x 1 x bfloat> %0,709 ptr %1,710 <vscale x 1 x i64> %2,711 <vscale x 1 x i1> %3,712 i64 %4, i64 1)713 714 ret <vscale x 1 x bfloat> %a715}716 717define <vscale x 2 x bfloat> @intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {718; CHECK-LABEL: intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i64:719; CHECK: # %bb.0: # %entry720; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma721; CHECK-NEXT: vluxei64.v v10, (a0), v8722; CHECK-NEXT: vmv1r.v v8, v10723; CHECK-NEXT: ret724entry:725 %a = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.nxv2i64(726 <vscale x 2 x bfloat> poison,727 ptr %0,728 <vscale x 2 x i64> %1,729 i64 %2)730 731 ret <vscale x 2 x bfloat> %a732}733 734define <vscale x 2 x bfloat> @intrinsic_vluxei_mask_v_nxv2bf16_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {735; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2bf16_nxv2bf16_nxv2i64:736; CHECK: # %bb.0: # %entry737; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu738; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t739; CHECK-NEXT: ret740entry:741 %a = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i64(742 <vscale x 2 x bfloat> %0,743 ptr %1,744 <vscale x 2 x i64> %2,745 <vscale x 2 x i1> %3,746 i64 %4, i64 1)747 748 ret <vscale x 2 x bfloat> %a749}750 751define <vscale x 4 x bfloat> @intrinsic_vluxei_v_nxv4bf16_nxv4bf16_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {752; CHECK-LABEL: intrinsic_vluxei_v_nxv4bf16_nxv4bf16_nxv4i64:753; CHECK: # %bb.0: # %entry754; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma755; CHECK-NEXT: vluxei64.v v12, (a0), v8756; CHECK-NEXT: vmv.v.v v8, v12757; CHECK-NEXT: ret758entry:759 %a = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.nxv4i64(760 <vscale x 4 x bfloat> poison,761 ptr %0,762 <vscale x 4 x i64> %1,763 i64 %2)764 765 ret <vscale x 4 x bfloat> %a766}767 768define <vscale x 4 x bfloat> @intrinsic_vluxei_mask_v_nxv4bf16_nxv4bf16_nxv4i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {769; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4bf16_nxv4bf16_nxv4i64:770; CHECK: # %bb.0: # %entry771; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu772; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t773; CHECK-NEXT: ret774entry:775 %a = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i64(776 <vscale x 4 x bfloat> %0,777 ptr %1,778 <vscale x 4 x i64> %2,779 <vscale x 4 x i1> %3,780 i64 %4, i64 1)781 782 ret <vscale x 4 x bfloat> %a783}784 785define <vscale x 8 x bfloat> @intrinsic_vluxei_v_nxv8bf16_nxv8bf16_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {786; CHECK-LABEL: intrinsic_vluxei_v_nxv8bf16_nxv8bf16_nxv8i64:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma789; CHECK-NEXT: vluxei64.v v16, (a0), v8790; CHECK-NEXT: vmv.v.v v8, v16791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.nxv8i64(794 <vscale x 8 x bfloat> poison,795 ptr %0,796 <vscale x 8 x i64> %1,797 i64 %2)798 799 ret <vscale x 8 x bfloat> %a800}801 802define <vscale x 8 x bfloat> @intrinsic_vluxei_mask_v_nxv8bf16_nxv8bf16_nxv8i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {803; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8bf16_nxv8bf16_nxv8i64:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu806; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t807; CHECK-NEXT: ret808entry:809 %a = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i64(810 <vscale x 8 x bfloat> %0,811 ptr %1,812 <vscale x 8 x i64> %2,813 <vscale x 8 x i1> %3,814 i64 %4, i64 1)815 816 ret <vscale x 8 x bfloat> %a817}818 819define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {820; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i64:821; CHECK: # %bb.0: # %entry822; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma823; CHECK-NEXT: vluxei64.v v9, (a0), v8824; CHECK-NEXT: vmv1r.v v8, v9825; CHECK-NEXT: ret826entry:827 %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64(828 <vscale x 1 x float> poison,829 ptr %0,830 <vscale x 1 x i64> %1,831 i64 %2)832 833 ret <vscale x 1 x float> %a834}835 836define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {837; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i64:838; CHECK: # %bb.0: # %entry839; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu840; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t841; CHECK-NEXT: ret842entry:843 %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64(844 <vscale x 1 x float> %0,845 ptr %1,846 <vscale x 1 x i64> %2,847 <vscale x 1 x i1> %3,848 i64 %4, i64 1)849 850 ret <vscale x 1 x float> %a851}852 853define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {854; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i64:855; CHECK: # %bb.0: # %entry856; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma857; CHECK-NEXT: vluxei64.v v10, (a0), v8858; CHECK-NEXT: vmv.v.v v8, v10859; CHECK-NEXT: ret860entry:861 %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64(862 <vscale x 2 x float> poison,863 ptr %0,864 <vscale x 2 x i64> %1,865 i64 %2)866 867 ret <vscale x 2 x float> %a868}869 870define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {871; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i64:872; CHECK: # %bb.0: # %entry873; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu874; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t875; CHECK-NEXT: ret876entry:877 %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64(878 <vscale x 2 x float> %0,879 ptr %1,880 <vscale x 2 x i64> %2,881 <vscale x 2 x i1> %3,882 i64 %4, i64 1)883 884 ret <vscale x 2 x float> %a885}886 887define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {888; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i64:889; CHECK: # %bb.0: # %entry890; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma891; CHECK-NEXT: vluxei64.v v12, (a0), v8892; CHECK-NEXT: vmv.v.v v8, v12893; CHECK-NEXT: ret894entry:895 %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64(896 <vscale x 4 x float> poison,897 ptr %0,898 <vscale x 4 x i64> %1,899 i64 %2)900 901 ret <vscale x 4 x float> %a902}903 904define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {905; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i64:906; CHECK: # %bb.0: # %entry907; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu908; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t909; CHECK-NEXT: ret910entry:911 %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64(912 <vscale x 4 x float> %0,913 ptr %1,914 <vscale x 4 x i64> %2,915 <vscale x 4 x i1> %3,916 i64 %4, i64 1)917 918 ret <vscale x 4 x float> %a919}920 921define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {922; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i64:923; CHECK: # %bb.0: # %entry924; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma925; CHECK-NEXT: vluxei64.v v16, (a0), v8926; CHECK-NEXT: vmv.v.v v8, v16927; CHECK-NEXT: ret928entry:929 %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64(930 <vscale x 8 x float> poison,931 ptr %0,932 <vscale x 8 x i64> %1,933 i64 %2)934 935 ret <vscale x 8 x float> %a936}937 938define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {939; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i64:940; CHECK: # %bb.0: # %entry941; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu942; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t943; CHECK-NEXT: ret944entry:945 %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64(946 <vscale x 8 x float> %0,947 ptr %1,948 <vscale x 8 x i64> %2,949 <vscale x 8 x i1> %3,950 i64 %4, i64 1)951 952 ret <vscale x 8 x float> %a953}954 955define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64(ptr %0, <vscale x 1 x i64> %1, i64 %2) nounwind {956; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i64:957; CHECK: # %bb.0: # %entry958; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma959; CHECK-NEXT: vluxei64.v v8, (a0), v8960; CHECK-NEXT: ret961entry:962 %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64(963 <vscale x 1 x double> poison,964 ptr %0,965 <vscale x 1 x i64> %1,966 i64 %2)967 968 ret <vscale x 1 x double> %a969}970 971define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {972; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i64:973; CHECK: # %bb.0: # %entry974; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu975; CHECK-NEXT: vluxei64.v v8, (a0), v9, v0.t976; CHECK-NEXT: ret977entry:978 %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64(979 <vscale x 1 x double> %0,980 ptr %1,981 <vscale x 1 x i64> %2,982 <vscale x 1 x i1> %3,983 i64 %4, i64 1)984 985 ret <vscale x 1 x double> %a986}987 988define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64(ptr %0, <vscale x 2 x i64> %1, i64 %2) nounwind {989; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i64:990; CHECK: # %bb.0: # %entry991; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma992; CHECK-NEXT: vluxei64.v v8, (a0), v8993; CHECK-NEXT: ret994entry:995 %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64(996 <vscale x 2 x double> poison,997 ptr %0,998 <vscale x 2 x i64> %1,999 i64 %2)1000 1001 ret <vscale x 2 x double> %a1002}1003 1004define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {1005; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i64:1006; CHECK: # %bb.0: # %entry1007; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu1008; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t1009; CHECK-NEXT: ret1010entry:1011 %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64(1012 <vscale x 2 x double> %0,1013 ptr %1,1014 <vscale x 2 x i64> %2,1015 <vscale x 2 x i1> %3,1016 i64 %4, i64 1)1017 1018 ret <vscale x 2 x double> %a1019}1020 1021define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64(ptr %0, <vscale x 4 x i64> %1, i64 %2) nounwind {1022; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i64:1023; CHECK: # %bb.0: # %entry1024; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1025; CHECK-NEXT: vluxei64.v v8, (a0), v81026; CHECK-NEXT: ret1027entry:1028 %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64(1029 <vscale x 4 x double> poison,1030 ptr %0,1031 <vscale x 4 x i64> %1,1032 i64 %2)1033 1034 ret <vscale x 4 x double> %a1035}1036 1037define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {1038; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i64:1039; CHECK: # %bb.0: # %entry1040; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu1041; CHECK-NEXT: vluxei64.v v8, (a0), v12, v0.t1042; CHECK-NEXT: ret1043entry:1044 %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64(1045 <vscale x 4 x double> %0,1046 ptr %1,1047 <vscale x 4 x i64> %2,1048 <vscale x 4 x i1> %3,1049 i64 %4, i64 1)1050 1051 ret <vscale x 4 x double> %a1052}1053 1054define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64(ptr %0, <vscale x 8 x i64> %1, i64 %2) nounwind {1055; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i64:1056; CHECK: # %bb.0: # %entry1057; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1058; CHECK-NEXT: vluxei64.v v8, (a0), v81059; CHECK-NEXT: ret1060entry:1061 %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64(1062 <vscale x 8 x double> poison,1063 ptr %0,1064 <vscale x 8 x i64> %1,1065 i64 %2)1066 1067 ret <vscale x 8 x double> %a1068}1069 1070define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {1071; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i64:1072; CHECK: # %bb.0: # %entry1073; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu1074; CHECK-NEXT: vluxei64.v v8, (a0), v16, v0.t1075; CHECK-NEXT: ret1076entry:1077 %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64(1078 <vscale x 8 x double> %0,1079 ptr %1,1080 <vscale x 8 x i64> %2,1081 <vscale x 8 x i1> %3,1082 i64 %4, i64 1)1083 1084 ret <vscale x 8 x double> %a1085}1086