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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT:    vluxei32.v v9, (a0), v812; CHECK-NEXT:    vmv1r.v v8, v913; CHECK-NEXT:    ret14entry:15  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(16    <vscale x 1 x i8> poison,17    ptr %0,18    <vscale x 1 x i32> %1,19    iXLen %2)20 21  ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i32:26; CHECK:       # %bb.0: # %entry27; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu28; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t29; CHECK-NEXT:    ret30entry:31  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(32    <vscale x 1 x i8> %0,33    ptr %1,34    <vscale x 1 x i32> %2,35    <vscale x 1 x i1> %3,36    iXLen %4, iXLen 1)37 38  ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:43; CHECK:       # %bb.0: # %entry44; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma45; CHECK-NEXT:    vluxei32.v v9, (a0), v846; CHECK-NEXT:    vmv1r.v v8, v947; CHECK-NEXT:    ret48entry:49  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(50    <vscale x 2 x i8> poison,51    ptr %0,52    <vscale x 2 x i32> %1,53    iXLen %2)54 55  ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i32:60; CHECK:       # %bb.0: # %entry61; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu62; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t63; CHECK-NEXT:    ret64entry:65  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(66    <vscale x 2 x i8> %0,67    ptr %1,68    <vscale x 2 x i32> %2,69    <vscale x 2 x i1> %3,70    iXLen %4, iXLen 1)71 72  ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:77; CHECK:       # %bb.0: # %entry78; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma79; CHECK-NEXT:    vluxei32.v v10, (a0), v880; CHECK-NEXT:    vmv1r.v v8, v1081; CHECK-NEXT:    ret82entry:83  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(84    <vscale x 4 x i8> poison,85    ptr %0,86    <vscale x 4 x i32> %1,87    iXLen %2)88 89  ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i32:94; CHECK:       # %bb.0: # %entry95; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu96; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t97; CHECK-NEXT:    ret98entry:99  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(100    <vscale x 4 x i8> %0,101    ptr %1,102    <vscale x 4 x i32> %2,103    <vscale x 4 x i1> %3,104    iXLen %4, iXLen 1)105 106  ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:111; CHECK:       # %bb.0: # %entry112; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma113; CHECK-NEXT:    vluxei32.v v12, (a0), v8114; CHECK-NEXT:    vmv.v.v v8, v12115; CHECK-NEXT:    ret116entry:117  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(118    <vscale x 8 x i8> poison,119    ptr %0,120    <vscale x 8 x i32> %1,121    iXLen %2)122 123  ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i32:128; CHECK:       # %bb.0: # %entry129; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu130; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t131; CHECK-NEXT:    ret132entry:133  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(134    <vscale x 8 x i8> %0,135    ptr %1,136    <vscale x 8 x i32> %2,137    <vscale x 8 x i1> %3,138    iXLen %4, iXLen 1)139 140  ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:145; CHECK:       # %bb.0: # %entry146; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma147; CHECK-NEXT:    vluxei32.v v16, (a0), v8148; CHECK-NEXT:    vmv.v.v v8, v16149; CHECK-NEXT:    ret150entry:151  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(152    <vscale x 16 x i8> poison,153    ptr %0,154    <vscale x 16 x i32> %1,155    iXLen %2)156 157  ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i32:162; CHECK:       # %bb.0: # %entry163; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu164; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t165; CHECK-NEXT:    ret166entry:167  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(168    <vscale x 16 x i8> %0,169    ptr %1,170    <vscale x 16 x i32> %2,171    <vscale x 16 x i1> %3,172    iXLen %4, iXLen 1)173 174  ret <vscale x 16 x i8> %a175}176 177define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:179; CHECK:       # %bb.0: # %entry180; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma181; CHECK-NEXT:    vluxei32.v v9, (a0), v8182; CHECK-NEXT:    vmv1r.v v8, v9183; CHECK-NEXT:    ret184entry:185  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(186    <vscale x 1 x i16> poison,187    ptr %0,188    <vscale x 1 x i32> %1,189    iXLen %2)190 191  ret <vscale x 1 x i16> %a192}193 194define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i32:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu198; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t199; CHECK-NEXT:    ret200entry:201  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(202    <vscale x 1 x i16> %0,203    ptr %1,204    <vscale x 1 x i32> %2,205    <vscale x 1 x i1> %3,206    iXLen %4, iXLen 1)207 208  ret <vscale x 1 x i16> %a209}210 211define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:213; CHECK:       # %bb.0: # %entry214; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma215; CHECK-NEXT:    vluxei32.v v9, (a0), v8216; CHECK-NEXT:    vmv1r.v v8, v9217; CHECK-NEXT:    ret218entry:219  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(220    <vscale x 2 x i16> poison,221    ptr %0,222    <vscale x 2 x i32> %1,223    iXLen %2)224 225  ret <vscale x 2 x i16> %a226}227 228define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i32:230; CHECK:       # %bb.0: # %entry231; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu232; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t233; CHECK-NEXT:    ret234entry:235  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(236    <vscale x 2 x i16> %0,237    ptr %1,238    <vscale x 2 x i32> %2,239    <vscale x 2 x i1> %3,240    iXLen %4, iXLen 1)241 242  ret <vscale x 2 x i16> %a243}244 245define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:247; CHECK:       # %bb.0: # %entry248; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma249; CHECK-NEXT:    vluxei32.v v10, (a0), v8250; CHECK-NEXT:    vmv.v.v v8, v10251; CHECK-NEXT:    ret252entry:253  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(254    <vscale x 4 x i16> poison,255    ptr %0,256    <vscale x 4 x i32> %1,257    iXLen %2)258 259  ret <vscale x 4 x i16> %a260}261 262define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i32:264; CHECK:       # %bb.0: # %entry265; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu266; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t267; CHECK-NEXT:    ret268entry:269  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(270    <vscale x 4 x i16> %0,271    ptr %1,272    <vscale x 4 x i32> %2,273    <vscale x 4 x i1> %3,274    iXLen %4, iXLen 1)275 276  ret <vscale x 4 x i16> %a277}278 279define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:281; CHECK:       # %bb.0: # %entry282; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma283; CHECK-NEXT:    vluxei32.v v12, (a0), v8284; CHECK-NEXT:    vmv.v.v v8, v12285; CHECK-NEXT:    ret286entry:287  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(288    <vscale x 8 x i16> poison,289    ptr %0,290    <vscale x 8 x i32> %1,291    iXLen %2)292 293  ret <vscale x 8 x i16> %a294}295 296define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i32:298; CHECK:       # %bb.0: # %entry299; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu300; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t301; CHECK-NEXT:    ret302entry:303  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(304    <vscale x 8 x i16> %0,305    ptr %1,306    <vscale x 8 x i32> %2,307    <vscale x 8 x i1> %3,308    iXLen %4, iXLen 1)309 310  ret <vscale x 8 x i16> %a311}312 313define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:315; CHECK:       # %bb.0: # %entry316; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma317; CHECK-NEXT:    vluxei32.v v16, (a0), v8318; CHECK-NEXT:    vmv.v.v v8, v16319; CHECK-NEXT:    ret320entry:321  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(322    <vscale x 16 x i16> poison,323    ptr %0,324    <vscale x 16 x i32> %1,325    iXLen %2)326 327  ret <vscale x 16 x i16> %a328}329 330define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i32:332; CHECK:       # %bb.0: # %entry333; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu334; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t335; CHECK-NEXT:    ret336entry:337  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(338    <vscale x 16 x i16> %0,339    ptr %1,340    <vscale x 16 x i32> %2,341    <vscale x 16 x i1> %3,342    iXLen %4, iXLen 1)343 344  ret <vscale x 16 x i16> %a345}346 347define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32:349; CHECK:       # %bb.0: # %entry350; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma351; CHECK-NEXT:    vluxei32.v v8, (a0), v8352; CHECK-NEXT:    ret353entry:354  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(355    <vscale x 1 x i32> poison,356    ptr %0,357    <vscale x 1 x i32> %1,358    iXLen %2)359 360  ret <vscale x 1 x i32> %a361}362 363define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {364; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i32:365; CHECK:       # %bb.0: # %entry366; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu367; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t368; CHECK-NEXT:    ret369entry:370  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(371    <vscale x 1 x i32> %0,372    ptr %1,373    <vscale x 1 x i32> %2,374    <vscale x 1 x i1> %3,375    iXLen %4, iXLen 1)376 377  ret <vscale x 1 x i32> %a378}379 380define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {381; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32:382; CHECK:       # %bb.0: # %entry383; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma384; CHECK-NEXT:    vluxei32.v v8, (a0), v8385; CHECK-NEXT:    ret386entry:387  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(388    <vscale x 2 x i32> poison,389    ptr %0,390    <vscale x 2 x i32> %1,391    iXLen %2)392 393  ret <vscale x 2 x i32> %a394}395 396define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {397; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i32:398; CHECK:       # %bb.0: # %entry399; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu400; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t401; CHECK-NEXT:    ret402entry:403  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(404    <vscale x 2 x i32> %0,405    ptr %1,406    <vscale x 2 x i32> %2,407    <vscale x 2 x i1> %3,408    iXLen %4, iXLen 1)409 410  ret <vscale x 2 x i32> %a411}412 413define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {414; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32:415; CHECK:       # %bb.0: # %entry416; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma417; CHECK-NEXT:    vluxei32.v v8, (a0), v8418; CHECK-NEXT:    ret419entry:420  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(421    <vscale x 4 x i32> poison,422    ptr %0,423    <vscale x 4 x i32> %1,424    iXLen %2)425 426  ret <vscale x 4 x i32> %a427}428 429define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {430; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i32:431; CHECK:       # %bb.0: # %entry432; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu433; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t434; CHECK-NEXT:    ret435entry:436  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(437    <vscale x 4 x i32> %0,438    ptr %1,439    <vscale x 4 x i32> %2,440    <vscale x 4 x i1> %3,441    iXLen %4, iXLen 1)442 443  ret <vscale x 4 x i32> %a444}445 446define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {447; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32:448; CHECK:       # %bb.0: # %entry449; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma450; CHECK-NEXT:    vluxei32.v v8, (a0), v8451; CHECK-NEXT:    ret452entry:453  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(454    <vscale x 8 x i32> poison,455    ptr %0,456    <vscale x 8 x i32> %1,457    iXLen %2)458 459  ret <vscale x 8 x i32> %a460}461 462define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {463; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i32:464; CHECK:       # %bb.0: # %entry465; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu466; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t467; CHECK-NEXT:    ret468entry:469  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(470    <vscale x 8 x i32> %0,471    ptr %1,472    <vscale x 8 x i32> %2,473    <vscale x 8 x i1> %3,474    iXLen %4, iXLen 1)475 476  ret <vscale x 8 x i32> %a477}478 479define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {480; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32:481; CHECK:       # %bb.0: # %entry482; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma483; CHECK-NEXT:    vluxei32.v v8, (a0), v8484; CHECK-NEXT:    ret485entry:486  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(487    <vscale x 16 x i32> poison,488    ptr %0,489    <vscale x 16 x i32> %1,490    iXLen %2)491 492  ret <vscale x 16 x i32> %a493}494 495define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {496; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i32:497; CHECK:       # %bb.0: # %entry498; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu499; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t500; CHECK-NEXT:    ret501entry:502  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(503    <vscale x 16 x i32> %0,504    ptr %1,505    <vscale x 16 x i32> %2,506    <vscale x 16 x i1> %3,507    iXLen %4, iXLen 1)508 509  ret <vscale x 16 x i32> %a510}511 512define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {513; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:514; CHECK:       # %bb.0: # %entry515; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma516; CHECK-NEXT:    vluxei32.v v9, (a0), v8517; CHECK-NEXT:    vmv.v.v v8, v9518; CHECK-NEXT:    ret519entry:520  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(521    <vscale x 1 x i64> poison,522    ptr %0,523    <vscale x 1 x i32> %1,524    iXLen %2)525 526  ret <vscale x 1 x i64> %a527}528 529define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i32:531; CHECK:       # %bb.0: # %entry532; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu533; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t534; CHECK-NEXT:    ret535entry:536  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(537    <vscale x 1 x i64> %0,538    ptr %1,539    <vscale x 1 x i32> %2,540    <vscale x 1 x i1> %3,541    iXLen %4, iXLen 1)542 543  ret <vscale x 1 x i64> %a544}545 546define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {547; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:548; CHECK:       # %bb.0: # %entry549; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma550; CHECK-NEXT:    vmv1r.v v10, v8551; CHECK-NEXT:    vluxei32.v v8, (a0), v10552; CHECK-NEXT:    ret553entry:554  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(555    <vscale x 2 x i64> poison,556    ptr %0,557    <vscale x 2 x i32> %1,558    iXLen %2)559 560  ret <vscale x 2 x i64> %a561}562 563define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {564; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i32:565; CHECK:       # %bb.0: # %entry566; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu567; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t568; CHECK-NEXT:    ret569entry:570  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(571    <vscale x 2 x i64> %0,572    ptr %1,573    <vscale x 2 x i32> %2,574    <vscale x 2 x i1> %3,575    iXLen %4, iXLen 1)576 577  ret <vscale x 2 x i64> %a578}579 580define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {581; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:582; CHECK:       # %bb.0: # %entry583; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma584; CHECK-NEXT:    vmv2r.v v12, v8585; CHECK-NEXT:    vluxei32.v v8, (a0), v12586; CHECK-NEXT:    ret587entry:588  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(589    <vscale x 4 x i64> poison,590    ptr %0,591    <vscale x 4 x i32> %1,592    iXLen %2)593 594  ret <vscale x 4 x i64> %a595}596 597define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {598; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i32:599; CHECK:       # %bb.0: # %entry600; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu601; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t602; CHECK-NEXT:    ret603entry:604  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(605    <vscale x 4 x i64> %0,606    ptr %1,607    <vscale x 4 x i32> %2,608    <vscale x 4 x i1> %3,609    iXLen %4, iXLen 1)610 611  ret <vscale x 4 x i64> %a612}613 614define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {615; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32:616; CHECK:       # %bb.0: # %entry617; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma618; CHECK-NEXT:    vmv4r.v v16, v8619; CHECK-NEXT:    vluxei32.v v8, (a0), v16620; CHECK-NEXT:    ret621entry:622  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(623    <vscale x 8 x i64> poison,624    ptr %0,625    <vscale x 8 x i32> %1,626    iXLen %2)627 628  ret <vscale x 8 x i64> %a629}630 631define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {632; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i32:633; CHECK:       # %bb.0: # %entry634; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu635; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t636; CHECK-NEXT:    ret637entry:638  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(639    <vscale x 8 x i64> %0,640    ptr %1,641    <vscale x 8 x i32> %2,642    <vscale x 8 x i1> %3,643    iXLen %4, iXLen 1)644 645  ret <vscale x 8 x i64> %a646}647 648define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {649; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:650; CHECK:       # %bb.0: # %entry651; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma652; CHECK-NEXT:    vluxei32.v v9, (a0), v8653; CHECK-NEXT:    vmv1r.v v8, v9654; CHECK-NEXT:    ret655entry:656  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(657    <vscale x 1 x half> poison,658    ptr %0,659    <vscale x 1 x i32> %1,660    iXLen %2)661 662  ret <vscale x 1 x half> %a663}664 665define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {666; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i32:667; CHECK:       # %bb.0: # %entry668; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu669; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t670; CHECK-NEXT:    ret671entry:672  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(673    <vscale x 1 x half> %0,674    ptr %1,675    <vscale x 1 x i32> %2,676    <vscale x 1 x i1> %3,677    iXLen %4, iXLen 1)678 679  ret <vscale x 1 x half> %a680}681 682define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {683; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:684; CHECK:       # %bb.0: # %entry685; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma686; CHECK-NEXT:    vluxei32.v v9, (a0), v8687; CHECK-NEXT:    vmv1r.v v8, v9688; CHECK-NEXT:    ret689entry:690  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(691    <vscale x 2 x half> poison,692    ptr %0,693    <vscale x 2 x i32> %1,694    iXLen %2)695 696  ret <vscale x 2 x half> %a697}698 699define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {700; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i32:701; CHECK:       # %bb.0: # %entry702; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu703; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t704; CHECK-NEXT:    ret705entry:706  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(707    <vscale x 2 x half> %0,708    ptr %1,709    <vscale x 2 x i32> %2,710    <vscale x 2 x i1> %3,711    iXLen %4, iXLen 1)712 713  ret <vscale x 2 x half> %a714}715 716define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {717; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:718; CHECK:       # %bb.0: # %entry719; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma720; CHECK-NEXT:    vluxei32.v v10, (a0), v8721; CHECK-NEXT:    vmv.v.v v8, v10722; CHECK-NEXT:    ret723entry:724  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(725    <vscale x 4 x half> poison,726    ptr %0,727    <vscale x 4 x i32> %1,728    iXLen %2)729 730  ret <vscale x 4 x half> %a731}732 733define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {734; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i32:735; CHECK:       # %bb.0: # %entry736; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu737; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t738; CHECK-NEXT:    ret739entry:740  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(741    <vscale x 4 x half> %0,742    ptr %1,743    <vscale x 4 x i32> %2,744    <vscale x 4 x i1> %3,745    iXLen %4, iXLen 1)746 747  ret <vscale x 4 x half> %a748}749 750define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {751; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:752; CHECK:       # %bb.0: # %entry753; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma754; CHECK-NEXT:    vluxei32.v v12, (a0), v8755; CHECK-NEXT:    vmv.v.v v8, v12756; CHECK-NEXT:    ret757entry:758  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(759    <vscale x 8 x half> poison,760    ptr %0,761    <vscale x 8 x i32> %1,762    iXLen %2)763 764  ret <vscale x 8 x half> %a765}766 767define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {768; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i32:769; CHECK:       # %bb.0: # %entry770; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu771; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t772; CHECK-NEXT:    ret773entry:774  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(775    <vscale x 8 x half> %0,776    ptr %1,777    <vscale x 8 x i32> %2,778    <vscale x 8 x i1> %3,779    iXLen %4, iXLen 1)780 781  ret <vscale x 8 x half> %a782}783 784define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {785; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:786; CHECK:       # %bb.0: # %entry787; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma788; CHECK-NEXT:    vluxei32.v v16, (a0), v8789; CHECK-NEXT:    vmv.v.v v8, v16790; CHECK-NEXT:    ret791entry:792  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(793    <vscale x 16 x half> poison,794    ptr %0,795    <vscale x 16 x i32> %1,796    iXLen %2)797 798  ret <vscale x 16 x half> %a799}800 801define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {802; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i32:803; CHECK:       # %bb.0: # %entry804; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu805; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t806; CHECK-NEXT:    ret807entry:808  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(809    <vscale x 16 x half> %0,810    ptr %1,811    <vscale x 16 x i32> %2,812    <vscale x 16 x i1> %3,813    iXLen %4, iXLen 1)814 815  ret <vscale x 16 x half> %a816}817 818define <vscale x 1 x bfloat> @intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {819; CHECK-LABEL: intrinsic_vluxei_v_nxv1bf16_nxv1bf16_nxv1i32:820; CHECK:       # %bb.0: # %entry821; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma822; CHECK-NEXT:    vluxei32.v v9, (a0), v8823; CHECK-NEXT:    vmv1r.v v8, v9824; CHECK-NEXT:    ret825entry:826  %a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.nxv1bf16.nxv1i32(827    <vscale x 1 x bfloat> poison,828    ptr %0,829    <vscale x 1 x i32> %1,830    iXLen %2)831 832  ret <vscale x 1 x bfloat> %a833}834 835define <vscale x 1 x bfloat> @intrinsic_vluxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {836; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32:837; CHECK:       # %bb.0: # %entry838; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu839; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t840; CHECK-NEXT:    ret841entry:842  %a = call <vscale x 1 x bfloat> @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i32(843    <vscale x 1 x bfloat> %0,844    ptr %1,845    <vscale x 1 x i32> %2,846    <vscale x 1 x i1> %3,847    iXLen %4, iXLen 1)848 849  ret <vscale x 1 x bfloat> %a850}851 852define <vscale x 2 x bfloat> @intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {853; CHECK-LABEL: intrinsic_vluxei_v_nxv2bf16_nxv2bf16_nxv2i32:854; CHECK:       # %bb.0: # %entry855; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma856; CHECK-NEXT:    vluxei32.v v9, (a0), v8857; CHECK-NEXT:    vmv1r.v v8, v9858; CHECK-NEXT:    ret859entry:860  %a = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.nxv2bf16.nxv2i32(861    <vscale x 2 x bfloat> poison,862    ptr %0,863    <vscale x 2 x i32> %1,864    iXLen %2)865 866  ret <vscale x 2 x bfloat> %a867}868 869define <vscale x 2 x bfloat> @intrinsic_vluxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {870; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32:871; CHECK:       # %bb.0: # %entry872; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu873; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t874; CHECK-NEXT:    ret875entry:876  %a = call <vscale x 2 x bfloat> @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i32(877    <vscale x 2 x bfloat> %0,878    ptr %1,879    <vscale x 2 x i32> %2,880    <vscale x 2 x i1> %3,881    iXLen %4, iXLen 1)882 883  ret <vscale x 2 x bfloat> %a884}885 886define <vscale x 4 x bfloat> @intrinsic_vluxei_v_nxv4bf16_nxv4bf16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {887; CHECK-LABEL: intrinsic_vluxei_v_nxv4bf16_nxv4bf16_nxv4i32:888; CHECK:       # %bb.0: # %entry889; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma890; CHECK-NEXT:    vluxei32.v v10, (a0), v8891; CHECK-NEXT:    vmv.v.v v8, v10892; CHECK-NEXT:    ret893entry:894  %a = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.nxv4bf16.nxv4i32(895    <vscale x 4 x bfloat> poison,896    ptr %0,897    <vscale x 4 x i32> %1,898    iXLen %2)899 900  ret <vscale x 4 x bfloat> %a901}902 903define <vscale x 4 x bfloat> @intrinsic_vluxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {904; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32:905; CHECK:       # %bb.0: # %entry906; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu907; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t908; CHECK-NEXT:    ret909entry:910  %a = call <vscale x 4 x bfloat> @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i32(911    <vscale x 4 x bfloat> %0,912    ptr %1,913    <vscale x 4 x i32> %2,914    <vscale x 4 x i1> %3,915    iXLen %4, iXLen 1)916 917  ret <vscale x 4 x bfloat> %a918}919 920define <vscale x 8 x bfloat> @intrinsic_vluxei_v_nxv8bf16_nxv8bf16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {921; CHECK-LABEL: intrinsic_vluxei_v_nxv8bf16_nxv8bf16_nxv8i32:922; CHECK:       # %bb.0: # %entry923; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma924; CHECK-NEXT:    vluxei32.v v12, (a0), v8925; CHECK-NEXT:    vmv.v.v v8, v12926; CHECK-NEXT:    ret927entry:928  %a = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.nxv8bf16.nxv8i32(929    <vscale x 8 x bfloat> poison,930    ptr %0,931    <vscale x 8 x i32> %1,932    iXLen %2)933 934  ret <vscale x 8 x bfloat> %a935}936 937define <vscale x 8 x bfloat> @intrinsic_vluxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {938; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32:939; CHECK:       # %bb.0: # %entry940; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu941; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t942; CHECK-NEXT:    ret943entry:944  %a = call <vscale x 8 x bfloat> @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i32(945    <vscale x 8 x bfloat> %0,946    ptr %1,947    <vscale x 8 x i32> %2,948    <vscale x 8 x i1> %3,949    iXLen %4, iXLen 1)950 951  ret <vscale x 8 x bfloat> %a952}953 954define <vscale x 16 x bfloat> @intrinsic_vluxei_v_nxv16bf16_nxv16bf16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {955; CHECK-LABEL: intrinsic_vluxei_v_nxv16bf16_nxv16bf16_nxv16i32:956; CHECK:       # %bb.0: # %entry957; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma958; CHECK-NEXT:    vluxei32.v v16, (a0), v8959; CHECK-NEXT:    vmv.v.v v8, v16960; CHECK-NEXT:    ret961entry:962  %a = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.nxv16bf16.nxv16i32(963    <vscale x 16 x bfloat> poison,964    ptr %0,965    <vscale x 16 x i32> %1,966    iXLen %2)967 968  ret <vscale x 16 x bfloat> %a969}970 971define <vscale x 16 x bfloat> @intrinsic_vluxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {972; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32:973; CHECK:       # %bb.0: # %entry974; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu975; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t976; CHECK-NEXT:    ret977entry:978  %a = call <vscale x 16 x bfloat> @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i32(979    <vscale x 16 x bfloat> %0,980    ptr %1,981    <vscale x 16 x i32> %2,982    <vscale x 16 x i1> %3,983    iXLen %4, iXLen 1)984 985  ret <vscale x 16 x bfloat> %a986}987 988define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {989; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32:990; CHECK:       # %bb.0: # %entry991; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma992; CHECK-NEXT:    vluxei32.v v8, (a0), v8993; CHECK-NEXT:    ret994entry:995  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(996    <vscale x 1 x float> poison,997    ptr %0,998    <vscale x 1 x i32> %1,999    iXLen %2)1000 1001  ret <vscale x 1 x float> %a1002}1003 1004define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1005; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i32:1006; CHECK:       # %bb.0: # %entry1007; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1008; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t1009; CHECK-NEXT:    ret1010entry:1011  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(1012    <vscale x 1 x float> %0,1013    ptr %1,1014    <vscale x 1 x i32> %2,1015    <vscale x 1 x i1> %3,1016    iXLen %4, iXLen 1)1017 1018  ret <vscale x 1 x float> %a1019}1020 1021define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1022; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32:1023; CHECK:       # %bb.0: # %entry1024; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1025; CHECK-NEXT:    vluxei32.v v8, (a0), v81026; CHECK-NEXT:    ret1027entry:1028  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(1029    <vscale x 2 x float> poison,1030    ptr %0,1031    <vscale x 2 x i32> %1,1032    iXLen %2)1033 1034  ret <vscale x 2 x float> %a1035}1036 1037define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1038; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i32:1039; CHECK:       # %bb.0: # %entry1040; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1041; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t1042; CHECK-NEXT:    ret1043entry:1044  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(1045    <vscale x 2 x float> %0,1046    ptr %1,1047    <vscale x 2 x i32> %2,1048    <vscale x 2 x i1> %3,1049    iXLen %4, iXLen 1)1050 1051  ret <vscale x 2 x float> %a1052}1053 1054define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1055; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32:1056; CHECK:       # %bb.0: # %entry1057; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1058; CHECK-NEXT:    vluxei32.v v8, (a0), v81059; CHECK-NEXT:    ret1060entry:1061  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(1062    <vscale x 4 x float> poison,1063    ptr %0,1064    <vscale x 4 x i32> %1,1065    iXLen %2)1066 1067  ret <vscale x 4 x float> %a1068}1069 1070define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1071; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i32:1072; CHECK:       # %bb.0: # %entry1073; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1074; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t1075; CHECK-NEXT:    ret1076entry:1077  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(1078    <vscale x 4 x float> %0,1079    ptr %1,1080    <vscale x 4 x i32> %2,1081    <vscale x 4 x i1> %3,1082    iXLen %4, iXLen 1)1083 1084  ret <vscale x 4 x float> %a1085}1086 1087define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1088; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32:1089; CHECK:       # %bb.0: # %entry1090; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1091; CHECK-NEXT:    vluxei32.v v8, (a0), v81092; CHECK-NEXT:    ret1093entry:1094  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(1095    <vscale x 8 x float> poison,1096    ptr %0,1097    <vscale x 8 x i32> %1,1098    iXLen %2)1099 1100  ret <vscale x 8 x float> %a1101}1102 1103define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1104; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i32:1105; CHECK:       # %bb.0: # %entry1106; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1107; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t1108; CHECK-NEXT:    ret1109entry:1110  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(1111    <vscale x 8 x float> %0,1112    ptr %1,1113    <vscale x 8 x i32> %2,1114    <vscale x 8 x i1> %3,1115    iXLen %4, iXLen 1)1116 1117  ret <vscale x 8 x float> %a1118}1119 1120define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {1121; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32:1122; CHECK:       # %bb.0: # %entry1123; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1124; CHECK-NEXT:    vluxei32.v v8, (a0), v81125; CHECK-NEXT:    ret1126entry:1127  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(1128    <vscale x 16 x float> poison,1129    ptr %0,1130    <vscale x 16 x i32> %1,1131    iXLen %2)1132 1133  ret <vscale x 16 x float> %a1134}1135 1136define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1137; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i32:1138; CHECK:       # %bb.0: # %entry1139; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1140; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t1141; CHECK-NEXT:    ret1142entry:1143  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(1144    <vscale x 16 x float> %0,1145    ptr %1,1146    <vscale x 16 x i32> %2,1147    <vscale x 16 x i1> %3,1148    iXLen %4, iXLen 1)1149 1150  ret <vscale x 16 x float> %a1151}1152 1153define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {1154; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:1155; CHECK:       # %bb.0: # %entry1156; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1157; CHECK-NEXT:    vluxei32.v v9, (a0), v81158; CHECK-NEXT:    vmv.v.v v8, v91159; CHECK-NEXT:    ret1160entry:1161  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(1162    <vscale x 1 x double> poison,1163    ptr %0,1164    <vscale x 1 x i32> %1,1165    iXLen %2)1166 1167  ret <vscale x 1 x double> %a1168}1169 1170define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1171; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i32:1172; CHECK:       # %bb.0: # %entry1173; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1174; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t1175; CHECK-NEXT:    ret1176entry:1177  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(1178    <vscale x 1 x double> %0,1179    ptr %1,1180    <vscale x 1 x i32> %2,1181    <vscale x 1 x i1> %3,1182    iXLen %4, iXLen 1)1183 1184  ret <vscale x 1 x double> %a1185}1186 1187define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1188; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:1189; CHECK:       # %bb.0: # %entry1190; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1191; CHECK-NEXT:    vmv1r.v v10, v81192; CHECK-NEXT:    vluxei32.v v8, (a0), v101193; CHECK-NEXT:    ret1194entry:1195  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(1196    <vscale x 2 x double> poison,1197    ptr %0,1198    <vscale x 2 x i32> %1,1199    iXLen %2)1200 1201  ret <vscale x 2 x double> %a1202}1203 1204define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1205; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i32:1206; CHECK:       # %bb.0: # %entry1207; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1208; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t1209; CHECK-NEXT:    ret1210entry:1211  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(1212    <vscale x 2 x double> %0,1213    ptr %1,1214    <vscale x 2 x i32> %2,1215    <vscale x 2 x i1> %3,1216    iXLen %4, iXLen 1)1217 1218  ret <vscale x 2 x double> %a1219}1220 1221define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1222; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:1223; CHECK:       # %bb.0: # %entry1224; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1225; CHECK-NEXT:    vmv2r.v v12, v81226; CHECK-NEXT:    vluxei32.v v8, (a0), v121227; CHECK-NEXT:    ret1228entry:1229  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(1230    <vscale x 4 x double> poison,1231    ptr %0,1232    <vscale x 4 x i32> %1,1233    iXLen %2)1234 1235  ret <vscale x 4 x double> %a1236}1237 1238define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1239; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i32:1240; CHECK:       # %bb.0: # %entry1241; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1242; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t1243; CHECK-NEXT:    ret1244entry:1245  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(1246    <vscale x 4 x double> %0,1247    ptr %1,1248    <vscale x 4 x i32> %2,1249    <vscale x 4 x i1> %3,1250    iXLen %4, iXLen 1)1251 1252  ret <vscale x 4 x double> %a1253}1254 1255define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1256; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:1257; CHECK:       # %bb.0: # %entry1258; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1259; CHECK-NEXT:    vmv4r.v v16, v81260; CHECK-NEXT:    vluxei32.v v8, (a0), v161261; CHECK-NEXT:    ret1262entry:1263  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(1264    <vscale x 8 x double> poison,1265    ptr %0,1266    <vscale x 8 x i32> %1,1267    iXLen %2)1268 1269  ret <vscale x 8 x double> %a1270}1271 1272define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1273; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i32:1274; CHECK:       # %bb.0: # %entry1275; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1276; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t1277; CHECK-NEXT:    ret1278entry:1279  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(1280    <vscale x 8 x double> %0,1281    ptr %1,1282    <vscale x 8 x i32> %2,1283    <vscale x 8 x i1> %3,1284    iXLen %4, iXLen 1)1285 1286  ret <vscale x 8 x double> %a1287}1288 1289define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1290; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:1291; CHECK:       # %bb.0: # %entry1292; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma1293; CHECK-NEXT:    vluxei16.v v9, (a0), v81294; CHECK-NEXT:    vmv1r.v v8, v91295; CHECK-NEXT:    ret1296entry:1297  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(1298    <vscale x 1 x i8> poison,1299    ptr %0,1300    <vscale x 1 x i16> %1,1301    iXLen %2)1302 1303  ret <vscale x 1 x i8> %a1304}1305 1306define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1307; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i16:1308; CHECK:       # %bb.0: # %entry1309; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu1310; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1311; CHECK-NEXT:    ret1312entry:1313  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(1314    <vscale x 1 x i8> %0,1315    ptr %1,1316    <vscale x 1 x i16> %2,1317    <vscale x 1 x i1> %3,1318    iXLen %4, iXLen 1)1319 1320  ret <vscale x 1 x i8> %a1321}1322 1323define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1324; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:1325; CHECK:       # %bb.0: # %entry1326; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma1327; CHECK-NEXT:    vluxei16.v v9, (a0), v81328; CHECK-NEXT:    vmv1r.v v8, v91329; CHECK-NEXT:    ret1330entry:1331  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(1332    <vscale x 2 x i8> poison,1333    ptr %0,1334    <vscale x 2 x i16> %1,1335    iXLen %2)1336 1337  ret <vscale x 2 x i8> %a1338}1339 1340define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1341; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i16:1342; CHECK:       # %bb.0: # %entry1343; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu1344; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1345; CHECK-NEXT:    ret1346entry:1347  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(1348    <vscale x 2 x i8> %0,1349    ptr %1,1350    <vscale x 2 x i16> %2,1351    <vscale x 2 x i1> %3,1352    iXLen %4, iXLen 1)1353 1354  ret <vscale x 2 x i8> %a1355}1356 1357define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1358; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:1359; CHECK:       # %bb.0: # %entry1360; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma1361; CHECK-NEXT:    vluxei16.v v9, (a0), v81362; CHECK-NEXT:    vmv1r.v v8, v91363; CHECK-NEXT:    ret1364entry:1365  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(1366    <vscale x 4 x i8> poison,1367    ptr %0,1368    <vscale x 4 x i16> %1,1369    iXLen %2)1370 1371  ret <vscale x 4 x i8> %a1372}1373 1374define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1375; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i16:1376; CHECK:       # %bb.0: # %entry1377; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu1378; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1379; CHECK-NEXT:    ret1380entry:1381  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(1382    <vscale x 4 x i8> %0,1383    ptr %1,1384    <vscale x 4 x i16> %2,1385    <vscale x 4 x i1> %3,1386    iXLen %4, iXLen 1)1387 1388  ret <vscale x 4 x i8> %a1389}1390 1391define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1392; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:1393; CHECK:       # %bb.0: # %entry1394; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma1395; CHECK-NEXT:    vluxei16.v v10, (a0), v81396; CHECK-NEXT:    vmv.v.v v8, v101397; CHECK-NEXT:    ret1398entry:1399  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(1400    <vscale x 8 x i8> poison,1401    ptr %0,1402    <vscale x 8 x i16> %1,1403    iXLen %2)1404 1405  ret <vscale x 8 x i8> %a1406}1407 1408define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1409; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i16:1410; CHECK:       # %bb.0: # %entry1411; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu1412; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1413; CHECK-NEXT:    ret1414entry:1415  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(1416    <vscale x 8 x i8> %0,1417    ptr %1,1418    <vscale x 8 x i16> %2,1419    <vscale x 8 x i1> %3,1420    iXLen %4, iXLen 1)1421 1422  ret <vscale x 8 x i8> %a1423}1424 1425define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1426; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:1427; CHECK:       # %bb.0: # %entry1428; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma1429; CHECK-NEXT:    vluxei16.v v12, (a0), v81430; CHECK-NEXT:    vmv.v.v v8, v121431; CHECK-NEXT:    ret1432entry:1433  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(1434    <vscale x 16 x i8> poison,1435    ptr %0,1436    <vscale x 16 x i16> %1,1437    iXLen %2)1438 1439  ret <vscale x 16 x i8> %a1440}1441 1442define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1443; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i16:1444; CHECK:       # %bb.0: # %entry1445; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu1446; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1447; CHECK-NEXT:    ret1448entry:1449  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(1450    <vscale x 16 x i8> %0,1451    ptr %1,1452    <vscale x 16 x i16> %2,1453    <vscale x 16 x i1> %3,1454    iXLen %4, iXLen 1)1455 1456  ret <vscale x 16 x i8> %a1457}1458 1459define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1460; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:1461; CHECK:       # %bb.0: # %entry1462; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma1463; CHECK-NEXT:    vluxei16.v v16, (a0), v81464; CHECK-NEXT:    vmv.v.v v8, v161465; CHECK-NEXT:    ret1466entry:1467  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(1468    <vscale x 32 x i8> poison,1469    ptr %0,1470    <vscale x 32 x i16> %1,1471    iXLen %2)1472 1473  ret <vscale x 32 x i8> %a1474}1475 1476define <vscale x 32 x i8> @intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1477; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i16:1478; CHECK:       # %bb.0: # %entry1479; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu1480; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1481; CHECK-NEXT:    ret1482entry:1483  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(1484    <vscale x 32 x i8> %0,1485    ptr %1,1486    <vscale x 32 x i16> %2,1487    <vscale x 32 x i1> %3,1488    iXLen %4, iXLen 1)1489 1490  ret <vscale x 32 x i8> %a1491}1492 1493define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1494; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16:1495; CHECK:       # %bb.0: # %entry1496; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1497; CHECK-NEXT:    vluxei16.v v8, (a0), v81498; CHECK-NEXT:    ret1499entry:1500  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(1501    <vscale x 1 x i16> poison,1502    ptr %0,1503    <vscale x 1 x i16> %1,1504    iXLen %2)1505 1506  ret <vscale x 1 x i16> %a1507}1508 1509define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1510; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i16:1511; CHECK:       # %bb.0: # %entry1512; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1513; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1514; CHECK-NEXT:    ret1515entry:1516  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(1517    <vscale x 1 x i16> %0,1518    ptr %1,1519    <vscale x 1 x i16> %2,1520    <vscale x 1 x i1> %3,1521    iXLen %4, iXLen 1)1522 1523  ret <vscale x 1 x i16> %a1524}1525 1526define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1527; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16:1528; CHECK:       # %bb.0: # %entry1529; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1530; CHECK-NEXT:    vluxei16.v v8, (a0), v81531; CHECK-NEXT:    ret1532entry:1533  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(1534    <vscale x 2 x i16> poison,1535    ptr %0,1536    <vscale x 2 x i16> %1,1537    iXLen %2)1538 1539  ret <vscale x 2 x i16> %a1540}1541 1542define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1543; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i16:1544; CHECK:       # %bb.0: # %entry1545; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1546; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1547; CHECK-NEXT:    ret1548entry:1549  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(1550    <vscale x 2 x i16> %0,1551    ptr %1,1552    <vscale x 2 x i16> %2,1553    <vscale x 2 x i1> %3,1554    iXLen %4, iXLen 1)1555 1556  ret <vscale x 2 x i16> %a1557}1558 1559define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1560; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16:1561; CHECK:       # %bb.0: # %entry1562; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1563; CHECK-NEXT:    vluxei16.v v8, (a0), v81564; CHECK-NEXT:    ret1565entry:1566  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(1567    <vscale x 4 x i16> poison,1568    ptr %0,1569    <vscale x 4 x i16> %1,1570    iXLen %2)1571 1572  ret <vscale x 4 x i16> %a1573}1574 1575define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1576; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i16:1577; CHECK:       # %bb.0: # %entry1578; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1579; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1580; CHECK-NEXT:    ret1581entry:1582  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(1583    <vscale x 4 x i16> %0,1584    ptr %1,1585    <vscale x 4 x i16> %2,1586    <vscale x 4 x i1> %3,1587    iXLen %4, iXLen 1)1588 1589  ret <vscale x 4 x i16> %a1590}1591 1592define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1593; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16:1594; CHECK:       # %bb.0: # %entry1595; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1596; CHECK-NEXT:    vluxei16.v v8, (a0), v81597; CHECK-NEXT:    ret1598entry:1599  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(1600    <vscale x 8 x i16> poison,1601    ptr %0,1602    <vscale x 8 x i16> %1,1603    iXLen %2)1604 1605  ret <vscale x 8 x i16> %a1606}1607 1608define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1609; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i16:1610; CHECK:       # %bb.0: # %entry1611; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1612; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1613; CHECK-NEXT:    ret1614entry:1615  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(1616    <vscale x 8 x i16> %0,1617    ptr %1,1618    <vscale x 8 x i16> %2,1619    <vscale x 8 x i1> %3,1620    iXLen %4, iXLen 1)1621 1622  ret <vscale x 8 x i16> %a1623}1624 1625define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1626; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16:1627; CHECK:       # %bb.0: # %entry1628; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1629; CHECK-NEXT:    vluxei16.v v8, (a0), v81630; CHECK-NEXT:    ret1631entry:1632  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(1633    <vscale x 16 x i16> poison,1634    ptr %0,1635    <vscale x 16 x i16> %1,1636    iXLen %2)1637 1638  ret <vscale x 16 x i16> %a1639}1640 1641define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1642; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i16:1643; CHECK:       # %bb.0: # %entry1644; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1645; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1646; CHECK-NEXT:    ret1647entry:1648  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(1649    <vscale x 16 x i16> %0,1650    ptr %1,1651    <vscale x 16 x i16> %2,1652    <vscale x 16 x i1> %3,1653    iXLen %4, iXLen 1)1654 1655  ret <vscale x 16 x i16> %a1656}1657 1658define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1659; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16:1660; CHECK:       # %bb.0: # %entry1661; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1662; CHECK-NEXT:    vluxei16.v v8, (a0), v81663; CHECK-NEXT:    ret1664entry:1665  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(1666    <vscale x 32 x i16> poison,1667    ptr %0,1668    <vscale x 32 x i16> %1,1669    iXLen %2)1670 1671  ret <vscale x 32 x i16> %a1672}1673 1674define <vscale x 32 x i16> @intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1675; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i16:1676; CHECK:       # %bb.0: # %entry1677; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1678; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1679; CHECK-NEXT:    ret1680entry:1681  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(1682    <vscale x 32 x i16> %0,1683    ptr %1,1684    <vscale x 32 x i16> %2,1685    <vscale x 32 x i1> %3,1686    iXLen %4, iXLen 1)1687 1688  ret <vscale x 32 x i16> %a1689}1690 1691define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1692; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:1693; CHECK:       # %bb.0: # %entry1694; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1695; CHECK-NEXT:    vluxei16.v v9, (a0), v81696; CHECK-NEXT:    vmv1r.v v8, v91697; CHECK-NEXT:    ret1698entry:1699  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(1700    <vscale x 1 x i32> poison,1701    ptr %0,1702    <vscale x 1 x i16> %1,1703    iXLen %2)1704 1705  ret <vscale x 1 x i32> %a1706}1707 1708define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1709; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16:1710; CHECK:       # %bb.0: # %entry1711; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1712; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1713; CHECK-NEXT:    ret1714entry:1715  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(1716    <vscale x 1 x i32> %0,1717    ptr %1,1718    <vscale x 1 x i16> %2,1719    <vscale x 1 x i1> %3,1720    iXLen %4, iXLen 1)1721 1722  ret <vscale x 1 x i32> %a1723}1724 1725define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1726; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:1727; CHECK:       # %bb.0: # %entry1728; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1729; CHECK-NEXT:    vluxei16.v v9, (a0), v81730; CHECK-NEXT:    vmv.v.v v8, v91731; CHECK-NEXT:    ret1732entry:1733  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(1734    <vscale x 2 x i32> poison,1735    ptr %0,1736    <vscale x 2 x i16> %1,1737    iXLen %2)1738 1739  ret <vscale x 2 x i32> %a1740}1741 1742define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1743; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i16:1744; CHECK:       # %bb.0: # %entry1745; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1746; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1747; CHECK-NEXT:    ret1748entry:1749  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(1750    <vscale x 2 x i32> %0,1751    ptr %1,1752    <vscale x 2 x i16> %2,1753    <vscale x 2 x i1> %3,1754    iXLen %4, iXLen 1)1755 1756  ret <vscale x 2 x i32> %a1757}1758 1759define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1760; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:1761; CHECK:       # %bb.0: # %entry1762; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1763; CHECK-NEXT:    vmv1r.v v10, v81764; CHECK-NEXT:    vluxei16.v v8, (a0), v101765; CHECK-NEXT:    ret1766entry:1767  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(1768    <vscale x 4 x i32> poison,1769    ptr %0,1770    <vscale x 4 x i16> %1,1771    iXLen %2)1772 1773  ret <vscale x 4 x i32> %a1774}1775 1776define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1777; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i16:1778; CHECK:       # %bb.0: # %entry1779; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1780; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1781; CHECK-NEXT:    ret1782entry:1783  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(1784    <vscale x 4 x i32> %0,1785    ptr %1,1786    <vscale x 4 x i16> %2,1787    <vscale x 4 x i1> %3,1788    iXLen %4, iXLen 1)1789 1790  ret <vscale x 4 x i32> %a1791}1792 1793define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1794; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:1795; CHECK:       # %bb.0: # %entry1796; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1797; CHECK-NEXT:    vmv2r.v v12, v81798; CHECK-NEXT:    vluxei16.v v8, (a0), v121799; CHECK-NEXT:    ret1800entry:1801  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(1802    <vscale x 8 x i32> poison,1803    ptr %0,1804    <vscale x 8 x i16> %1,1805    iXLen %2)1806 1807  ret <vscale x 8 x i32> %a1808}1809 1810define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1811; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i16:1812; CHECK:       # %bb.0: # %entry1813; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1814; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1815; CHECK-NEXT:    ret1816entry:1817  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(1818    <vscale x 8 x i32> %0,1819    ptr %1,1820    <vscale x 8 x i16> %2,1821    <vscale x 8 x i1> %3,1822    iXLen %4, iXLen 1)1823 1824  ret <vscale x 8 x i32> %a1825}1826 1827define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1828; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:1829; CHECK:       # %bb.0: # %entry1830; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1831; CHECK-NEXT:    vmv4r.v v16, v81832; CHECK-NEXT:    vluxei16.v v8, (a0), v161833; CHECK-NEXT:    ret1834entry:1835  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(1836    <vscale x 16 x i32> poison,1837    ptr %0,1838    <vscale x 16 x i16> %1,1839    iXLen %2)1840 1841  ret <vscale x 16 x i32> %a1842}1843 1844define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1845; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i16:1846; CHECK:       # %bb.0: # %entry1847; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1848; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1849; CHECK-NEXT:    ret1850entry:1851  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(1852    <vscale x 16 x i32> %0,1853    ptr %1,1854    <vscale x 16 x i16> %2,1855    <vscale x 16 x i1> %3,1856    iXLen %4, iXLen 1)1857 1858  ret <vscale x 16 x i32> %a1859}1860 1861define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1862; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:1863; CHECK:       # %bb.0: # %entry1864; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1865; CHECK-NEXT:    vluxei16.v v9, (a0), v81866; CHECK-NEXT:    vmv.v.v v8, v91867; CHECK-NEXT:    ret1868entry:1869  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(1870    <vscale x 1 x i64> poison,1871    ptr %0,1872    <vscale x 1 x i16> %1,1873    iXLen %2)1874 1875  ret <vscale x 1 x i64> %a1876}1877 1878define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1879; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i16:1880; CHECK:       # %bb.0: # %entry1881; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1882; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1883; CHECK-NEXT:    ret1884entry:1885  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(1886    <vscale x 1 x i64> %0,1887    ptr %1,1888    <vscale x 1 x i16> %2,1889    <vscale x 1 x i1> %3,1890    iXLen %4, iXLen 1)1891 1892  ret <vscale x 1 x i64> %a1893}1894 1895define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1896; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:1897; CHECK:       # %bb.0: # %entry1898; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1899; CHECK-NEXT:    vmv1r.v v10, v81900; CHECK-NEXT:    vluxei16.v v8, (a0), v101901; CHECK-NEXT:    ret1902entry:1903  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(1904    <vscale x 2 x i64> poison,1905    ptr %0,1906    <vscale x 2 x i16> %1,1907    iXLen %2)1908 1909  ret <vscale x 2 x i64> %a1910}1911 1912define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1913; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i16:1914; CHECK:       # %bb.0: # %entry1915; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1916; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1917; CHECK-NEXT:    ret1918entry:1919  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(1920    <vscale x 2 x i64> %0,1921    ptr %1,1922    <vscale x 2 x i16> %2,1923    <vscale x 2 x i1> %3,1924    iXLen %4, iXLen 1)1925 1926  ret <vscale x 2 x i64> %a1927}1928 1929define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1930; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:1931; CHECK:       # %bb.0: # %entry1932; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1933; CHECK-NEXT:    vmv1r.v v12, v81934; CHECK-NEXT:    vluxei16.v v8, (a0), v121935; CHECK-NEXT:    ret1936entry:1937  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(1938    <vscale x 4 x i64> poison,1939    ptr %0,1940    <vscale x 4 x i16> %1,1941    iXLen %2)1942 1943  ret <vscale x 4 x i64> %a1944}1945 1946define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1947; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i16:1948; CHECK:       # %bb.0: # %entry1949; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1950; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1951; CHECK-NEXT:    ret1952entry:1953  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(1954    <vscale x 4 x i64> %0,1955    ptr %1,1956    <vscale x 4 x i16> %2,1957    <vscale x 4 x i1> %3,1958    iXLen %4, iXLen 1)1959 1960  ret <vscale x 4 x i64> %a1961}1962 1963define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1964; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16:1965; CHECK:       # %bb.0: # %entry1966; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1967; CHECK-NEXT:    vmv2r.v v16, v81968; CHECK-NEXT:    vluxei16.v v8, (a0), v161969; CHECK-NEXT:    ret1970entry:1971  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(1972    <vscale x 8 x i64> poison,1973    ptr %0,1974    <vscale x 8 x i16> %1,1975    iXLen %2)1976 1977  ret <vscale x 8 x i64> %a1978}1979 1980define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1981; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i16:1982; CHECK:       # %bb.0: # %entry1983; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1984; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1985; CHECK-NEXT:    ret1986entry:1987  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(1988    <vscale x 8 x i64> %0,1989    ptr %1,1990    <vscale x 8 x i16> %2,1991    <vscale x 8 x i1> %3,1992    iXLen %4, iXLen 1)1993 1994  ret <vscale x 8 x i64> %a1995}1996 1997define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1998; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16:1999; CHECK:       # %bb.0: # %entry2000; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2001; CHECK-NEXT:    vluxei16.v v8, (a0), v82002; CHECK-NEXT:    ret2003entry:2004  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(2005    <vscale x 1 x half> poison,2006    ptr %0,2007    <vscale x 1 x i16> %1,2008    iXLen %2)2009 2010  ret <vscale x 1 x half> %a2011}2012 2013define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2014; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i16:2015; CHECK:       # %bb.0: # %entry2016; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu2017; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2018; CHECK-NEXT:    ret2019entry:2020  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(2021    <vscale x 1 x half> %0,2022    ptr %1,2023    <vscale x 1 x i16> %2,2024    <vscale x 1 x i1> %3,2025    iXLen %4, iXLen 1)2026 2027  ret <vscale x 1 x half> %a2028}2029 2030define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2031; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16:2032; CHECK:       # %bb.0: # %entry2033; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2034; CHECK-NEXT:    vluxei16.v v8, (a0), v82035; CHECK-NEXT:    ret2036entry:2037  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(2038    <vscale x 2 x half> poison,2039    ptr %0,2040    <vscale x 2 x i16> %1,2041    iXLen %2)2042 2043  ret <vscale x 2 x half> %a2044}2045 2046define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2047; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i16:2048; CHECK:       # %bb.0: # %entry2049; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu2050; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2051; CHECK-NEXT:    ret2052entry:2053  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(2054    <vscale x 2 x half> %0,2055    ptr %1,2056    <vscale x 2 x i16> %2,2057    <vscale x 2 x i1> %3,2058    iXLen %4, iXLen 1)2059 2060  ret <vscale x 2 x half> %a2061}2062 2063define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2064; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16:2065; CHECK:       # %bb.0: # %entry2066; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2067; CHECK-NEXT:    vluxei16.v v8, (a0), v82068; CHECK-NEXT:    ret2069entry:2070  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(2071    <vscale x 4 x half> poison,2072    ptr %0,2073    <vscale x 4 x i16> %1,2074    iXLen %2)2075 2076  ret <vscale x 4 x half> %a2077}2078 2079define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2080; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i16:2081; CHECK:       # %bb.0: # %entry2082; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu2083; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2084; CHECK-NEXT:    ret2085entry:2086  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(2087    <vscale x 4 x half> %0,2088    ptr %1,2089    <vscale x 4 x i16> %2,2090    <vscale x 4 x i1> %3,2091    iXLen %4, iXLen 1)2092 2093  ret <vscale x 4 x half> %a2094}2095 2096define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2097; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16:2098; CHECK:       # %bb.0: # %entry2099; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2100; CHECK-NEXT:    vluxei16.v v8, (a0), v82101; CHECK-NEXT:    ret2102entry:2103  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(2104    <vscale x 8 x half> poison,2105    ptr %0,2106    <vscale x 8 x i16> %1,2107    iXLen %2)2108 2109  ret <vscale x 8 x half> %a2110}2111 2112define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2113; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i16:2114; CHECK:       # %bb.0: # %entry2115; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu2116; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t2117; CHECK-NEXT:    ret2118entry:2119  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(2120    <vscale x 8 x half> %0,2121    ptr %1,2122    <vscale x 8 x i16> %2,2123    <vscale x 8 x i1> %3,2124    iXLen %4, iXLen 1)2125 2126  ret <vscale x 8 x half> %a2127}2128 2129define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {2130; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16:2131; CHECK:       # %bb.0: # %entry2132; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2133; CHECK-NEXT:    vluxei16.v v8, (a0), v82134; CHECK-NEXT:    ret2135entry:2136  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(2137    <vscale x 16 x half> poison,2138    ptr %0,2139    <vscale x 16 x i16> %1,2140    iXLen %2)2141 2142  ret <vscale x 16 x half> %a2143}2144 2145define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2146; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i16:2147; CHECK:       # %bb.0: # %entry2148; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu2149; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t2150; CHECK-NEXT:    ret2151entry:2152  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(2153    <vscale x 16 x half> %0,2154    ptr %1,2155    <vscale x 16 x i16> %2,2156    <vscale x 16 x i1> %3,2157    iXLen %4, iXLen 1)2158 2159  ret <vscale x 16 x half> %a2160}2161 2162define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {2163; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16:2164; CHECK:       # %bb.0: # %entry2165; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2166; CHECK-NEXT:    vluxei16.v v8, (a0), v82167; CHECK-NEXT:    ret2168entry:2169  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(2170    <vscale x 32 x half> poison,2171    ptr %0,2172    <vscale x 32 x i16> %1,2173    iXLen %2)2174 2175  ret <vscale x 32 x half> %a2176}2177 2178define <vscale x 32 x half> @intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2179; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i16:2180; CHECK:       # %bb.0: # %entry2181; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2182; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2183; CHECK-NEXT:    ret2184entry:2185  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(2186    <vscale x 32 x half> %0,2187    ptr %1,2188    <vscale x 32 x i16> %2,2189    <vscale x 32 x i1> %3,2190    iXLen %4, iXLen 1)2191 2192  ret <vscale x 32 x half> %a2193}2194 2195define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2196; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:2197; CHECK:       # %bb.0: # %entry2198; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2199; CHECK-NEXT:    vluxei16.v v9, (a0), v82200; CHECK-NEXT:    vmv1r.v v8, v92201; CHECK-NEXT:    ret2202entry:2203  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(2204    <vscale x 1 x float> poison,2205    ptr %0,2206    <vscale x 1 x i16> %1,2207    iXLen %2)2208 2209  ret <vscale x 1 x float> %a2210}2211 2212define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2213; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i16:2214; CHECK:       # %bb.0: # %entry2215; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2216; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2217; CHECK-NEXT:    ret2218entry:2219  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(2220    <vscale x 1 x float> %0,2221    ptr %1,2222    <vscale x 1 x i16> %2,2223    <vscale x 1 x i1> %3,2224    iXLen %4, iXLen 1)2225 2226  ret <vscale x 1 x float> %a2227}2228 2229define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2230; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:2231; CHECK:       # %bb.0: # %entry2232; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2233; CHECK-NEXT:    vluxei16.v v9, (a0), v82234; CHECK-NEXT:    vmv.v.v v8, v92235; CHECK-NEXT:    ret2236entry:2237  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(2238    <vscale x 2 x float> poison,2239    ptr %0,2240    <vscale x 2 x i16> %1,2241    iXLen %2)2242 2243  ret <vscale x 2 x float> %a2244}2245 2246define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2247; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i16:2248; CHECK:       # %bb.0: # %entry2249; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2250; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2251; CHECK-NEXT:    ret2252entry:2253  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(2254    <vscale x 2 x float> %0,2255    ptr %1,2256    <vscale x 2 x i16> %2,2257    <vscale x 2 x i1> %3,2258    iXLen %4, iXLen 1)2259 2260  ret <vscale x 2 x float> %a2261}2262 2263define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2264; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:2265; CHECK:       # %bb.0: # %entry2266; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2267; CHECK-NEXT:    vmv1r.v v10, v82268; CHECK-NEXT:    vluxei16.v v8, (a0), v102269; CHECK-NEXT:    ret2270entry:2271  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(2272    <vscale x 4 x float> poison,2273    ptr %0,2274    <vscale x 4 x i16> %1,2275    iXLen %2)2276 2277  ret <vscale x 4 x float> %a2278}2279 2280define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2281; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i16:2282; CHECK:       # %bb.0: # %entry2283; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2284; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t2285; CHECK-NEXT:    ret2286entry:2287  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(2288    <vscale x 4 x float> %0,2289    ptr %1,2290    <vscale x 4 x i16> %2,2291    <vscale x 4 x i1> %3,2292    iXLen %4, iXLen 1)2293 2294  ret <vscale x 4 x float> %a2295}2296 2297define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2298; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:2299; CHECK:       # %bb.0: # %entry2300; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2301; CHECK-NEXT:    vmv2r.v v12, v82302; CHECK-NEXT:    vluxei16.v v8, (a0), v122303; CHECK-NEXT:    ret2304entry:2305  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(2306    <vscale x 8 x float> poison,2307    ptr %0,2308    <vscale x 8 x i16> %1,2309    iXLen %2)2310 2311  ret <vscale x 8 x float> %a2312}2313 2314define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2315; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i16:2316; CHECK:       # %bb.0: # %entry2317; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2318; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t2319; CHECK-NEXT:    ret2320entry:2321  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(2322    <vscale x 8 x float> %0,2323    ptr %1,2324    <vscale x 8 x i16> %2,2325    <vscale x 8 x i1> %3,2326    iXLen %4, iXLen 1)2327 2328  ret <vscale x 8 x float> %a2329}2330 2331define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {2332; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:2333; CHECK:       # %bb.0: # %entry2334; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2335; CHECK-NEXT:    vmv4r.v v16, v82336; CHECK-NEXT:    vluxei16.v v8, (a0), v162337; CHECK-NEXT:    ret2338entry:2339  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(2340    <vscale x 16 x float> poison,2341    ptr %0,2342    <vscale x 16 x i16> %1,2343    iXLen %2)2344 2345  ret <vscale x 16 x float> %a2346}2347 2348define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2349; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i16:2350; CHECK:       # %bb.0: # %entry2351; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2352; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2353; CHECK-NEXT:    ret2354entry:2355  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(2356    <vscale x 16 x float> %0,2357    ptr %1,2358    <vscale x 16 x i16> %2,2359    <vscale x 16 x i1> %3,2360    iXLen %4, iXLen 1)2361 2362  ret <vscale x 16 x float> %a2363}2364 2365define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2366; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:2367; CHECK:       # %bb.0: # %entry2368; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2369; CHECK-NEXT:    vluxei16.v v9, (a0), v82370; CHECK-NEXT:    vmv.v.v v8, v92371; CHECK-NEXT:    ret2372entry:2373  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(2374    <vscale x 1 x double> poison,2375    ptr %0,2376    <vscale x 1 x i16> %1,2377    iXLen %2)2378 2379  ret <vscale x 1 x double> %a2380}2381 2382define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2383; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i16:2384; CHECK:       # %bb.0: # %entry2385; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2386; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2387; CHECK-NEXT:    ret2388entry:2389  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(2390    <vscale x 1 x double> %0,2391    ptr %1,2392    <vscale x 1 x i16> %2,2393    <vscale x 1 x i1> %3,2394    iXLen %4, iXLen 1)2395 2396  ret <vscale x 1 x double> %a2397}2398 2399define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2400; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:2401; CHECK:       # %bb.0: # %entry2402; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2403; CHECK-NEXT:    vmv1r.v v10, v82404; CHECK-NEXT:    vluxei16.v v8, (a0), v102405; CHECK-NEXT:    ret2406entry:2407  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(2408    <vscale x 2 x double> poison,2409    ptr %0,2410    <vscale x 2 x i16> %1,2411    iXLen %2)2412 2413  ret <vscale x 2 x double> %a2414}2415 2416define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2417; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i16:2418; CHECK:       # %bb.0: # %entry2419; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu2420; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t2421; CHECK-NEXT:    ret2422entry:2423  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(2424    <vscale x 2 x double> %0,2425    ptr %1,2426    <vscale x 2 x i16> %2,2427    <vscale x 2 x i1> %3,2428    iXLen %4, iXLen 1)2429 2430  ret <vscale x 2 x double> %a2431}2432 2433define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2434; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:2435; CHECK:       # %bb.0: # %entry2436; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2437; CHECK-NEXT:    vmv1r.v v12, v82438; CHECK-NEXT:    vluxei16.v v8, (a0), v122439; CHECK-NEXT:    ret2440entry:2441  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(2442    <vscale x 4 x double> poison,2443    ptr %0,2444    <vscale x 4 x i16> %1,2445    iXLen %2)2446 2447  ret <vscale x 4 x double> %a2448}2449 2450define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2451; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i16:2452; CHECK:       # %bb.0: # %entry2453; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu2454; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t2455; CHECK-NEXT:    ret2456entry:2457  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(2458    <vscale x 4 x double> %0,2459    ptr %1,2460    <vscale x 4 x i16> %2,2461    <vscale x 4 x i1> %3,2462    iXLen %4, iXLen 1)2463 2464  ret <vscale x 4 x double> %a2465}2466 2467define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2468; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:2469; CHECK:       # %bb.0: # %entry2470; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2471; CHECK-NEXT:    vmv2r.v v16, v82472; CHECK-NEXT:    vluxei16.v v8, (a0), v162473; CHECK-NEXT:    ret2474entry:2475  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(2476    <vscale x 8 x double> poison,2477    ptr %0,2478    <vscale x 8 x i16> %1,2479    iXLen %2)2480 2481  ret <vscale x 8 x double> %a2482}2483 2484define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2485; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i16:2486; CHECK:       # %bb.0: # %entry2487; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu2488; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2489; CHECK-NEXT:    ret2490entry:2491  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(2492    <vscale x 8 x double> %0,2493    ptr %1,2494    <vscale x 8 x i16> %2,2495    <vscale x 8 x i1> %3,2496    iXLen %4, iXLen 1)2497 2498  ret <vscale x 8 x double> %a2499}2500 2501define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2502; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8:2503; CHECK:       # %bb.0: # %entry2504; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma2505; CHECK-NEXT:    vluxei8.v v8, (a0), v82506; CHECK-NEXT:    ret2507entry:2508  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(2509    <vscale x 1 x i8> poison,2510    ptr %0,2511    <vscale x 1 x i8> %1,2512    iXLen %2)2513 2514  ret <vscale x 1 x i8> %a2515}2516 2517define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2518; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i8:2519; CHECK:       # %bb.0: # %entry2520; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu2521; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2522; CHECK-NEXT:    ret2523entry:2524  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(2525    <vscale x 1 x i8> %0,2526    ptr %1,2527    <vscale x 1 x i8> %2,2528    <vscale x 1 x i1> %3,2529    iXLen %4, iXLen 1)2530 2531  ret <vscale x 1 x i8> %a2532}2533 2534define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2535; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8:2536; CHECK:       # %bb.0: # %entry2537; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma2538; CHECK-NEXT:    vluxei8.v v8, (a0), v82539; CHECK-NEXT:    ret2540entry:2541  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(2542    <vscale x 2 x i8> poison,2543    ptr %0,2544    <vscale x 2 x i8> %1,2545    iXLen %2)2546 2547  ret <vscale x 2 x i8> %a2548}2549 2550define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2551; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i8:2552; CHECK:       # %bb.0: # %entry2553; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu2554; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2555; CHECK-NEXT:    ret2556entry:2557  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(2558    <vscale x 2 x i8> %0,2559    ptr %1,2560    <vscale x 2 x i8> %2,2561    <vscale x 2 x i1> %3,2562    iXLen %4, iXLen 1)2563 2564  ret <vscale x 2 x i8> %a2565}2566 2567define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2568; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8:2569; CHECK:       # %bb.0: # %entry2570; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma2571; CHECK-NEXT:    vluxei8.v v8, (a0), v82572; CHECK-NEXT:    ret2573entry:2574  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(2575    <vscale x 4 x i8> poison,2576    ptr %0,2577    <vscale x 4 x i8> %1,2578    iXLen %2)2579 2580  ret <vscale x 4 x i8> %a2581}2582 2583define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2584; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i8:2585; CHECK:       # %bb.0: # %entry2586; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu2587; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2588; CHECK-NEXT:    ret2589entry:2590  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(2591    <vscale x 4 x i8> %0,2592    ptr %1,2593    <vscale x 4 x i8> %2,2594    <vscale x 4 x i1> %3,2595    iXLen %4, iXLen 1)2596 2597  ret <vscale x 4 x i8> %a2598}2599 2600define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2601; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8:2602; CHECK:       # %bb.0: # %entry2603; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma2604; CHECK-NEXT:    vluxei8.v v8, (a0), v82605; CHECK-NEXT:    ret2606entry:2607  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(2608    <vscale x 8 x i8> poison,2609    ptr %0,2610    <vscale x 8 x i8> %1,2611    iXLen %2)2612 2613  ret <vscale x 8 x i8> %a2614}2615 2616define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2617; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i8:2618; CHECK:       # %bb.0: # %entry2619; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu2620; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2621; CHECK-NEXT:    ret2622entry:2623  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(2624    <vscale x 8 x i8> %0,2625    ptr %1,2626    <vscale x 8 x i8> %2,2627    <vscale x 8 x i1> %3,2628    iXLen %4, iXLen 1)2629 2630  ret <vscale x 8 x i8> %a2631}2632 2633define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2634; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8:2635; CHECK:       # %bb.0: # %entry2636; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma2637; CHECK-NEXT:    vluxei8.v v8, (a0), v82638; CHECK-NEXT:    ret2639entry:2640  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(2641    <vscale x 16 x i8> poison,2642    ptr %0,2643    <vscale x 16 x i8> %1,2644    iXLen %2)2645 2646  ret <vscale x 16 x i8> %a2647}2648 2649define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2650; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i8:2651; CHECK:       # %bb.0: # %entry2652; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu2653; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t2654; CHECK-NEXT:    ret2655entry:2656  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(2657    <vscale x 16 x i8> %0,2658    ptr %1,2659    <vscale x 16 x i8> %2,2660    <vscale x 16 x i1> %3,2661    iXLen %4, iXLen 1)2662 2663  ret <vscale x 16 x i8> %a2664}2665 2666define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2667; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8:2668; CHECK:       # %bb.0: # %entry2669; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma2670; CHECK-NEXT:    vluxei8.v v8, (a0), v82671; CHECK-NEXT:    ret2672entry:2673  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(2674    <vscale x 32 x i8> poison,2675    ptr %0,2676    <vscale x 32 x i8> %1,2677    iXLen %2)2678 2679  ret <vscale x 32 x i8> %a2680}2681 2682define <vscale x 32 x i8> @intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2683; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i8:2684; CHECK:       # %bb.0: # %entry2685; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu2686; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t2687; CHECK-NEXT:    ret2688entry:2689  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(2690    <vscale x 32 x i8> %0,2691    ptr %1,2692    <vscale x 32 x i8> %2,2693    <vscale x 32 x i1> %3,2694    iXLen %4, iXLen 1)2695 2696  ret <vscale x 32 x i8> %a2697}2698 2699define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(ptr %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {2700; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8:2701; CHECK:       # %bb.0: # %entry2702; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma2703; CHECK-NEXT:    vluxei8.v v8, (a0), v82704; CHECK-NEXT:    ret2705entry:2706  %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(2707    <vscale x 64 x i8> poison,2708    ptr %0,2709    <vscale x 64 x i8> %1,2710    iXLen %2)2711 2712  ret <vscale x 64 x i8> %a2713}2714 2715define <vscale x 64 x i8> @intrinsic_vluxei_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {2716; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv64i8_nxv64i8_nxv64i8:2717; CHECK:       # %bb.0: # %entry2718; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu2719; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t2720; CHECK-NEXT:    ret2721entry:2722  %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(2723    <vscale x 64 x i8> %0,2724    ptr %1,2725    <vscale x 64 x i8> %2,2726    <vscale x 64 x i1> %3,2727    iXLen %4, iXLen 1)2728 2729  ret <vscale x 64 x i8> %a2730}2731 2732define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2733; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:2734; CHECK:       # %bb.0: # %entry2735; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2736; CHECK-NEXT:    vluxei8.v v9, (a0), v82737; CHECK-NEXT:    vmv1r.v v8, v92738; CHECK-NEXT:    ret2739entry:2740  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(2741    <vscale x 1 x i16> poison,2742    ptr %0,2743    <vscale x 1 x i8> %1,2744    iXLen %2)2745 2746  ret <vscale x 1 x i16> %a2747}2748 2749define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2750; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i8:2751; CHECK:       # %bb.0: # %entry2752; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu2753; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2754; CHECK-NEXT:    ret2755entry:2756  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(2757    <vscale x 1 x i16> %0,2758    ptr %1,2759    <vscale x 1 x i8> %2,2760    <vscale x 1 x i1> %3,2761    iXLen %4, iXLen 1)2762 2763  ret <vscale x 1 x i16> %a2764}2765 2766define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2767; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:2768; CHECK:       # %bb.0: # %entry2769; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2770; CHECK-NEXT:    vluxei8.v v9, (a0), v82771; CHECK-NEXT:    vmv1r.v v8, v92772; CHECK-NEXT:    ret2773entry:2774  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(2775    <vscale x 2 x i16> poison,2776    ptr %0,2777    <vscale x 2 x i8> %1,2778    iXLen %2)2779 2780  ret <vscale x 2 x i16> %a2781}2782 2783define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2784; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i8:2785; CHECK:       # %bb.0: # %entry2786; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu2787; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2788; CHECK-NEXT:    ret2789entry:2790  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(2791    <vscale x 2 x i16> %0,2792    ptr %1,2793    <vscale x 2 x i8> %2,2794    <vscale x 2 x i1> %3,2795    iXLen %4, iXLen 1)2796 2797  ret <vscale x 2 x i16> %a2798}2799 2800define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2801; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:2802; CHECK:       # %bb.0: # %entry2803; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2804; CHECK-NEXT:    vluxei8.v v9, (a0), v82805; CHECK-NEXT:    vmv.v.v v8, v92806; CHECK-NEXT:    ret2807entry:2808  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(2809    <vscale x 4 x i16> poison,2810    ptr %0,2811    <vscale x 4 x i8> %1,2812    iXLen %2)2813 2814  ret <vscale x 4 x i16> %a2815}2816 2817define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2818; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i8:2819; CHECK:       # %bb.0: # %entry2820; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu2821; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2822; CHECK-NEXT:    ret2823entry:2824  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(2825    <vscale x 4 x i16> %0,2826    ptr %1,2827    <vscale x 4 x i8> %2,2828    <vscale x 4 x i1> %3,2829    iXLen %4, iXLen 1)2830 2831  ret <vscale x 4 x i16> %a2832}2833 2834define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2835; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:2836; CHECK:       # %bb.0: # %entry2837; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2838; CHECK-NEXT:    vmv1r.v v10, v82839; CHECK-NEXT:    vluxei8.v v8, (a0), v102840; CHECK-NEXT:    ret2841entry:2842  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(2843    <vscale x 8 x i16> poison,2844    ptr %0,2845    <vscale x 8 x i8> %1,2846    iXLen %2)2847 2848  ret <vscale x 8 x i16> %a2849}2850 2851define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2852; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i8:2853; CHECK:       # %bb.0: # %entry2854; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu2855; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t2856; CHECK-NEXT:    ret2857entry:2858  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(2859    <vscale x 8 x i16> %0,2860    ptr %1,2861    <vscale x 8 x i8> %2,2862    <vscale x 8 x i1> %3,2863    iXLen %4, iXLen 1)2864 2865  ret <vscale x 8 x i16> %a2866}2867 2868define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2869; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:2870; CHECK:       # %bb.0: # %entry2871; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2872; CHECK-NEXT:    vmv2r.v v12, v82873; CHECK-NEXT:    vluxei8.v v8, (a0), v122874; CHECK-NEXT:    ret2875entry:2876  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(2877    <vscale x 16 x i16> poison,2878    ptr %0,2879    <vscale x 16 x i8> %1,2880    iXLen %2)2881 2882  ret <vscale x 16 x i16> %a2883}2884 2885define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2886; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i8:2887; CHECK:       # %bb.0: # %entry2888; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu2889; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t2890; CHECK-NEXT:    ret2891entry:2892  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(2893    <vscale x 16 x i16> %0,2894    ptr %1,2895    <vscale x 16 x i8> %2,2896    <vscale x 16 x i1> %3,2897    iXLen %4, iXLen 1)2898 2899  ret <vscale x 16 x i16> %a2900}2901 2902define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2903; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:2904; CHECK:       # %bb.0: # %entry2905; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2906; CHECK-NEXT:    vmv4r.v v16, v82907; CHECK-NEXT:    vluxei8.v v8, (a0), v162908; CHECK-NEXT:    ret2909entry:2910  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(2911    <vscale x 32 x i16> poison,2912    ptr %0,2913    <vscale x 32 x i8> %1,2914    iXLen %2)2915 2916  ret <vscale x 32 x i16> %a2917}2918 2919define <vscale x 32 x i16> @intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2920; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i8:2921; CHECK:       # %bb.0: # %entry2922; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2923; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t2924; CHECK-NEXT:    ret2925entry:2926  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(2927    <vscale x 32 x i16> %0,2928    ptr %1,2929    <vscale x 32 x i8> %2,2930    <vscale x 32 x i1> %3,2931    iXLen %4, iXLen 1)2932 2933  ret <vscale x 32 x i16> %a2934}2935 2936define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2937; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:2938; CHECK:       # %bb.0: # %entry2939; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2940; CHECK-NEXT:    vluxei8.v v9, (a0), v82941; CHECK-NEXT:    vmv1r.v v8, v92942; CHECK-NEXT:    ret2943entry:2944  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(2945    <vscale x 1 x i32> poison,2946    ptr %0,2947    <vscale x 1 x i8> %1,2948    iXLen %2)2949 2950  ret <vscale x 1 x i32> %a2951}2952 2953define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2954; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i8:2955; CHECK:       # %bb.0: # %entry2956; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2957; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2958; CHECK-NEXT:    ret2959entry:2960  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(2961    <vscale x 1 x i32> %0,2962    ptr %1,2963    <vscale x 1 x i8> %2,2964    <vscale x 1 x i1> %3,2965    iXLen %4, iXLen 1)2966 2967  ret <vscale x 1 x i32> %a2968}2969 2970define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2971; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:2972; CHECK:       # %bb.0: # %entry2973; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2974; CHECK-NEXT:    vluxei8.v v9, (a0), v82975; CHECK-NEXT:    vmv.v.v v8, v92976; CHECK-NEXT:    ret2977entry:2978  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(2979    <vscale x 2 x i32> poison,2980    ptr %0,2981    <vscale x 2 x i8> %1,2982    iXLen %2)2983 2984  ret <vscale x 2 x i32> %a2985}2986 2987define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2988; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i8:2989; CHECK:       # %bb.0: # %entry2990; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2991; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2992; CHECK-NEXT:    ret2993entry:2994  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(2995    <vscale x 2 x i32> %0,2996    ptr %1,2997    <vscale x 2 x i8> %2,2998    <vscale x 2 x i1> %3,2999    iXLen %4, iXLen 1)3000 3001  ret <vscale x 2 x i32> %a3002}3003 3004define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3005; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:3006; CHECK:       # %bb.0: # %entry3007; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3008; CHECK-NEXT:    vmv1r.v v10, v83009; CHECK-NEXT:    vluxei8.v v8, (a0), v103010; CHECK-NEXT:    ret3011entry:3012  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(3013    <vscale x 4 x i32> poison,3014    ptr %0,3015    <vscale x 4 x i8> %1,3016    iXLen %2)3017 3018  ret <vscale x 4 x i32> %a3019}3020 3021define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3022; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i8:3023; CHECK:       # %bb.0: # %entry3024; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu3025; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3026; CHECK-NEXT:    ret3027entry:3028  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(3029    <vscale x 4 x i32> %0,3030    ptr %1,3031    <vscale x 4 x i8> %2,3032    <vscale x 4 x i1> %3,3033    iXLen %4, iXLen 1)3034 3035  ret <vscale x 4 x i32> %a3036}3037 3038define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3039; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:3040; CHECK:       # %bb.0: # %entry3041; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma3042; CHECK-NEXT:    vmv1r.v v12, v83043; CHECK-NEXT:    vluxei8.v v8, (a0), v123044; CHECK-NEXT:    ret3045entry:3046  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(3047    <vscale x 8 x i32> poison,3048    ptr %0,3049    <vscale x 8 x i8> %1,3050    iXLen %2)3051 3052  ret <vscale x 8 x i32> %a3053}3054 3055define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3056; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i8:3057; CHECK:       # %bb.0: # %entry3058; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu3059; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3060; CHECK-NEXT:    ret3061entry:3062  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(3063    <vscale x 8 x i32> %0,3064    ptr %1,3065    <vscale x 8 x i8> %2,3066    <vscale x 8 x i1> %3,3067    iXLen %4, iXLen 1)3068 3069  ret <vscale x 8 x i32> %a3070}3071 3072define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3073; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:3074; CHECK:       # %bb.0: # %entry3075; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma3076; CHECK-NEXT:    vmv2r.v v16, v83077; CHECK-NEXT:    vluxei8.v v8, (a0), v163078; CHECK-NEXT:    ret3079entry:3080  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(3081    <vscale x 16 x i32> poison,3082    ptr %0,3083    <vscale x 16 x i8> %1,3084    iXLen %2)3085 3086  ret <vscale x 16 x i32> %a3087}3088 3089define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3090; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i8:3091; CHECK:       # %bb.0: # %entry3092; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu3093; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3094; CHECK-NEXT:    ret3095entry:3096  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(3097    <vscale x 16 x i32> %0,3098    ptr %1,3099    <vscale x 16 x i8> %2,3100    <vscale x 16 x i1> %3,3101    iXLen %4, iXLen 1)3102 3103  ret <vscale x 16 x i32> %a3104}3105 3106define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3107; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:3108; CHECK:       # %bb.0: # %entry3109; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma3110; CHECK-NEXT:    vluxei8.v v9, (a0), v83111; CHECK-NEXT:    vmv.v.v v8, v93112; CHECK-NEXT:    ret3113entry:3114  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(3115    <vscale x 1 x i64> poison,3116    ptr %0,3117    <vscale x 1 x i8> %1,3118    iXLen %2)3119 3120  ret <vscale x 1 x i64> %a3121}3122 3123define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3124; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i8:3125; CHECK:       # %bb.0: # %entry3126; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu3127; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3128; CHECK-NEXT:    ret3129entry:3130  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(3131    <vscale x 1 x i64> %0,3132    ptr %1,3133    <vscale x 1 x i8> %2,3134    <vscale x 1 x i1> %3,3135    iXLen %4, iXLen 1)3136 3137  ret <vscale x 1 x i64> %a3138}3139 3140define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3141; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:3142; CHECK:       # %bb.0: # %entry3143; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3144; CHECK-NEXT:    vmv1r.v v10, v83145; CHECK-NEXT:    vluxei8.v v8, (a0), v103146; CHECK-NEXT:    ret3147entry:3148  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(3149    <vscale x 2 x i64> poison,3150    ptr %0,3151    <vscale x 2 x i8> %1,3152    iXLen %2)3153 3154  ret <vscale x 2 x i64> %a3155}3156 3157define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3158; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i8:3159; CHECK:       # %bb.0: # %entry3160; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu3161; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3162; CHECK-NEXT:    ret3163entry:3164  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(3165    <vscale x 2 x i64> %0,3166    ptr %1,3167    <vscale x 2 x i8> %2,3168    <vscale x 2 x i1> %3,3169    iXLen %4, iXLen 1)3170 3171  ret <vscale x 2 x i64> %a3172}3173 3174define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3175; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:3176; CHECK:       # %bb.0: # %entry3177; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3178; CHECK-NEXT:    vmv1r.v v12, v83179; CHECK-NEXT:    vluxei8.v v8, (a0), v123180; CHECK-NEXT:    ret3181entry:3182  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(3183    <vscale x 4 x i64> poison,3184    ptr %0,3185    <vscale x 4 x i8> %1,3186    iXLen %2)3187 3188  ret <vscale x 4 x i64> %a3189}3190 3191define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3192; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i8:3193; CHECK:       # %bb.0: # %entry3194; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3195; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3196; CHECK-NEXT:    ret3197entry:3198  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(3199    <vscale x 4 x i64> %0,3200    ptr %1,3201    <vscale x 4 x i8> %2,3202    <vscale x 4 x i1> %3,3203    iXLen %4, iXLen 1)3204 3205  ret <vscale x 4 x i64> %a3206}3207 3208define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3209; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8:3210; CHECK:       # %bb.0: # %entry3211; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3212; CHECK-NEXT:    vmv1r.v v16, v83213; CHECK-NEXT:    vluxei8.v v8, (a0), v163214; CHECK-NEXT:    ret3215entry:3216  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(3217    <vscale x 8 x i64> poison,3218    ptr %0,3219    <vscale x 8 x i8> %1,3220    iXLen %2)3221 3222  ret <vscale x 8 x i64> %a3223}3224 3225define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3226; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i8:3227; CHECK:       # %bb.0: # %entry3228; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3229; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3230; CHECK-NEXT:    ret3231entry:3232  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(3233    <vscale x 8 x i64> %0,3234    ptr %1,3235    <vscale x 8 x i8> %2,3236    <vscale x 8 x i1> %3,3237    iXLen %4, iXLen 1)3238 3239  ret <vscale x 8 x i64> %a3240}3241 3242define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3243; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:3244; CHECK:       # %bb.0: # %entry3245; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma3246; CHECK-NEXT:    vluxei8.v v9, (a0), v83247; CHECK-NEXT:    vmv1r.v v8, v93248; CHECK-NEXT:    ret3249entry:3250  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(3251    <vscale x 1 x half> poison,3252    ptr %0,3253    <vscale x 1 x i8> %1,3254    iXLen %2)3255 3256  ret <vscale x 1 x half> %a3257}3258 3259define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3260; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i8:3261; CHECK:       # %bb.0: # %entry3262; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu3263; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3264; CHECK-NEXT:    ret3265entry:3266  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(3267    <vscale x 1 x half> %0,3268    ptr %1,3269    <vscale x 1 x i8> %2,3270    <vscale x 1 x i1> %3,3271    iXLen %4, iXLen 1)3272 3273  ret <vscale x 1 x half> %a3274}3275 3276define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3277; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:3278; CHECK:       # %bb.0: # %entry3279; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma3280; CHECK-NEXT:    vluxei8.v v9, (a0), v83281; CHECK-NEXT:    vmv1r.v v8, v93282; CHECK-NEXT:    ret3283entry:3284  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(3285    <vscale x 2 x half> poison,3286    ptr %0,3287    <vscale x 2 x i8> %1,3288    iXLen %2)3289 3290  ret <vscale x 2 x half> %a3291}3292 3293define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3294; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i8:3295; CHECK:       # %bb.0: # %entry3296; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu3297; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3298; CHECK-NEXT:    ret3299entry:3300  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(3301    <vscale x 2 x half> %0,3302    ptr %1,3303    <vscale x 2 x i8> %2,3304    <vscale x 2 x i1> %3,3305    iXLen %4, iXLen 1)3306 3307  ret <vscale x 2 x half> %a3308}3309 3310define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3311; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:3312; CHECK:       # %bb.0: # %entry3313; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma3314; CHECK-NEXT:    vluxei8.v v9, (a0), v83315; CHECK-NEXT:    vmv.v.v v8, v93316; CHECK-NEXT:    ret3317entry:3318  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(3319    <vscale x 4 x half> poison,3320    ptr %0,3321    <vscale x 4 x i8> %1,3322    iXLen %2)3323 3324  ret <vscale x 4 x half> %a3325}3326 3327define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3328; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i8:3329; CHECK:       # %bb.0: # %entry3330; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu3331; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3332; CHECK-NEXT:    ret3333entry:3334  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(3335    <vscale x 4 x half> %0,3336    ptr %1,3337    <vscale x 4 x i8> %2,3338    <vscale x 4 x i1> %3,3339    iXLen %4, iXLen 1)3340 3341  ret <vscale x 4 x half> %a3342}3343 3344define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3345; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:3346; CHECK:       # %bb.0: # %entry3347; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma3348; CHECK-NEXT:    vmv1r.v v10, v83349; CHECK-NEXT:    vluxei8.v v8, (a0), v103350; CHECK-NEXT:    ret3351entry:3352  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(3353    <vscale x 8 x half> poison,3354    ptr %0,3355    <vscale x 8 x i8> %1,3356    iXLen %2)3357 3358  ret <vscale x 8 x half> %a3359}3360 3361define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3362; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i8:3363; CHECK:       # %bb.0: # %entry3364; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu3365; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3366; CHECK-NEXT:    ret3367entry:3368  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(3369    <vscale x 8 x half> %0,3370    ptr %1,3371    <vscale x 8 x i8> %2,3372    <vscale x 8 x i1> %3,3373    iXLen %4, iXLen 1)3374 3375  ret <vscale x 8 x half> %a3376}3377 3378define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3379; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:3380; CHECK:       # %bb.0: # %entry3381; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma3382; CHECK-NEXT:    vmv2r.v v12, v83383; CHECK-NEXT:    vluxei8.v v8, (a0), v123384; CHECK-NEXT:    ret3385entry:3386  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(3387    <vscale x 16 x half> poison,3388    ptr %0,3389    <vscale x 16 x i8> %1,3390    iXLen %2)3391 3392  ret <vscale x 16 x half> %a3393}3394 3395define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3396; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i8:3397; CHECK:       # %bb.0: # %entry3398; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu3399; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3400; CHECK-NEXT:    ret3401entry:3402  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(3403    <vscale x 16 x half> %0,3404    ptr %1,3405    <vscale x 16 x i8> %2,3406    <vscale x 16 x i1> %3,3407    iXLen %4, iXLen 1)3408 3409  ret <vscale x 16 x half> %a3410}3411 3412define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {3413; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:3414; CHECK:       # %bb.0: # %entry3415; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma3416; CHECK-NEXT:    vmv4r.v v16, v83417; CHECK-NEXT:    vluxei8.v v8, (a0), v163418; CHECK-NEXT:    ret3419entry:3420  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(3421    <vscale x 32 x half> poison,3422    ptr %0,3423    <vscale x 32 x i8> %1,3424    iXLen %2)3425 3426  ret <vscale x 32 x half> %a3427}3428 3429define <vscale x 32 x half> @intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {3430; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i8:3431; CHECK:       # %bb.0: # %entry3432; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu3433; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3434; CHECK-NEXT:    ret3435entry:3436  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(3437    <vscale x 32 x half> %0,3438    ptr %1,3439    <vscale x 32 x i8> %2,3440    <vscale x 32 x i1> %3,3441    iXLen %4, iXLen 1)3442 3443  ret <vscale x 32 x half> %a3444}3445 3446define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3447; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:3448; CHECK:       # %bb.0: # %entry3449; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma3450; CHECK-NEXT:    vluxei8.v v9, (a0), v83451; CHECK-NEXT:    vmv1r.v v8, v93452; CHECK-NEXT:    ret3453entry:3454  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(3455    <vscale x 1 x float> poison,3456    ptr %0,3457    <vscale x 1 x i8> %1,3458    iXLen %2)3459 3460  ret <vscale x 1 x float> %a3461}3462 3463define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3464; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i8:3465; CHECK:       # %bb.0: # %entry3466; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu3467; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3468; CHECK-NEXT:    ret3469entry:3470  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(3471    <vscale x 1 x float> %0,3472    ptr %1,3473    <vscale x 1 x i8> %2,3474    <vscale x 1 x i1> %3,3475    iXLen %4, iXLen 1)3476 3477  ret <vscale x 1 x float> %a3478}3479 3480define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3481; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:3482; CHECK:       # %bb.0: # %entry3483; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma3484; CHECK-NEXT:    vluxei8.v v9, (a0), v83485; CHECK-NEXT:    vmv.v.v v8, v93486; CHECK-NEXT:    ret3487entry:3488  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(3489    <vscale x 2 x float> poison,3490    ptr %0,3491    <vscale x 2 x i8> %1,3492    iXLen %2)3493 3494  ret <vscale x 2 x float> %a3495}3496 3497define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3498; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i8:3499; CHECK:       # %bb.0: # %entry3500; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu3501; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3502; CHECK-NEXT:    ret3503entry:3504  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(3505    <vscale x 2 x float> %0,3506    ptr %1,3507    <vscale x 2 x i8> %2,3508    <vscale x 2 x i1> %3,3509    iXLen %4, iXLen 1)3510 3511  ret <vscale x 2 x float> %a3512}3513 3514define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3515; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:3516; CHECK:       # %bb.0: # %entry3517; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3518; CHECK-NEXT:    vmv1r.v v10, v83519; CHECK-NEXT:    vluxei8.v v8, (a0), v103520; CHECK-NEXT:    ret3521entry:3522  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(3523    <vscale x 4 x float> poison,3524    ptr %0,3525    <vscale x 4 x i8> %1,3526    iXLen %2)3527 3528  ret <vscale x 4 x float> %a3529}3530 3531define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3532; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i8:3533; CHECK:       # %bb.0: # %entry3534; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu3535; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3536; CHECK-NEXT:    ret3537entry:3538  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(3539    <vscale x 4 x float> %0,3540    ptr %1,3541    <vscale x 4 x i8> %2,3542    <vscale x 4 x i1> %3,3543    iXLen %4, iXLen 1)3544 3545  ret <vscale x 4 x float> %a3546}3547 3548define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3549; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:3550; CHECK:       # %bb.0: # %entry3551; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma3552; CHECK-NEXT:    vmv1r.v v12, v83553; CHECK-NEXT:    vluxei8.v v8, (a0), v123554; CHECK-NEXT:    ret3555entry:3556  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(3557    <vscale x 8 x float> poison,3558    ptr %0,3559    <vscale x 8 x i8> %1,3560    iXLen %2)3561 3562  ret <vscale x 8 x float> %a3563}3564 3565define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3566; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i8:3567; CHECK:       # %bb.0: # %entry3568; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu3569; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3570; CHECK-NEXT:    ret3571entry:3572  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(3573    <vscale x 8 x float> %0,3574    ptr %1,3575    <vscale x 8 x i8> %2,3576    <vscale x 8 x i1> %3,3577    iXLen %4, iXLen 1)3578 3579  ret <vscale x 8 x float> %a3580}3581 3582define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3583; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:3584; CHECK:       # %bb.0: # %entry3585; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma3586; CHECK-NEXT:    vmv2r.v v16, v83587; CHECK-NEXT:    vluxei8.v v8, (a0), v163588; CHECK-NEXT:    ret3589entry:3590  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(3591    <vscale x 16 x float> poison,3592    ptr %0,3593    <vscale x 16 x i8> %1,3594    iXLen %2)3595 3596  ret <vscale x 16 x float> %a3597}3598 3599define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3600; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i8:3601; CHECK:       # %bb.0: # %entry3602; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu3603; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3604; CHECK-NEXT:    ret3605entry:3606  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(3607    <vscale x 16 x float> %0,3608    ptr %1,3609    <vscale x 16 x i8> %2,3610    <vscale x 16 x i1> %3,3611    iXLen %4, iXLen 1)3612 3613  ret <vscale x 16 x float> %a3614}3615 3616define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3617; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:3618; CHECK:       # %bb.0: # %entry3619; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma3620; CHECK-NEXT:    vluxei8.v v9, (a0), v83621; CHECK-NEXT:    vmv.v.v v8, v93622; CHECK-NEXT:    ret3623entry:3624  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(3625    <vscale x 1 x double> poison,3626    ptr %0,3627    <vscale x 1 x i8> %1,3628    iXLen %2)3629 3630  ret <vscale x 1 x double> %a3631}3632 3633define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3634; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i8:3635; CHECK:       # %bb.0: # %entry3636; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu3637; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3638; CHECK-NEXT:    ret3639entry:3640  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(3641    <vscale x 1 x double> %0,3642    ptr %1,3643    <vscale x 1 x i8> %2,3644    <vscale x 1 x i1> %3,3645    iXLen %4, iXLen 1)3646 3647  ret <vscale x 1 x double> %a3648}3649 3650define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3651; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:3652; CHECK:       # %bb.0: # %entry3653; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3654; CHECK-NEXT:    vmv1r.v v10, v83655; CHECK-NEXT:    vluxei8.v v8, (a0), v103656; CHECK-NEXT:    ret3657entry:3658  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(3659    <vscale x 2 x double> poison,3660    ptr %0,3661    <vscale x 2 x i8> %1,3662    iXLen %2)3663 3664  ret <vscale x 2 x double> %a3665}3666 3667define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3668; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i8:3669; CHECK:       # %bb.0: # %entry3670; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu3671; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3672; CHECK-NEXT:    ret3673entry:3674  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(3675    <vscale x 2 x double> %0,3676    ptr %1,3677    <vscale x 2 x i8> %2,3678    <vscale x 2 x i1> %3,3679    iXLen %4, iXLen 1)3680 3681  ret <vscale x 2 x double> %a3682}3683 3684define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3685; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:3686; CHECK:       # %bb.0: # %entry3687; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3688; CHECK-NEXT:    vmv1r.v v12, v83689; CHECK-NEXT:    vluxei8.v v8, (a0), v123690; CHECK-NEXT:    ret3691entry:3692  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(3693    <vscale x 4 x double> poison,3694    ptr %0,3695    <vscale x 4 x i8> %1,3696    iXLen %2)3697 3698  ret <vscale x 4 x double> %a3699}3700 3701define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3702; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i8:3703; CHECK:       # %bb.0: # %entry3704; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3705; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3706; CHECK-NEXT:    ret3707entry:3708  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(3709    <vscale x 4 x double> %0,3710    ptr %1,3711    <vscale x 4 x i8> %2,3712    <vscale x 4 x i1> %3,3713    iXLen %4, iXLen 1)3714 3715  ret <vscale x 4 x double> %a3716}3717 3718define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3719; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:3720; CHECK:       # %bb.0: # %entry3721; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3722; CHECK-NEXT:    vmv1r.v v16, v83723; CHECK-NEXT:    vluxei8.v v8, (a0), v163724; CHECK-NEXT:    ret3725entry:3726  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(3727    <vscale x 8 x double> poison,3728    ptr %0,3729    <vscale x 8 x i8> %1,3730    iXLen %2)3731 3732  ret <vscale x 8 x double> %a3733}3734 3735define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3736; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i8:3737; CHECK:       # %bb.0: # %entry3738; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3739; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3740; CHECK-NEXT:    ret3741entry:3742  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(3743    <vscale x 8 x double> %0,3744    ptr %1,3745    <vscale x 8 x i8> %2,3746    <vscale x 8 x i1> %3,3747    iXLen %4, iXLen 1)3748 3749  ret <vscale x 8 x double> %a3750}3751