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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma11; CHECK-NEXT: vmacc.vv v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8(15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 <vscale x 1 x i8> %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu27; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(31 <vscale x 1 x i8> %0,32 <vscale x 1 x i8> %1,33 <vscale x 1 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 0)36 37 ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma44; CHECK-NEXT: vmacc.vv v8, v9, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(48 <vscale x 2 x i8> %0,49 <vscale x 2 x i8> %1,50 <vscale x 2 x i8> %2,51 iXLen %3, iXLen 0)52 53 ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu60; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(64 <vscale x 2 x i8> %0,65 <vscale x 2 x i8> %1,66 <vscale x 2 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 0)69 70 ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma77; CHECK-NEXT: vmacc.vv v8, v9, v1078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(81 <vscale x 4 x i8> %0,82 <vscale x 4 x i8> %1,83 <vscale x 4 x i8> %2,84 iXLen %3, iXLen 0)85 86 ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu93; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(97 <vscale x 4 x i8> %0,98 <vscale x 4 x i8> %1,99 <vscale x 4 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 0)102 103 ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma110; CHECK-NEXT: vmacc.vv v8, v9, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(114 <vscale x 8 x i8> %0,115 <vscale x 8 x i8> %1,116 <vscale x 8 x i8> %2,117 iXLen %3, iXLen 0)118 119 ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu126; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(130 <vscale x 8 x i8> %0,131 <vscale x 8 x i8> %1,132 <vscale x 8 x i8> %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 0)135 136 ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma143; CHECK-NEXT: vmacc.vv v8, v10, v12144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(147 <vscale x 16 x i8> %0,148 <vscale x 16 x i8> %1,149 <vscale x 16 x i8> %2,150 iXLen %3, iXLen 0)151 152 ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu159; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(163 <vscale x 16 x i8> %0,164 <vscale x 16 x i8> %1,165 <vscale x 16 x i8> %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 0)168 169 ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {173; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma176; CHECK-NEXT: vmacc.vv v8, v12, v16177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(180 <vscale x 32 x i8> %0,181 <vscale x 32 x i8> %1,182 <vscale x 32 x i8> %2,183 iXLen %3, iXLen 0)184 185 ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu192; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(196 <vscale x 32 x i8> %0,197 <vscale x 32 x i8> %1,198 <vscale x 32 x i8> %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 0)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 1 x i16> @intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma209; CHECK-NEXT: vmacc.vv v8, v9, v10210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(213 <vscale x 1 x i16> %0,214 <vscale x 1 x i16> %1,215 <vscale x 1 x i16> %2,216 iXLen %3, iXLen 0)217 218 ret <vscale x 1 x i16> %a219}220 221define <vscale x 1 x i16> @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu225; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(229 <vscale x 1 x i16> %0,230 <vscale x 1 x i16> %1,231 <vscale x 1 x i16> %2,232 <vscale x 1 x i1> %3,233 iXLen %4, iXLen 0)234 235 ret <vscale x 1 x i16> %a236}237 238define <vscale x 2 x i16> @intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma242; CHECK-NEXT: vmacc.vv v8, v9, v10243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(246 <vscale x 2 x i16> %0,247 <vscale x 2 x i16> %1,248 <vscale x 2 x i16> %2,249 iXLen %3, iXLen 0)250 251 ret <vscale x 2 x i16> %a252}253 254define <vscale x 2 x i16> @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu258; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(262 <vscale x 2 x i16> %0,263 <vscale x 2 x i16> %1,264 <vscale x 2 x i16> %2,265 <vscale x 2 x i1> %3,266 iXLen %4, iXLen 0)267 268 ret <vscale x 2 x i16> %a269}270 271define <vscale x 4 x i16> @intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma275; CHECK-NEXT: vmacc.vv v8, v9, v10276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(279 <vscale x 4 x i16> %0,280 <vscale x 4 x i16> %1,281 <vscale x 4 x i16> %2,282 iXLen %3, iXLen 0)283 284 ret <vscale x 4 x i16> %a285}286 287define <vscale x 4 x i16> @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu291; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(295 <vscale x 4 x i16> %0,296 <vscale x 4 x i16> %1,297 <vscale x 4 x i16> %2,298 <vscale x 4 x i1> %3,299 iXLen %4, iXLen 0)300 301 ret <vscale x 4 x i16> %a302}303 304define <vscale x 8 x i16> @intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma308; CHECK-NEXT: vmacc.vv v8, v10, v12309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(312 <vscale x 8 x i16> %0,313 <vscale x 8 x i16> %1,314 <vscale x 8 x i16> %2,315 iXLen %3, iXLen 0)316 317 ret <vscale x 8 x i16> %a318}319 320define <vscale x 8 x i16> @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu324; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(328 <vscale x 8 x i16> %0,329 <vscale x 8 x i16> %1,330 <vscale x 8 x i16> %2,331 <vscale x 8 x i1> %3,332 iXLen %4, iXLen 0)333 334 ret <vscale x 8 x i16> %a335}336 337define <vscale x 16 x i16> @intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {338; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma341; CHECK-NEXT: vmacc.vv v8, v12, v16342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(345 <vscale x 16 x i16> %0,346 <vscale x 16 x i16> %1,347 <vscale x 16 x i16> %2,348 iXLen %3, iXLen 0)349 350 ret <vscale x 16 x i16> %a351}352 353define <vscale x 16 x i16> @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu357; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(361 <vscale x 16 x i16> %0,362 <vscale x 16 x i16> %1,363 <vscale x 16 x i16> %2,364 <vscale x 16 x i1> %3,365 iXLen %4, iXLen 0)366 367 ret <vscale x 16 x i16> %a368}369 370define <vscale x 1 x i32> @intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {371; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma374; CHECK-NEXT: vmacc.vv v8, v9, v10375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(378 <vscale x 1 x i32> %0,379 <vscale x 1 x i32> %1,380 <vscale x 1 x i32> %2,381 iXLen %3, iXLen 0)382 383 ret <vscale x 1 x i32> %a384}385 386define <vscale x 1 x i32> @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu390; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(394 <vscale x 1 x i32> %0,395 <vscale x 1 x i32> %1,396 <vscale x 1 x i32> %2,397 <vscale x 1 x i1> %3,398 iXLen %4, iXLen 0)399 400 ret <vscale x 1 x i32> %a401}402 403define <vscale x 2 x i32> @intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {404; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma407; CHECK-NEXT: vmacc.vv v8, v9, v10408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(411 <vscale x 2 x i32> %0,412 <vscale x 2 x i32> %1,413 <vscale x 2 x i32> %2,414 iXLen %3, iXLen 0)415 416 ret <vscale x 2 x i32> %a417}418 419define <vscale x 2 x i32> @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu423; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(427 <vscale x 2 x i32> %0,428 <vscale x 2 x i32> %1,429 <vscale x 2 x i32> %2,430 <vscale x 2 x i1> %3,431 iXLen %4, iXLen 0)432 433 ret <vscale x 2 x i32> %a434}435 436define <vscale x 4 x i32> @intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {437; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma440; CHECK-NEXT: vmacc.vv v8, v10, v12441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(444 <vscale x 4 x i32> %0,445 <vscale x 4 x i32> %1,446 <vscale x 4 x i32> %2,447 iXLen %3, iXLen 0)448 449 ret <vscale x 4 x i32> %a450}451 452define <vscale x 4 x i32> @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu456; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(460 <vscale x 4 x i32> %0,461 <vscale x 4 x i32> %1,462 <vscale x 4 x i32> %2,463 <vscale x 4 x i1> %3,464 iXLen %4, iXLen 0)465 466 ret <vscale x 4 x i32> %a467}468 469define <vscale x 8 x i32> @intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {470; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma473; CHECK-NEXT: vmacc.vv v8, v12, v16474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(477 <vscale x 8 x i32> %0,478 <vscale x 8 x i32> %1,479 <vscale x 8 x i32> %2,480 iXLen %3, iXLen 0)481 482 ret <vscale x 8 x i32> %a483}484 485define <vscale x 8 x i32> @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu489; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(493 <vscale x 8 x i32> %0,494 <vscale x 8 x i32> %1,495 <vscale x 8 x i32> %2,496 <vscale x 8 x i1> %3,497 iXLen %4, iXLen 0)498 499 ret <vscale x 8 x i32> %a500}501 502define <vscale x 1 x i64> @intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {503; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma506; CHECK-NEXT: vmacc.vv v8, v9, v10507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64(510 <vscale x 1 x i64> %0,511 <vscale x 1 x i64> %1,512 <vscale x 1 x i64> %2,513 iXLen %3, iXLen 0)514 515 ret <vscale x 1 x i64> %a516}517 518define <vscale x 1 x i64> @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu522; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(526 <vscale x 1 x i64> %0,527 <vscale x 1 x i64> %1,528 <vscale x 1 x i64> %2,529 <vscale x 1 x i1> %3,530 iXLen %4, iXLen 0)531 532 ret <vscale x 1 x i64> %a533}534 535define <vscale x 2 x i64> @intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, iXLen %3) nounwind {536; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma539; CHECK-NEXT: vmacc.vv v8, v10, v12540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64(543 <vscale x 2 x i64> %0,544 <vscale x 2 x i64> %1,545 <vscale x 2 x i64> %2,546 iXLen %3, iXLen 0)547 548 ret <vscale x 2 x i64> %a549}550 551define <vscale x 2 x i64> @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu555; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(559 <vscale x 2 x i64> %0,560 <vscale x 2 x i64> %1,561 <vscale x 2 x i64> %2,562 <vscale x 2 x i1> %3,563 iXLen %4, iXLen 0)564 565 ret <vscale x 2 x i64> %a566}567 568define <vscale x 4 x i64> @intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, iXLen %3) nounwind {569; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma572; CHECK-NEXT: vmacc.vv v8, v12, v16573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64(576 <vscale x 4 x i64> %0,577 <vscale x 4 x i64> %1,578 <vscale x 4 x i64> %2,579 iXLen %3, iXLen 0)580 581 ret <vscale x 4 x i64> %a582}583 584define <vscale x 4 x i64> @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu588; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(592 <vscale x 4 x i64> %0,593 <vscale x 4 x i64> %1,594 <vscale x 4 x i64> %2,595 <vscale x 4 x i1> %3,596 iXLen %4, iXLen 0)597 598 ret <vscale x 4 x i64> %a599}600 601define <vscale x 1 x i8> @intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {602; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma605; CHECK-NEXT: vmacc.vx v8, a0, v9606; CHECK-NEXT: ret607entry:608 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(609 <vscale x 1 x i8> %0,610 i8 %1,611 <vscale x 1 x i8> %2,612 iXLen %3, iXLen 0)613 614 ret <vscale x 1 x i8> %a615}616 617define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {618; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu621; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t622; CHECK-NEXT: ret623entry:624 %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(625 <vscale x 1 x i8> %0,626 i8 %1,627 <vscale x 1 x i8> %2,628 <vscale x 1 x i1> %3,629 iXLen %4, iXLen 0)630 631 ret <vscale x 1 x i8> %a632}633 634define <vscale x 2 x i8> @intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {635; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma638; CHECK-NEXT: vmacc.vx v8, a0, v9639; CHECK-NEXT: ret640entry:641 %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(642 <vscale x 2 x i8> %0,643 i8 %1,644 <vscale x 2 x i8> %2,645 iXLen %3, iXLen 0)646 647 ret <vscale x 2 x i8> %a648}649 650define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {651; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu654; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(658 <vscale x 2 x i8> %0,659 i8 %1,660 <vscale x 2 x i8> %2,661 <vscale x 2 x i1> %3,662 iXLen %4, iXLen 0)663 664 ret <vscale x 2 x i8> %a665}666 667define <vscale x 4 x i8> @intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {668; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma671; CHECK-NEXT: vmacc.vx v8, a0, v9672; CHECK-NEXT: ret673entry:674 %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(675 <vscale x 4 x i8> %0,676 i8 %1,677 <vscale x 4 x i8> %2,678 iXLen %3, iXLen 0)679 680 ret <vscale x 4 x i8> %a681}682 683define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {684; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu687; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t688; CHECK-NEXT: ret689entry:690 %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(691 <vscale x 4 x i8> %0,692 i8 %1,693 <vscale x 4 x i8> %2,694 <vscale x 4 x i1> %3,695 iXLen %4, iXLen 0)696 697 ret <vscale x 4 x i8> %a698}699 700define <vscale x 8 x i8> @intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {701; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma704; CHECK-NEXT: vmacc.vx v8, a0, v9705; CHECK-NEXT: ret706entry:707 %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(708 <vscale x 8 x i8> %0,709 i8 %1,710 <vscale x 8 x i8> %2,711 iXLen %3, iXLen 0)712 713 ret <vscale x 8 x i8> %a714}715 716define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {717; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8:718; CHECK: # %bb.0: # %entry719; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu720; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t721; CHECK-NEXT: ret722entry:723 %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(724 <vscale x 8 x i8> %0,725 i8 %1,726 <vscale x 8 x i8> %2,727 <vscale x 8 x i1> %3,728 iXLen %4, iXLen 0)729 730 ret <vscale x 8 x i8> %a731}732 733define <vscale x 16 x i8> @intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {734; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma737; CHECK-NEXT: vmacc.vx v8, a0, v10738; CHECK-NEXT: ret739entry:740 %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(741 <vscale x 16 x i8> %0,742 i8 %1,743 <vscale x 16 x i8> %2,744 iXLen %3, iXLen 0)745 746 ret <vscale x 16 x i8> %a747}748 749define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {750; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu753; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t754; CHECK-NEXT: ret755entry:756 %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(757 <vscale x 16 x i8> %0,758 i8 %1,759 <vscale x 16 x i8> %2,760 <vscale x 16 x i1> %3,761 iXLen %4, iXLen 0)762 763 ret <vscale x 16 x i8> %a764}765 766define <vscale x 32 x i8> @intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {767; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma770; CHECK-NEXT: vmacc.vx v8, a0, v12771; CHECK-NEXT: ret772entry:773 %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(774 <vscale x 32 x i8> %0,775 i8 %1,776 <vscale x 32 x i8> %2,777 iXLen %3, iXLen 0)778 779 ret <vscale x 32 x i8> %a780}781 782define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {783; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu786; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t787; CHECK-NEXT: ret788entry:789 %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(790 <vscale x 32 x i8> %0,791 i8 %1,792 <vscale x 32 x i8> %2,793 <vscale x 32 x i1> %3,794 iXLen %4, iXLen 0)795 796 ret <vscale x 32 x i8> %a797}798 799define <vscale x 1 x i16> @intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {800; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma803; CHECK-NEXT: vmacc.vx v8, a0, v9804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(807 <vscale x 1 x i16> %0,808 i16 %1,809 <vscale x 1 x i16> %2,810 iXLen %3, iXLen 0)811 812 ret <vscale x 1 x i16> %a813}814 815define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {816; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu819; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t820; CHECK-NEXT: ret821entry:822 %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(823 <vscale x 1 x i16> %0,824 i16 %1,825 <vscale x 1 x i16> %2,826 <vscale x 1 x i1> %3,827 iXLen %4, iXLen 0)828 829 ret <vscale x 1 x i16> %a830}831 832define <vscale x 2 x i16> @intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {833; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma836; CHECK-NEXT: vmacc.vx v8, a0, v9837; CHECK-NEXT: ret838entry:839 %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(840 <vscale x 2 x i16> %0,841 i16 %1,842 <vscale x 2 x i16> %2,843 iXLen %3, iXLen 0)844 845 ret <vscale x 2 x i16> %a846}847 848define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {849; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16:850; CHECK: # %bb.0: # %entry851; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu852; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t853; CHECK-NEXT: ret854entry:855 %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(856 <vscale x 2 x i16> %0,857 i16 %1,858 <vscale x 2 x i16> %2,859 <vscale x 2 x i1> %3,860 iXLen %4, iXLen 0)861 862 ret <vscale x 2 x i16> %a863}864 865define <vscale x 4 x i16> @intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {866; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma869; CHECK-NEXT: vmacc.vx v8, a0, v9870; CHECK-NEXT: ret871entry:872 %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(873 <vscale x 4 x i16> %0,874 i16 %1,875 <vscale x 4 x i16> %2,876 iXLen %3, iXLen 0)877 878 ret <vscale x 4 x i16> %a879}880 881define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {882; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16:883; CHECK: # %bb.0: # %entry884; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu885; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t886; CHECK-NEXT: ret887entry:888 %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(889 <vscale x 4 x i16> %0,890 i16 %1,891 <vscale x 4 x i16> %2,892 <vscale x 4 x i1> %3,893 iXLen %4, iXLen 0)894 895 ret <vscale x 4 x i16> %a896}897 898define <vscale x 8 x i16> @intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {899; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma902; CHECK-NEXT: vmacc.vx v8, a0, v10903; CHECK-NEXT: ret904entry:905 %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(906 <vscale x 8 x i16> %0,907 i16 %1,908 <vscale x 8 x i16> %2,909 iXLen %3, iXLen 0)910 911 ret <vscale x 8 x i16> %a912}913 914define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {915; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu918; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t919; CHECK-NEXT: ret920entry:921 %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(922 <vscale x 8 x i16> %0,923 i16 %1,924 <vscale x 8 x i16> %2,925 <vscale x 8 x i1> %3,926 iXLen %4, iXLen 0)927 928 ret <vscale x 8 x i16> %a929}930 931define <vscale x 16 x i16> @intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {932; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma935; CHECK-NEXT: vmacc.vx v8, a0, v12936; CHECK-NEXT: ret937entry:938 %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(939 <vscale x 16 x i16> %0,940 i16 %1,941 <vscale x 16 x i16> %2,942 iXLen %3, iXLen 0)943 944 ret <vscale x 16 x i16> %a945}946 947define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {948; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu951; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t952; CHECK-NEXT: ret953entry:954 %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(955 <vscale x 16 x i16> %0,956 i16 %1,957 <vscale x 16 x i16> %2,958 <vscale x 16 x i1> %3,959 iXLen %4, iXLen 0)960 961 ret <vscale x 16 x i16> %a962}963 964define <vscale x 1 x i32> @intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {965; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma968; CHECK-NEXT: vmacc.vx v8, a0, v9969; CHECK-NEXT: ret970entry:971 %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(972 <vscale x 1 x i32> %0,973 i32 %1,974 <vscale x 1 x i32> %2,975 iXLen %3, iXLen 0)976 977 ret <vscale x 1 x i32> %a978}979 980define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {981; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32:982; CHECK: # %bb.0: # %entry983; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu984; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t985; CHECK-NEXT: ret986entry:987 %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(988 <vscale x 1 x i32> %0,989 i32 %1,990 <vscale x 1 x i32> %2,991 <vscale x 1 x i1> %3,992 iXLen %4, iXLen 0)993 994 ret <vscale x 1 x i32> %a995}996 997define <vscale x 2 x i32> @intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {998; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma1001; CHECK-NEXT: vmacc.vx v8, a0, v91002; CHECK-NEXT: ret1003entry:1004 %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(1005 <vscale x 2 x i32> %0,1006 i32 %1,1007 <vscale x 2 x i32> %2,1008 iXLen %3, iXLen 0)1009 1010 ret <vscale x 2 x i32> %a1011}1012 1013define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1014; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32:1015; CHECK: # %bb.0: # %entry1016; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu1017; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t1018; CHECK-NEXT: ret1019entry:1020 %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(1021 <vscale x 2 x i32> %0,1022 i32 %1,1023 <vscale x 2 x i32> %2,1024 <vscale x 2 x i1> %3,1025 iXLen %4, iXLen 0)1026 1027 ret <vscale x 2 x i32> %a1028}1029 1030define <vscale x 4 x i32> @intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {1031; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma1034; CHECK-NEXT: vmacc.vx v8, a0, v101035; CHECK-NEXT: ret1036entry:1037 %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(1038 <vscale x 4 x i32> %0,1039 i32 %1,1040 <vscale x 4 x i32> %2,1041 iXLen %3, iXLen 0)1042 1043 ret <vscale x 4 x i32> %a1044}1045 1046define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1047; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu1050; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t1051; CHECK-NEXT: ret1052entry:1053 %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(1054 <vscale x 4 x i32> %0,1055 i32 %1,1056 <vscale x 4 x i32> %2,1057 <vscale x 4 x i1> %3,1058 iXLen %4, iXLen 0)1059 1060 ret <vscale x 4 x i32> %a1061}1062 1063define <vscale x 8 x i32> @intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {1064; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32:1065; CHECK: # %bb.0: # %entry1066; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma1067; CHECK-NEXT: vmacc.vx v8, a0, v121068; CHECK-NEXT: ret1069entry:1070 %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(1071 <vscale x 8 x i32> %0,1072 i32 %1,1073 <vscale x 8 x i32> %2,1074 iXLen %3, iXLen 0)1075 1076 ret <vscale x 8 x i32> %a1077}1078 1079define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1080; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32:1081; CHECK: # %bb.0: # %entry1082; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu1083; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t1084; CHECK-NEXT: ret1085entry:1086 %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(1087 <vscale x 8 x i32> %0,1088 i32 %1,1089 <vscale x 8 x i32> %2,1090 <vscale x 8 x i1> %3,1091 iXLen %4, iXLen 0)1092 1093 ret <vscale x 8 x i32> %a1094}1095 1096define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {1097; RV32-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:1098; RV32: # %bb.0: # %entry1099; RV32-NEXT: addi sp, sp, -161100; RV32-NEXT: sw a0, 8(sp)1101; RV32-NEXT: sw a1, 12(sp)1102; RV32-NEXT: addi a0, sp, 81103; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1104; RV32-NEXT: vlse64.v v10, (a0), zero1105; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma1106; RV32-NEXT: vmacc.vv v8, v10, v91107; RV32-NEXT: addi sp, sp, 161108; RV32-NEXT: ret1109;1110; RV64-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:1111; RV64: # %bb.0: # %entry1112; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma1113; RV64-NEXT: vmacc.vx v8, a0, v91114; RV64-NEXT: ret1115entry:1116 %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(1117 <vscale x 1 x i64> %0,1118 i64 %1,1119 <vscale x 1 x i64> %2,1120 iXLen %3, iXLen 0)1121 1122 ret <vscale x 1 x i64> %a1123}1124 1125define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1126; RV32-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64:1127; RV32: # %bb.0: # %entry1128; RV32-NEXT: addi sp, sp, -161129; RV32-NEXT: sw a0, 8(sp)1130; RV32-NEXT: sw a1, 12(sp)1131; RV32-NEXT: addi a0, sp, 81132; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1133; RV32-NEXT: vlse64.v v10, (a0), zero1134; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu1135; RV32-NEXT: vmacc.vv v8, v10, v9, v0.t1136; RV32-NEXT: addi sp, sp, 161137; RV32-NEXT: ret1138;1139; RV64-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64:1140; RV64: # %bb.0: # %entry1141; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu1142; RV64-NEXT: vmacc.vx v8, a0, v9, v0.t1143; RV64-NEXT: ret1144entry:1145 %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(1146 <vscale x 1 x i64> %0,1147 i64 %1,1148 <vscale x 1 x i64> %2,1149 <vscale x 1 x i1> %3,1150 iXLen %4, iXLen 0)1151 1152 ret <vscale x 1 x i64> %a1153}1154 1155define <vscale x 2 x i64> @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, iXLen %3) nounwind {1156; RV32-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64:1157; RV32: # %bb.0: # %entry1158; RV32-NEXT: addi sp, sp, -161159; RV32-NEXT: sw a0, 8(sp)1160; RV32-NEXT: sw a1, 12(sp)1161; RV32-NEXT: addi a0, sp, 81162; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1163; RV32-NEXT: vlse64.v v12, (a0), zero1164; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, ma1165; RV32-NEXT: vmacc.vv v8, v12, v101166; RV32-NEXT: addi sp, sp, 161167; RV32-NEXT: ret1168;1169; RV64-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64:1170; RV64: # %bb.0: # %entry1171; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, ma1172; RV64-NEXT: vmacc.vx v8, a0, v101173; RV64-NEXT: ret1174entry:1175 %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(1176 <vscale x 2 x i64> %0,1177 i64 %1,1178 <vscale x 2 x i64> %2,1179 iXLen %3, iXLen 0)1180 1181 ret <vscale x 2 x i64> %a1182}1183 1184define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1185; RV32-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64:1186; RV32: # %bb.0: # %entry1187; RV32-NEXT: addi sp, sp, -161188; RV32-NEXT: sw a0, 8(sp)1189; RV32-NEXT: sw a1, 12(sp)1190; RV32-NEXT: addi a0, sp, 81191; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1192; RV32-NEXT: vlse64.v v12, (a0), zero1193; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu1194; RV32-NEXT: vmacc.vv v8, v12, v10, v0.t1195; RV32-NEXT: addi sp, sp, 161196; RV32-NEXT: ret1197;1198; RV64-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64:1199; RV64: # %bb.0: # %entry1200; RV64-NEXT: vsetvli zero, a1, e64, m2, tu, mu1201; RV64-NEXT: vmacc.vx v8, a0, v10, v0.t1202; RV64-NEXT: ret1203entry:1204 %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(1205 <vscale x 2 x i64> %0,1206 i64 %1,1207 <vscale x 2 x i64> %2,1208 <vscale x 2 x i1> %3,1209 iXLen %4, iXLen 0)1210 1211 ret <vscale x 2 x i64> %a1212}1213 1214define <vscale x 4 x i64> @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, iXLen %3) nounwind {1215; RV32-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64:1216; RV32: # %bb.0: # %entry1217; RV32-NEXT: addi sp, sp, -161218; RV32-NEXT: sw a0, 8(sp)1219; RV32-NEXT: sw a1, 12(sp)1220; RV32-NEXT: addi a0, sp, 81221; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1222; RV32-NEXT: vlse64.v v16, (a0), zero1223; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, ma1224; RV32-NEXT: vmacc.vv v8, v16, v121225; RV32-NEXT: addi sp, sp, 161226; RV32-NEXT: ret1227;1228; RV64-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64:1229; RV64: # %bb.0: # %entry1230; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, ma1231; RV64-NEXT: vmacc.vx v8, a0, v121232; RV64-NEXT: ret1233entry:1234 %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(1235 <vscale x 4 x i64> %0,1236 i64 %1,1237 <vscale x 4 x i64> %2,1238 iXLen %3, iXLen 0)1239 1240 ret <vscale x 4 x i64> %a1241}1242 1243define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1244; RV32-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64:1245; RV32: # %bb.0: # %entry1246; RV32-NEXT: addi sp, sp, -161247; RV32-NEXT: sw a0, 8(sp)1248; RV32-NEXT: sw a1, 12(sp)1249; RV32-NEXT: addi a0, sp, 81250; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1251; RV32-NEXT: vlse64.v v16, (a0), zero1252; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, mu1253; RV32-NEXT: vmacc.vv v8, v16, v12, v0.t1254; RV32-NEXT: addi sp, sp, 161255; RV32-NEXT: ret1256;1257; RV64-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64:1258; RV64: # %bb.0: # %entry1259; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, mu1260; RV64-NEXT: vmacc.vx v8, a0, v12, v0.t1261; RV64-NEXT: ret1262entry:1263 %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(1264 <vscale x 4 x i64> %0,1265 i64 %1,1266 <vscale x 4 x i64> %2,1267 <vscale x 4 x i1> %3,1268 iXLen %4, iXLen 0)1269 1270 ret <vscale x 4 x i64> %a1271}1272