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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7; This tests a mix of vmacc and vmadd by using different operand orders to8; trigger commuting in TwoAddressInstructionPass.9 10define <vscale x 1 x i8> @vmadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i8> %vc) {11; CHECK-LABEL: vmadd_vv_nxv1i8:12; CHECK: # %bb.0:13; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma14; CHECK-NEXT: vmadd.vv v8, v9, v1015; CHECK-NEXT: ret16 %x = mul <vscale x 1 x i8> %va, %vb17 %y = add <vscale x 1 x i8> %x, %vc18 ret <vscale x 1 x i8> %y19}20 21define <vscale x 1 x i8> @vmadd_vx_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, i8 %c) {22; CHECK-LABEL: vmadd_vx_nxv1i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma25; CHECK-NEXT: vmadd.vx v8, a0, v926; CHECK-NEXT: ret27 %head = insertelement <vscale x 1 x i8> poison, i8 %c, i32 028 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer29 %x = mul <vscale x 1 x i8> %va, %splat30 %y = add <vscale x 1 x i8> %x, %vb31 ret <vscale x 1 x i8> %y32}33 34define <vscale x 2 x i8> @vmadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i8> %vc) {35; CHECK-LABEL: vmadd_vv_nxv2i8:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma38; CHECK-NEXT: vmadd.vv v8, v10, v939; CHECK-NEXT: ret40 %x = mul <vscale x 2 x i8> %va, %vc41 %y = add <vscale x 2 x i8> %x, %vb42 ret <vscale x 2 x i8> %y43}44 45define <vscale x 2 x i8> @vmadd_vx_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, i8 %c) {46; CHECK-LABEL: vmadd_vx_nxv2i8:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma49; CHECK-NEXT: vmacc.vx v8, a0, v950; CHECK-NEXT: ret51 %head = insertelement <vscale x 2 x i8> poison, i8 %c, i32 052 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer53 %x = mul <vscale x 2 x i8> %vb, %splat54 %y = add <vscale x 2 x i8> %x, %va55 ret <vscale x 2 x i8> %y56}57 58define <vscale x 4 x i8> @vmadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i8> %vc) {59; CHECK-LABEL: vmadd_vv_nxv4i8:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma62; CHECK-NEXT: vmadd.vv v8, v9, v1063; CHECK-NEXT: ret64 %x = mul <vscale x 4 x i8> %vb, %va65 %y = add <vscale x 4 x i8> %x, %vc66 ret <vscale x 4 x i8> %y67}68 69define <vscale x 4 x i8> @vmadd_vx_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, i8 %c) {70; CHECK-LABEL: vmadd_vx_nxv4i8:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma73; CHECK-NEXT: vmadd.vx v8, a0, v974; CHECK-NEXT: ret75 %head = insertelement <vscale x 4 x i8> poison, i8 %c, i32 076 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer77 %x = mul <vscale x 4 x i8> %va, %splat78 %y = add <vscale x 4 x i8> %x, %vb79 ret <vscale x 4 x i8> %y80}81 82define <vscale x 8 x i8> @vmadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i8> %vc) {83; CHECK-LABEL: vmadd_vv_nxv8i8:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma86; CHECK-NEXT: vmacc.vv v8, v10, v987; CHECK-NEXT: ret88 %x = mul <vscale x 8 x i8> %vb, %vc89 %y = add <vscale x 8 x i8> %x, %va90 ret <vscale x 8 x i8> %y91}92 93define <vscale x 8 x i8> @vmadd_vx_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i8 %c) {94; CHECK-LABEL: vmadd_vx_nxv8i8:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma97; CHECK-NEXT: vmacc.vx v8, a0, v998; CHECK-NEXT: ret99 %head = insertelement <vscale x 8 x i8> poison, i8 %c, i32 0100 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer101 %x = mul <vscale x 8 x i8> %vb, %splat102 %y = add <vscale x 8 x i8> %x, %va103 ret <vscale x 8 x i8> %y104}105 106define <vscale x 16 x i8> @vmadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i8> %vc) {107; CHECK-LABEL: vmadd_vv_nxv16i8:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma110; CHECK-NEXT: vmadd.vv v8, v12, v10111; CHECK-NEXT: ret112 %x = mul <vscale x 16 x i8> %vc, %va113 %y = add <vscale x 16 x i8> %x, %vb114 ret <vscale x 16 x i8> %y115}116 117define <vscale x 16 x i8> @vmadd_vx_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, i8 %c) {118; CHECK-LABEL: vmadd_vx_nxv16i8:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma121; CHECK-NEXT: vmadd.vx v8, a0, v10122; CHECK-NEXT: ret123 %head = insertelement <vscale x 16 x i8> poison, i8 %c, i32 0124 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer125 %x = mul <vscale x 16 x i8> %va, %splat126 %y = add <vscale x 16 x i8> %x, %vb127 ret <vscale x 16 x i8> %y128}129 130define <vscale x 32 x i8> @vmadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i8> %vc) {131; CHECK-LABEL: vmadd_vv_nxv32i8:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma134; CHECK-NEXT: vmacc.vv v8, v16, v12135; CHECK-NEXT: ret136 %x = mul <vscale x 32 x i8> %vc, %vb137 %y = add <vscale x 32 x i8> %x, %va138 ret <vscale x 32 x i8> %y139}140 141define <vscale x 32 x i8> @vmadd_vx_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, i8 %c) {142; CHECK-LABEL: vmadd_vx_nxv32i8:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma145; CHECK-NEXT: vmacc.vx v8, a0, v12146; CHECK-NEXT: ret147 %head = insertelement <vscale x 32 x i8> poison, i8 %c, i32 0148 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer149 %x = mul <vscale x 32 x i8> %vb, %splat150 %y = add <vscale x 32 x i8> %x, %va151 ret <vscale x 32 x i8> %y152}153 154define <vscale x 64 x i8> @vmadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i8> %vc) {155; CHECK-LABEL: vmadd_vv_nxv64i8:156; CHECK: # %bb.0:157; CHECK-NEXT: vl8r.v v24, (a0)158; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma159; CHECK-NEXT: vmacc.vv v8, v16, v24160; CHECK-NEXT: ret161 %x = mul <vscale x 64 x i8> %vc, %vb162 %y = add <vscale x 64 x i8> %x, %va163 ret <vscale x 64 x i8> %y164}165 166define <vscale x 64 x i8> @vmadd_vx_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, i8 %c) {167; CHECK-LABEL: vmadd_vx_nxv64i8:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma170; CHECK-NEXT: vmacc.vx v8, a0, v16171; CHECK-NEXT: ret172 %head = insertelement <vscale x 64 x i8> poison, i8 %c, i32 0173 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer174 %x = mul <vscale x 64 x i8> %vb, %splat175 %y = add <vscale x 64 x i8> %x, %va176 ret <vscale x 64 x i8> %y177}178 179define <vscale x 1 x i16> @vmadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i16> %vc) {180; CHECK-LABEL: vmadd_vv_nxv1i16:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma183; CHECK-NEXT: vmadd.vv v8, v9, v10184; CHECK-NEXT: ret185 %x = mul <vscale x 1 x i16> %va, %vb186 %y = add <vscale x 1 x i16> %x, %vc187 ret <vscale x 1 x i16> %y188}189 190define <vscale x 1 x i16> @vmadd_vx_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, i16 %c) {191; CHECK-LABEL: vmadd_vx_nxv1i16:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma194; CHECK-NEXT: vmadd.vx v8, a0, v9195; CHECK-NEXT: ret196 %head = insertelement <vscale x 1 x i16> poison, i16 %c, i32 0197 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer198 %x = mul <vscale x 1 x i16> %va, %splat199 %y = add <vscale x 1 x i16> %x, %vb200 ret <vscale x 1 x i16> %y201}202 203define <vscale x 2 x i16> @vmadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i16> %vc) {204; CHECK-LABEL: vmadd_vv_nxv2i16:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma207; CHECK-NEXT: vmadd.vv v8, v10, v9208; CHECK-NEXT: ret209 %x = mul <vscale x 2 x i16> %va, %vc210 %y = add <vscale x 2 x i16> %x, %vb211 ret <vscale x 2 x i16> %y212}213 214define <vscale x 2 x i16> @vmadd_vx_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, i16 %c) {215; CHECK-LABEL: vmadd_vx_nxv2i16:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma218; CHECK-NEXT: vmacc.vx v8, a0, v9219; CHECK-NEXT: ret220 %head = insertelement <vscale x 2 x i16> poison, i16 %c, i32 0221 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer222 %x = mul <vscale x 2 x i16> %vb, %splat223 %y = add <vscale x 2 x i16> %x, %va224 ret <vscale x 2 x i16> %y225}226 227define <vscale x 4 x i16> @vmadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i16> %vc) {228; CHECK-LABEL: vmadd_vv_nxv4i16:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma231; CHECK-NEXT: vmadd.vv v8, v9, v10232; CHECK-NEXT: ret233 %x = mul <vscale x 4 x i16> %vb, %va234 %y = add <vscale x 4 x i16> %x, %vc235 ret <vscale x 4 x i16> %y236}237 238define <vscale x 4 x i16> @vmadd_vx_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i16 %c) {239; CHECK-LABEL: vmadd_vx_nxv4i16:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma242; CHECK-NEXT: vmadd.vx v8, a0, v9243; CHECK-NEXT: ret244 %head = insertelement <vscale x 4 x i16> poison, i16 %c, i32 0245 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer246 %x = mul <vscale x 4 x i16> %va, %splat247 %y = add <vscale x 4 x i16> %x, %vb248 ret <vscale x 4 x i16> %y249}250 251define <vscale x 8 x i16> @vmadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i16> %vc) {252; CHECK-LABEL: vmadd_vv_nxv8i16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma255; CHECK-NEXT: vmacc.vv v8, v12, v10256; CHECK-NEXT: ret257 %x = mul <vscale x 8 x i16> %vb, %vc258 %y = add <vscale x 8 x i16> %x, %va259 ret <vscale x 8 x i16> %y260}261 262define <vscale x 8 x i16> @vmadd_vx_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, i16 %c) {263; CHECK-LABEL: vmadd_vx_nxv8i16:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma266; CHECK-NEXT: vmacc.vx v8, a0, v10267; CHECK-NEXT: ret268 %head = insertelement <vscale x 8 x i16> poison, i16 %c, i32 0269 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer270 %x = mul <vscale x 8 x i16> %vb, %splat271 %y = add <vscale x 8 x i16> %x, %va272 ret <vscale x 8 x i16> %y273}274 275define <vscale x 16 x i16> @vmadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i16> %vc) {276; CHECK-LABEL: vmadd_vv_nxv16i16:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma279; CHECK-NEXT: vmadd.vv v8, v16, v12280; CHECK-NEXT: ret281 %x = mul <vscale x 16 x i16> %vc, %va282 %y = add <vscale x 16 x i16> %x, %vb283 ret <vscale x 16 x i16> %y284}285 286define <vscale x 16 x i16> @vmadd_vx_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, i16 %c) {287; CHECK-LABEL: vmadd_vx_nxv16i16:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma290; CHECK-NEXT: vmadd.vx v8, a0, v12291; CHECK-NEXT: ret292 %head = insertelement <vscale x 16 x i16> poison, i16 %c, i32 0293 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer294 %x = mul <vscale x 16 x i16> %va, %splat295 %y = add <vscale x 16 x i16> %x, %vb296 ret <vscale x 16 x i16> %y297}298 299define <vscale x 32 x i16> @vmadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i16> %vc) {300; CHECK-LABEL: vmadd_vv_nxv32i16:301; CHECK: # %bb.0:302; CHECK-NEXT: vl8re16.v v24, (a0)303; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma304; CHECK-NEXT: vmacc.vv v8, v16, v24305; CHECK-NEXT: ret306 %x = mul <vscale x 32 x i16> %vc, %vb307 %y = add <vscale x 32 x i16> %x, %va308 ret <vscale x 32 x i16> %y309}310 311define <vscale x 32 x i16> @vmadd_vx_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, i16 %c) {312; CHECK-LABEL: vmadd_vx_nxv32i16:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma315; CHECK-NEXT: vmacc.vx v8, a0, v16316; CHECK-NEXT: ret317 %head = insertelement <vscale x 32 x i16> poison, i16 %c, i32 0318 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer319 %x = mul <vscale x 32 x i16> %vb, %splat320 %y = add <vscale x 32 x i16> %x, %va321 ret <vscale x 32 x i16> %y322}323 324define <vscale x 1 x i32> @vmadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i32> %vc) {325; CHECK-LABEL: vmadd_vv_nxv1i32:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma328; CHECK-NEXT: vmadd.vv v8, v9, v10329; CHECK-NEXT: ret330 %x = mul <vscale x 1 x i32> %va, %vb331 %y = add <vscale x 1 x i32> %x, %vc332 ret <vscale x 1 x i32> %y333}334 335define <vscale x 1 x i32> @vmadd_vx_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, i32 %c) {336; CHECK-LABEL: vmadd_vx_nxv1i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma339; CHECK-NEXT: vmadd.vx v8, a0, v9340; CHECK-NEXT: ret341 %head = insertelement <vscale x 1 x i32> poison, i32 %c, i32 0342 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer343 %x = mul <vscale x 1 x i32> %va, %splat344 %y = add <vscale x 1 x i32> %x, %vb345 ret <vscale x 1 x i32> %y346}347 348define <vscale x 2 x i32> @vmadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i32> %vc) {349; CHECK-LABEL: vmadd_vv_nxv2i32:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma352; CHECK-NEXT: vmadd.vv v8, v10, v9353; CHECK-NEXT: ret354 %x = mul <vscale x 2 x i32> %va, %vc355 %y = add <vscale x 2 x i32> %x, %vb356 ret <vscale x 2 x i32> %y357}358 359define <vscale x 2 x i32> @vmadd_vx_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 %c) {360; CHECK-LABEL: vmadd_vx_nxv2i32:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma363; CHECK-NEXT: vmacc.vx v8, a0, v9364; CHECK-NEXT: ret365 %head = insertelement <vscale x 2 x i32> poison, i32 %c, i32 0366 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer367 %x = mul <vscale x 2 x i32> %vb, %splat368 %y = add <vscale x 2 x i32> %x, %va369 ret <vscale x 2 x i32> %y370}371 372define <vscale x 4 x i32> @vmadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i32> %vc) {373; CHECK-LABEL: vmadd_vv_nxv4i32:374; CHECK: # %bb.0:375; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma376; CHECK-NEXT: vmadd.vv v8, v10, v12377; CHECK-NEXT: ret378 %x = mul <vscale x 4 x i32> %vb, %va379 %y = add <vscale x 4 x i32> %x, %vc380 ret <vscale x 4 x i32> %y381}382 383define <vscale x 4 x i32> @vmadd_vx_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, i32 %c) {384; CHECK-LABEL: vmadd_vx_nxv4i32:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma387; CHECK-NEXT: vmadd.vx v8, a0, v10388; CHECK-NEXT: ret389 %head = insertelement <vscale x 4 x i32> poison, i32 %c, i32 0390 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer391 %x = mul <vscale x 4 x i32> %va, %splat392 %y = add <vscale x 4 x i32> %x, %vb393 ret <vscale x 4 x i32> %y394}395 396define <vscale x 8 x i32> @vmadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %vc) {397; CHECK-LABEL: vmadd_vv_nxv8i32:398; CHECK: # %bb.0:399; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma400; CHECK-NEXT: vmacc.vv v8, v16, v12401; CHECK-NEXT: ret402 %x = mul <vscale x 8 x i32> %vb, %vc403 %y = add <vscale x 8 x i32> %x, %va404 ret <vscale x 8 x i32> %y405}406 407define <vscale x 8 x i32> @vmadd_vx_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, i32 %c) {408; CHECK-LABEL: vmadd_vx_nxv8i32:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma411; CHECK-NEXT: vmacc.vx v8, a0, v12412; CHECK-NEXT: ret413 %head = insertelement <vscale x 8 x i32> poison, i32 %c, i32 0414 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer415 %x = mul <vscale x 8 x i32> %vb, %splat416 %y = add <vscale x 8 x i32> %x, %va417 ret <vscale x 8 x i32> %y418}419 420define <vscale x 16 x i32> @vmadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i32> %vc) {421; CHECK-LABEL: vmadd_vv_nxv16i32:422; CHECK: # %bb.0:423; CHECK-NEXT: vl8re32.v v24, (a0)424; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma425; CHECK-NEXT: vmadd.vv v8, v24, v16426; CHECK-NEXT: ret427 %x = mul <vscale x 16 x i32> %vc, %va428 %y = add <vscale x 16 x i32> %x, %vb429 ret <vscale x 16 x i32> %y430}431 432define <vscale x 16 x i32> @vmadd_vx_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, i32 %c) {433; CHECK-LABEL: vmadd_vx_nxv16i32:434; CHECK: # %bb.0:435; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma436; CHECK-NEXT: vmadd.vx v8, a0, v16437; CHECK-NEXT: ret438 %head = insertelement <vscale x 16 x i32> poison, i32 %c, i32 0439 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer440 %x = mul <vscale x 16 x i32> %va, %splat441 %y = add <vscale x 16 x i32> %x, %vb442 ret <vscale x 16 x i32> %y443}444 445define <vscale x 1 x i64> @vmadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i64> %vc) {446; CHECK-LABEL: vmadd_vv_nxv1i64:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma449; CHECK-NEXT: vmadd.vv v8, v9, v10450; CHECK-NEXT: ret451 %x = mul <vscale x 1 x i64> %va, %vb452 %y = add <vscale x 1 x i64> %x, %vc453 ret <vscale x 1 x i64> %y454}455 456define <vscale x 1 x i64> @vmadd_vx_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i64 %c) {457; RV32-LABEL: vmadd_vx_nxv1i64:458; RV32: # %bb.0:459; RV32-NEXT: addi sp, sp, -16460; RV32-NEXT: .cfi_def_cfa_offset 16461; RV32-NEXT: sw a0, 8(sp)462; RV32-NEXT: sw a1, 12(sp)463; RV32-NEXT: addi a0, sp, 8464; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma465; RV32-NEXT: vlse64.v v10, (a0), zero466; RV32-NEXT: vmadd.vv v8, v10, v9467; RV32-NEXT: addi sp, sp, 16468; RV32-NEXT: .cfi_def_cfa_offset 0469; RV32-NEXT: ret470;471; RV64-LABEL: vmadd_vx_nxv1i64:472; RV64: # %bb.0:473; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma474; RV64-NEXT: vmadd.vx v8, a0, v9475; RV64-NEXT: ret476 %head = insertelement <vscale x 1 x i64> poison, i64 %c, i32 0477 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer478 %x = mul <vscale x 1 x i64> %va, %splat479 %y = add <vscale x 1 x i64> %x, %vb480 ret <vscale x 1 x i64> %y481}482 483define <vscale x 2 x i64> @vmadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i64> %vc) {484; CHECK-LABEL: vmadd_vv_nxv2i64:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma487; CHECK-NEXT: vmadd.vv v8, v12, v10488; CHECK-NEXT: ret489 %x = mul <vscale x 2 x i64> %va, %vc490 %y = add <vscale x 2 x i64> %x, %vb491 ret <vscale x 2 x i64> %y492}493 494define <vscale x 2 x i64> @vmadd_vx_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i64 %c) {495; RV32-LABEL: vmadd_vx_nxv2i64:496; RV32: # %bb.0:497; RV32-NEXT: addi sp, sp, -16498; RV32-NEXT: .cfi_def_cfa_offset 16499; RV32-NEXT: sw a0, 8(sp)500; RV32-NEXT: sw a1, 12(sp)501; RV32-NEXT: addi a0, sp, 8502; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma503; RV32-NEXT: vlse64.v v12, (a0), zero504; RV32-NEXT: vmacc.vv v8, v10, v12505; RV32-NEXT: addi sp, sp, 16506; RV32-NEXT: .cfi_def_cfa_offset 0507; RV32-NEXT: ret508;509; RV64-LABEL: vmadd_vx_nxv2i64:510; RV64: # %bb.0:511; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma512; RV64-NEXT: vmacc.vx v8, a0, v10513; RV64-NEXT: ret514 %head = insertelement <vscale x 2 x i64> poison, i64 %c, i32 0515 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer516 %x = mul <vscale x 2 x i64> %vb, %splat517 %y = add <vscale x 2 x i64> %x, %va518 ret <vscale x 2 x i64> %y519}520 521define <vscale x 4 x i64> @vmadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i64> %vc) {522; CHECK-LABEL: vmadd_vv_nxv4i64:523; CHECK: # %bb.0:524; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma525; CHECK-NEXT: vmadd.vv v8, v12, v16526; CHECK-NEXT: ret527 %x = mul <vscale x 4 x i64> %vb, %va528 %y = add <vscale x 4 x i64> %x, %vc529 ret <vscale x 4 x i64> %y530}531 532define <vscale x 4 x i64> @vmadd_vx_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, i64 %c) {533; RV32-LABEL: vmadd_vx_nxv4i64:534; RV32: # %bb.0:535; RV32-NEXT: addi sp, sp, -16536; RV32-NEXT: .cfi_def_cfa_offset 16537; RV32-NEXT: sw a0, 8(sp)538; RV32-NEXT: sw a1, 12(sp)539; RV32-NEXT: addi a0, sp, 8540; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma541; RV32-NEXT: vlse64.v v16, (a0), zero542; RV32-NEXT: vmadd.vv v8, v16, v12543; RV32-NEXT: addi sp, sp, 16544; RV32-NEXT: .cfi_def_cfa_offset 0545; RV32-NEXT: ret546;547; RV64-LABEL: vmadd_vx_nxv4i64:548; RV64: # %bb.0:549; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma550; RV64-NEXT: vmadd.vx v8, a0, v12551; RV64-NEXT: ret552 %head = insertelement <vscale x 4 x i64> poison, i64 %c, i32 0553 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer554 %x = mul <vscale x 4 x i64> %va, %splat555 %y = add <vscale x 4 x i64> %x, %vb556 ret <vscale x 4 x i64> %y557}558 559define <vscale x 8 x i64> @vmadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i64> %vc) {560; CHECK-LABEL: vmadd_vv_nxv8i64:561; CHECK: # %bb.0:562; CHECK-NEXT: vl8re64.v v24, (a0)563; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma564; CHECK-NEXT: vmacc.vv v8, v16, v24565; CHECK-NEXT: ret566 %x = mul <vscale x 8 x i64> %vb, %vc567 %y = add <vscale x 8 x i64> %x, %va568 ret <vscale x 8 x i64> %y569}570 571define <vscale x 8 x i64> @vmadd_vx_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, i64 %c) {572; RV32-LABEL: vmadd_vx_nxv8i64:573; RV32: # %bb.0:574; RV32-NEXT: addi sp, sp, -16575; RV32-NEXT: .cfi_def_cfa_offset 16576; RV32-NEXT: sw a0, 8(sp)577; RV32-NEXT: sw a1, 12(sp)578; RV32-NEXT: addi a0, sp, 8579; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma580; RV32-NEXT: vlse64.v v24, (a0), zero581; RV32-NEXT: vmacc.vv v8, v16, v24582; RV32-NEXT: addi sp, sp, 16583; RV32-NEXT: .cfi_def_cfa_offset 0584; RV32-NEXT: ret585;586; RV64-LABEL: vmadd_vx_nxv8i64:587; RV64: # %bb.0:588; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma589; RV64-NEXT: vmacc.vx v8, a0, v16590; RV64-NEXT: ret591 %head = insertelement <vscale x 8 x i64> poison, i64 %c, i32 0592 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer593 %x = mul <vscale x 8 x i64> %vb, %splat594 %y = add <vscale x 8 x i64> %x, %va595 ret <vscale x 8 x i64> %y596}597 598define <vscale x 4 x i32> @combine_mul_add_imm1(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {599; CHECK-LABEL: combine_mul_add_imm1:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma602; CHECK-NEXT: vmadd.vv v8, v10, v10603; CHECK-NEXT: ret604 %x = add <vscale x 4 x i32> %a, splat (i32 1)605 %y = mul <vscale x 4 x i32> %x, %b606 ret <vscale x 4 x i32> %y607}608 609define <vscale x 4 x i32> @combine_mul_add_imm1_2(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {610; CHECK-LABEL: combine_mul_add_imm1_2:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma613; CHECK-NEXT: vmadd.vv v8, v10, v10614; CHECK-NEXT: ret615 %x = add <vscale x 4 x i32> %a, splat (i32 1)616 %y = mul <vscale x 4 x i32> %b, %x617 ret <vscale x 4 x i32> %y618}619