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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i1> @vmand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {6; CHECK-LABEL: vmand_vv_nxv1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vmand.mm v0, v0, v810; CHECK-NEXT: ret11 %vc = and <vscale x 1 x i1> %va, %vb12 ret <vscale x 1 x i1> %vc13}14 15define <vscale x 2 x i1> @vmand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {16; CHECK-LABEL: vmand_vv_nxv2i1:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma19; CHECK-NEXT: vmand.mm v0, v0, v820; CHECK-NEXT: ret21 %vc = and <vscale x 2 x i1> %va, %vb22 ret <vscale x 2 x i1> %vc23}24 25define <vscale x 4 x i1> @vmand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {26; CHECK-LABEL: vmand_vv_nxv4i1:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma29; CHECK-NEXT: vmand.mm v0, v0, v830; CHECK-NEXT: ret31 %vc = and <vscale x 4 x i1> %va, %vb32 ret <vscale x 4 x i1> %vc33}34 35define <vscale x 8 x i1> @vmand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {36; CHECK-LABEL: vmand_vv_nxv8i1:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma39; CHECK-NEXT: vmand.mm v0, v0, v840; CHECK-NEXT: ret41 %vc = and <vscale x 8 x i1> %va, %vb42 ret <vscale x 8 x i1> %vc43}44 45define <vscale x 16 x i1> @vmand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {46; CHECK-LABEL: vmand_vv_nxv16i1:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma49; CHECK-NEXT: vmand.mm v0, v0, v850; CHECK-NEXT: ret51 %vc = and <vscale x 16 x i1> %va, %vb52 ret <vscale x 16 x i1> %vc53}54 55define <vscale x 1 x i1> @vmor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {56; CHECK-LABEL: vmor_vv_nxv1i1:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma59; CHECK-NEXT: vmor.mm v0, v0, v860; CHECK-NEXT: ret61 %vc = or <vscale x 1 x i1> %va, %vb62 ret <vscale x 1 x i1> %vc63}64 65define <vscale x 2 x i1> @vmor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {66; CHECK-LABEL: vmor_vv_nxv2i1:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma69; CHECK-NEXT: vmor.mm v0, v0, v870; CHECK-NEXT: ret71 %vc = or <vscale x 2 x i1> %va, %vb72 ret <vscale x 2 x i1> %vc73}74 75define <vscale x 4 x i1> @vmor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {76; CHECK-LABEL: vmor_vv_nxv4i1:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma79; CHECK-NEXT: vmor.mm v0, v0, v880; CHECK-NEXT: ret81 %vc = or <vscale x 4 x i1> %va, %vb82 ret <vscale x 4 x i1> %vc83}84 85define <vscale x 8 x i1> @vmor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {86; CHECK-LABEL: vmor_vv_nxv8i1:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma89; CHECK-NEXT: vmor.mm v0, v0, v890; CHECK-NEXT: ret91 %vc = or <vscale x 8 x i1> %va, %vb92 ret <vscale x 8 x i1> %vc93}94 95define <vscale x 16 x i1> @vmor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {96; CHECK-LABEL: vmor_vv_nxv16i1:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma99; CHECK-NEXT: vmor.mm v0, v0, v8100; CHECK-NEXT: ret101 %vc = or <vscale x 16 x i1> %va, %vb102 ret <vscale x 16 x i1> %vc103}104 105define <vscale x 1 x i1> @vmxor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {106; CHECK-LABEL: vmxor_vv_nxv1i1:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma109; CHECK-NEXT: vmxor.mm v0, v0, v8110; CHECK-NEXT: ret111 %vc = xor <vscale x 1 x i1> %va, %vb112 ret <vscale x 1 x i1> %vc113}114 115define <vscale x 2 x i1> @vmxor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {116; CHECK-LABEL: vmxor_vv_nxv2i1:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma119; CHECK-NEXT: vmxor.mm v0, v0, v8120; CHECK-NEXT: ret121 %vc = xor <vscale x 2 x i1> %va, %vb122 ret <vscale x 2 x i1> %vc123}124 125define <vscale x 4 x i1> @vmxor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {126; CHECK-LABEL: vmxor_vv_nxv4i1:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma129; CHECK-NEXT: vmxor.mm v0, v0, v8130; CHECK-NEXT: ret131 %vc = xor <vscale x 4 x i1> %va, %vb132 ret <vscale x 4 x i1> %vc133}134 135define <vscale x 8 x i1> @vmxor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {136; CHECK-LABEL: vmxor_vv_nxv8i1:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma139; CHECK-NEXT: vmxor.mm v0, v0, v8140; CHECK-NEXT: ret141 %vc = xor <vscale x 8 x i1> %va, %vb142 ret <vscale x 8 x i1> %vc143}144 145define <vscale x 16 x i1> @vmxor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {146; CHECK-LABEL: vmxor_vv_nxv16i1:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma149; CHECK-NEXT: vmxor.mm v0, v0, v8150; CHECK-NEXT: ret151 %vc = xor <vscale x 16 x i1> %va, %vb152 ret <vscale x 16 x i1> %vc153}154 155define <vscale x 1 x i1> @vmnand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {156; CHECK-LABEL: vmnand_vv_nxv1i1:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma159; CHECK-NEXT: vmnand.mm v0, v0, v8160; CHECK-NEXT: ret161 %vc = and <vscale x 1 x i1> %va, %vb162 %not = xor <vscale x 1 x i1> %vc, splat (i1 1)163 ret <vscale x 1 x i1> %not164}165 166define <vscale x 2 x i1> @vmnand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {167; CHECK-LABEL: vmnand_vv_nxv2i1:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma170; CHECK-NEXT: vmnand.mm v0, v0, v8171; CHECK-NEXT: ret172 %vc = and <vscale x 2 x i1> %va, %vb173 %not = xor <vscale x 2 x i1> %vc, splat (i1 1)174 ret <vscale x 2 x i1> %not175}176 177define <vscale x 4 x i1> @vmnand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {178; CHECK-LABEL: vmnand_vv_nxv4i1:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma181; CHECK-NEXT: vmnand.mm v0, v0, v8182; CHECK-NEXT: ret183 %vc = and <vscale x 4 x i1> %va, %vb184 %not = xor <vscale x 4 x i1> %vc, splat (i1 1)185 ret <vscale x 4 x i1> %not186}187 188define <vscale x 8 x i1> @vmnand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {189; CHECK-LABEL: vmnand_vv_nxv8i1:190; CHECK: # %bb.0:191; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma192; CHECK-NEXT: vmnand.mm v0, v0, v8193; CHECK-NEXT: ret194 %vc = and <vscale x 8 x i1> %va, %vb195 %not = xor <vscale x 8 x i1> %vc, splat (i1 1)196 ret <vscale x 8 x i1> %not197}198 199define <vscale x 16 x i1> @vmnand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {200; CHECK-LABEL: vmnand_vv_nxv16i1:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma203; CHECK-NEXT: vmnand.mm v0, v0, v8204; CHECK-NEXT: ret205 %vc = and <vscale x 16 x i1> %va, %vb206 %not = xor <vscale x 16 x i1> %vc, splat (i1 1)207 ret <vscale x 16 x i1> %not208}209 210define <vscale x 1 x i1> @vmnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {211; CHECK-LABEL: vmnor_vv_nxv1i1:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma214; CHECK-NEXT: vmnor.mm v0, v0, v8215; CHECK-NEXT: ret216 %vc = or <vscale x 1 x i1> %va, %vb217 %not = xor <vscale x 1 x i1> %vc, splat (i1 1)218 ret <vscale x 1 x i1> %not219}220 221define <vscale x 2 x i1> @vmnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {222; CHECK-LABEL: vmnor_vv_nxv2i1:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma225; CHECK-NEXT: vmnor.mm v0, v0, v8226; CHECK-NEXT: ret227 %vc = or <vscale x 2 x i1> %va, %vb228 %not = xor <vscale x 2 x i1> %vc, splat (i1 1)229 ret <vscale x 2 x i1> %not230}231 232define <vscale x 4 x i1> @vmnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {233; CHECK-LABEL: vmnor_vv_nxv4i1:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma236; CHECK-NEXT: vmnor.mm v0, v0, v8237; CHECK-NEXT: ret238 %vc = or <vscale x 4 x i1> %va, %vb239 %not = xor <vscale x 4 x i1> %vc, splat (i1 1)240 ret <vscale x 4 x i1> %not241}242 243define <vscale x 8 x i1> @vmnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {244; CHECK-LABEL: vmnor_vv_nxv8i1:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma247; CHECK-NEXT: vmnor.mm v0, v0, v8248; CHECK-NEXT: ret249 %vc = or <vscale x 8 x i1> %va, %vb250 %not = xor <vscale x 8 x i1> %vc, splat (i1 1)251 ret <vscale x 8 x i1> %not252}253 254define <vscale x 16 x i1> @vmnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {255; CHECK-LABEL: vmnor_vv_nxv16i1:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma258; CHECK-NEXT: vmnor.mm v0, v0, v8259; CHECK-NEXT: ret260 %vc = or <vscale x 16 x i1> %va, %vb261 %not = xor <vscale x 16 x i1> %vc, splat (i1 1)262 ret <vscale x 16 x i1> %not263}264 265define <vscale x 1 x i1> @vmxnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {266; CHECK-LABEL: vmxnor_vv_nxv1i1:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma269; CHECK-NEXT: vmxnor.mm v0, v0, v8270; CHECK-NEXT: ret271 %vc = xor <vscale x 1 x i1> %va, %vb272 %not = xor <vscale x 1 x i1> %vc, splat (i1 1)273 ret <vscale x 1 x i1> %not274}275 276define <vscale x 2 x i1> @vmxnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {277; CHECK-LABEL: vmxnor_vv_nxv2i1:278; CHECK: # %bb.0:279; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma280; CHECK-NEXT: vmxnor.mm v0, v0, v8281; CHECK-NEXT: ret282 %vc = xor <vscale x 2 x i1> %va, %vb283 %not = xor <vscale x 2 x i1> %vc, splat (i1 1)284 ret <vscale x 2 x i1> %not285}286 287define <vscale x 4 x i1> @vmxnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {288; CHECK-LABEL: vmxnor_vv_nxv4i1:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma291; CHECK-NEXT: vmxnor.mm v0, v0, v8292; CHECK-NEXT: ret293 %vc = xor <vscale x 4 x i1> %va, %vb294 %not = xor <vscale x 4 x i1> %vc, splat (i1 1)295 ret <vscale x 4 x i1> %not296}297 298define <vscale x 8 x i1> @vmxnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {299; CHECK-LABEL: vmxnor_vv_nxv8i1:300; CHECK: # %bb.0:301; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma302; CHECK-NEXT: vmxnor.mm v0, v0, v8303; CHECK-NEXT: ret304 %vc = xor <vscale x 8 x i1> %va, %vb305 %not = xor <vscale x 8 x i1> %vc, splat (i1 1)306 ret <vscale x 8 x i1> %not307}308 309define <vscale x 16 x i1> @vmxnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {310; CHECK-LABEL: vmxnor_vv_nxv16i1:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma313; CHECK-NEXT: vmxnor.mm v0, v0, v8314; CHECK-NEXT: ret315 %vc = xor <vscale x 16 x i1> %va, %vb316 %not = xor <vscale x 16 x i1> %vc, splat (i1 1)317 ret <vscale x 16 x i1> %not318}319 320define <vscale x 1 x i1> @vmandn_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {321; CHECK-LABEL: vmandn_vv_nxv1i1:322; CHECK: # %bb.0:323; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma324; CHECK-NEXT: vmandn.mm v0, v0, v8325; CHECK-NEXT: ret326 %not = xor <vscale x 1 x i1> %vb, splat (i1 1)327 %vc = and <vscale x 1 x i1> %va, %not328 ret <vscale x 1 x i1> %vc329}330 331define <vscale x 2 x i1> @vmandn_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {332; CHECK-LABEL: vmandn_vv_nxv2i1:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma335; CHECK-NEXT: vmandn.mm v0, v0, v8336; CHECK-NEXT: ret337 %not = xor <vscale x 2 x i1> %vb, splat (i1 1)338 %vc = and <vscale x 2 x i1> %va, %not339 ret <vscale x 2 x i1> %vc340}341 342define <vscale x 4 x i1> @vmandn_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {343; CHECK-LABEL: vmandn_vv_nxv4i1:344; CHECK: # %bb.0:345; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma346; CHECK-NEXT: vmandn.mm v0, v0, v8347; CHECK-NEXT: ret348 %not = xor <vscale x 4 x i1> %vb, splat (i1 1)349 %vc = and <vscale x 4 x i1> %va, %not350 ret <vscale x 4 x i1> %vc351}352 353define <vscale x 8 x i1> @vmandn_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {354; CHECK-LABEL: vmandn_vv_nxv8i1:355; CHECK: # %bb.0:356; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma357; CHECK-NEXT: vmandn.mm v0, v0, v8358; CHECK-NEXT: ret359 %not = xor <vscale x 8 x i1> %vb, splat (i1 1)360 %vc = and <vscale x 8 x i1> %va, %not361 ret <vscale x 8 x i1> %vc362}363 364define <vscale x 16 x i1> @vmandn_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {365; CHECK-LABEL: vmandn_vv_nxv16i1:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma368; CHECK-NEXT: vmandn.mm v0, v0, v8369; CHECK-NEXT: ret370 %not = xor <vscale x 16 x i1> %vb, splat (i1 1)371 %vc = and <vscale x 16 x i1> %va, %not372 ret <vscale x 16 x i1> %vc373}374 375define <vscale x 1 x i1> @vmorn_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {376; CHECK-LABEL: vmorn_vv_nxv1i1:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma379; CHECK-NEXT: vmorn.mm v0, v0, v8380; CHECK-NEXT: ret381 %not = xor <vscale x 1 x i1> %vb, splat (i1 1)382 %vc = or <vscale x 1 x i1> %va, %not383 ret <vscale x 1 x i1> %vc384}385 386define <vscale x 2 x i1> @vmorn_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {387; CHECK-LABEL: vmorn_vv_nxv2i1:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma390; CHECK-NEXT: vmorn.mm v0, v0, v8391; CHECK-NEXT: ret392 %not = xor <vscale x 2 x i1> %vb, splat (i1 1)393 %vc = or <vscale x 2 x i1> %va, %not394 ret <vscale x 2 x i1> %vc395}396 397define <vscale x 4 x i1> @vmorn_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {398; CHECK-LABEL: vmorn_vv_nxv4i1:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma401; CHECK-NEXT: vmorn.mm v0, v0, v8402; CHECK-NEXT: ret403 %not = xor <vscale x 4 x i1> %vb, splat (i1 1)404 %vc = or <vscale x 4 x i1> %va, %not405 ret <vscale x 4 x i1> %vc406}407 408define <vscale x 8 x i1> @vmorn_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {409; CHECK-LABEL: vmorn_vv_nxv8i1:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma412; CHECK-NEXT: vmorn.mm v0, v0, v8413; CHECK-NEXT: ret414 %not = xor <vscale x 8 x i1> %vb, splat (i1 1)415 %vc = or <vscale x 8 x i1> %va, %not416 ret <vscale x 8 x i1> %vc417}418 419define <vscale x 16 x i1> @vmorn_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {420; CHECK-LABEL: vmorn_vv_nxv16i1:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma423; CHECK-NEXT: vmorn.mm v0, v0, v8424; CHECK-NEXT: ret425 %not = xor <vscale x 16 x i1> %vb, splat (i1 1)426 %vc = or <vscale x 16 x i1> %va, %not427 ret <vscale x 16 x i1> %vc428}429