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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck -check-prefixes=CHECK,RV32 %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck -check-prefixes=CHECK,RV64 %s6 7define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmerge.vvm v8, v8, v9, v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i8> %0,17 <vscale x 1 x i8> %1,18 <vscale x 1 x i1> %2,19 iXLen %3)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma28; CHECK-NEXT: vmerge.vvm v8, v8, v9, v029; CHECK-NEXT: ret30entry:31 %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(32 <vscale x 2 x i8> poison,33 <vscale x 2 x i8> %0,34 <vscale x 2 x i8> %1,35 <vscale x 2 x i1> %2,36 iXLen %3)37 38 ret <vscale x 2 x i8> %a39}40 41define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {42; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma45; CHECK-NEXT: vmerge.vvm v8, v8, v9, v046; CHECK-NEXT: ret47entry:48 %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(49 <vscale x 4 x i8> poison,50 <vscale x 4 x i8> %0,51 <vscale x 4 x i8> %1,52 <vscale x 4 x i1> %2,53 iXLen %3)54 55 ret <vscale x 4 x i8> %a56}57 58define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {59; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma62; CHECK-NEXT: vmerge.vvm v8, v8, v9, v063; CHECK-NEXT: ret64entry:65 %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(66 <vscale x 8 x i8> poison,67 <vscale x 8 x i8> %0,68 <vscale x 8 x i8> %1,69 <vscale x 8 x i1> %2,70 iXLen %3)71 72 ret <vscale x 8 x i8> %a73}74 75define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {76; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma79; CHECK-NEXT: vmerge.vvm v8, v8, v10, v080; CHECK-NEXT: ret81entry:82 %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(83 <vscale x 16 x i8> poison,84 <vscale x 16 x i8> %0,85 <vscale x 16 x i8> %1,86 <vscale x 16 x i1> %2,87 iXLen %3)88 89 ret <vscale x 16 x i8> %a90}91 92define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {93; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma96; CHECK-NEXT: vmerge.vvm v8, v8, v12, v097; CHECK-NEXT: ret98entry:99 %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(100 <vscale x 32 x i8> poison,101 <vscale x 32 x i8> %0,102 <vscale x 32 x i8> %1,103 <vscale x 32 x i1> %2,104 iXLen %3)105 106 ret <vscale x 32 x i8> %a107}108 109define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {110; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma113; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0114; CHECK-NEXT: ret115entry:116 %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(117 <vscale x 64 x i8> poison,118 <vscale x 64 x i8> %0,119 <vscale x 64 x i8> %1,120 <vscale x 64 x i1> %2,121 iXLen %3)122 123 ret <vscale x 64 x i8> %a124}125 126define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {127; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma130; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(134 <vscale x 1 x i16> poison,135 <vscale x 1 x i16> %0,136 <vscale x 1 x i16> %1,137 <vscale x 1 x i1> %2,138 iXLen %3)139 140 ret <vscale x 1 x i16> %a141}142 143define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {144; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma147; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0148; CHECK-NEXT: ret149entry:150 %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(151 <vscale x 2 x i16> poison,152 <vscale x 2 x i16> %0,153 <vscale x 2 x i16> %1,154 <vscale x 2 x i1> %2,155 iXLen %3)156 157 ret <vscale x 2 x i16> %a158}159 160define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {161; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma164; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(168 <vscale x 4 x i16> poison,169 <vscale x 4 x i16> %0,170 <vscale x 4 x i16> %1,171 <vscale x 4 x i1> %2,172 iXLen %3)173 174 ret <vscale x 4 x i16> %a175}176 177define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma181; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(185 <vscale x 8 x i16> poison,186 <vscale x 8 x i16> %0,187 <vscale x 8 x i16> %1,188 <vscale x 8 x i1> %2,189 iXLen %3)190 191 ret <vscale x 8 x i16> %a192}193 194define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {195; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma198; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(202 <vscale x 16 x i16> poison,203 <vscale x 16 x i16> %0,204 <vscale x 16 x i16> %1,205 <vscale x 16 x i1> %2,206 iXLen %3)207 208 ret <vscale x 16 x i16> %a209}210 211define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {212; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma215; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0216; CHECK-NEXT: ret217entry:218 %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(219 <vscale x 32 x i16> poison,220 <vscale x 32 x i16> %0,221 <vscale x 32 x i16> %1,222 <vscale x 32 x i1> %2,223 iXLen %3)224 225 ret <vscale x 32 x i16> %a226}227 228define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {229; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma232; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(236 <vscale x 1 x i32> poison,237 <vscale x 1 x i32> %0,238 <vscale x 1 x i32> %1,239 <vscale x 1 x i1> %2,240 iXLen %3)241 242 ret <vscale x 1 x i32> %a243}244 245define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {246; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma249; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0250; CHECK-NEXT: ret251entry:252 %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(253 <vscale x 2 x i32> poison,254 <vscale x 2 x i32> %0,255 <vscale x 2 x i32> %1,256 <vscale x 2 x i1> %2,257 iXLen %3)258 259 ret <vscale x 2 x i32> %a260}261 262define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {263; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma266; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(270 <vscale x 4 x i32> poison,271 <vscale x 4 x i32> %0,272 <vscale x 4 x i32> %1,273 <vscale x 4 x i1> %2,274 iXLen %3)275 276 ret <vscale x 4 x i32> %a277}278 279define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma283; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(287 <vscale x 8 x i32> poison,288 <vscale x 8 x i32> %0,289 <vscale x 8 x i32> %1,290 <vscale x 8 x i1> %2,291 iXLen %3)292 293 ret <vscale x 8 x i32> %a294}295 296define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {297; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma300; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(304 <vscale x 16 x i32> poison,305 <vscale x 16 x i32> %0,306 <vscale x 16 x i32> %1,307 <vscale x 16 x i1> %2,308 iXLen %3)309 310 ret <vscale x 16 x i32> %a311}312 313define <vscale x 1 x i64> @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {314; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma317; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0318; CHECK-NEXT: ret319entry:320 %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(321 <vscale x 1 x i64> poison,322 <vscale x 1 x i64> %0,323 <vscale x 1 x i64> %1,324 <vscale x 1 x i1> %2,325 iXLen %3)326 327 ret <vscale x 1 x i64> %a328}329 330define <vscale x 2 x i64> @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {331; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma334; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(338 <vscale x 2 x i64> poison,339 <vscale x 2 x i64> %0,340 <vscale x 2 x i64> %1,341 <vscale x 2 x i1> %2,342 iXLen %3)343 344 ret <vscale x 2 x i64> %a345}346 347define <vscale x 4 x i64> @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {348; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma351; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0352; CHECK-NEXT: ret353entry:354 %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(355 <vscale x 4 x i64> poison,356 <vscale x 4 x i64> %0,357 <vscale x 4 x i64> %1,358 <vscale x 4 x i1> %2,359 iXLen %3)360 361 ret <vscale x 4 x i64> %a362}363 364define <vscale x 8 x i64> @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {365; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma368; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(372 <vscale x 8 x i64> poison,373 <vscale x 8 x i64> %0,374 <vscale x 8 x i64> %1,375 <vscale x 8 x i1> %2,376 iXLen %3)377 378 ret <vscale x 8 x i64> %a379}380 381define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {382; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma385; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0386; CHECK-NEXT: ret387entry:388 %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(389 <vscale x 1 x i8> poison,390 <vscale x 1 x i8> %0,391 i8 %1,392 <vscale x 1 x i1> %2,393 iXLen %3)394 395 ret <vscale x 1 x i8> %a396}397 398define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {399; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma402; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(406 <vscale x 2 x i8> poison,407 <vscale x 2 x i8> %0,408 i8 %1,409 <vscale x 2 x i1> %2,410 iXLen %3)411 412 ret <vscale x 2 x i8> %a413}414 415define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {416; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma419; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0420; CHECK-NEXT: ret421entry:422 %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(423 <vscale x 4 x i8> poison,424 <vscale x 4 x i8> %0,425 i8 %1,426 <vscale x 4 x i1> %2,427 iXLen %3)428 429 ret <vscale x 4 x i8> %a430}431 432define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {433; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma436; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0437; CHECK-NEXT: ret438entry:439 %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(440 <vscale x 8 x i8> poison,441 <vscale x 8 x i8> %0,442 i8 %1,443 <vscale x 8 x i1> %2,444 iXLen %3)445 446 ret <vscale x 8 x i8> %a447}448 449define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {450; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma453; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0454; CHECK-NEXT: ret455entry:456 %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(457 <vscale x 16 x i8> poison,458 <vscale x 16 x i8> %0,459 i8 %1,460 <vscale x 16 x i1> %2,461 iXLen %3)462 463 ret <vscale x 16 x i8> %a464}465 466define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {467; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8:468; CHECK: # %bb.0: # %entry469; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma470; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0471; CHECK-NEXT: ret472entry:473 %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(474 <vscale x 32 x i8> poison,475 <vscale x 32 x i8> %0,476 i8 %1,477 <vscale x 32 x i1> %2,478 iXLen %3)479 480 ret <vscale x 32 x i8> %a481}482 483define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {484; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8:485; CHECK: # %bb.0: # %entry486; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma487; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0488; CHECK-NEXT: ret489entry:490 %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(491 <vscale x 64 x i8> poison,492 <vscale x 64 x i8> %0,493 i8 %1,494 <vscale x 64 x i1> %2,495 iXLen %3)496 497 ret <vscale x 64 x i8> %a498}499 500define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {501; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma504; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(508 <vscale x 1 x i16> poison,509 <vscale x 1 x i16> %0,510 i16 %1,511 <vscale x 1 x i1> %2,512 iXLen %3)513 514 ret <vscale x 1 x i16> %a515}516 517define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {518; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16:519; CHECK: # %bb.0: # %entry520; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma521; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0522; CHECK-NEXT: ret523entry:524 %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(525 <vscale x 2 x i16> poison,526 <vscale x 2 x i16> %0,527 i16 %1,528 <vscale x 2 x i1> %2,529 iXLen %3)530 531 ret <vscale x 2 x i16> %a532}533 534define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {535; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma538; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0539; CHECK-NEXT: ret540entry:541 %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(542 <vscale x 4 x i16> poison,543 <vscale x 4 x i16> %0,544 i16 %1,545 <vscale x 4 x i1> %2,546 iXLen %3)547 548 ret <vscale x 4 x i16> %a549}550 551define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {552; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma555; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(559 <vscale x 8 x i16> poison,560 <vscale x 8 x i16> %0,561 i16 %1,562 <vscale x 8 x i1> %2,563 iXLen %3)564 565 ret <vscale x 8 x i16> %a566}567 568define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {569; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma572; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(576 <vscale x 16 x i16> poison,577 <vscale x 16 x i16> %0,578 i16 %1,579 <vscale x 16 x i1> %2,580 iXLen %3)581 582 ret <vscale x 16 x i16> %a583}584 585define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {586; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16:587; CHECK: # %bb.0: # %entry588; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma589; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0590; CHECK-NEXT: ret591entry:592 %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(593 <vscale x 32 x i16> poison,594 <vscale x 32 x i16> %0,595 i16 %1,596 <vscale x 32 x i1> %2,597 iXLen %3)598 599 ret <vscale x 32 x i16> %a600}601 602define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {603; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma606; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0607; CHECK-NEXT: ret608entry:609 %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(610 <vscale x 1 x i32> poison,611 <vscale x 1 x i32> %0,612 i32 %1,613 <vscale x 1 x i1> %2,614 iXLen %3)615 616 ret <vscale x 1 x i32> %a617}618 619define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {620; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32:621; CHECK: # %bb.0: # %entry622; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma623; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0624; CHECK-NEXT: ret625entry:626 %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(627 <vscale x 2 x i32> poison,628 <vscale x 2 x i32> %0,629 i32 %1,630 <vscale x 2 x i1> %2,631 iXLen %3)632 633 ret <vscale x 2 x i32> %a634}635 636define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {637; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32:638; CHECK: # %bb.0: # %entry639; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma640; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0641; CHECK-NEXT: ret642entry:643 %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(644 <vscale x 4 x i32> poison,645 <vscale x 4 x i32> %0,646 i32 %1,647 <vscale x 4 x i1> %2,648 iXLen %3)649 650 ret <vscale x 4 x i32> %a651}652 653define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {654; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma657; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0658; CHECK-NEXT: ret659entry:660 %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(661 <vscale x 8 x i32> poison,662 <vscale x 8 x i32> %0,663 i32 %1,664 <vscale x 8 x i1> %2,665 iXLen %3)666 667 ret <vscale x 8 x i32> %a668}669 670define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {671; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma674; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(678 <vscale x 16 x i32> poison,679 <vscale x 16 x i32> %0,680 i32 %1,681 <vscale x 16 x i1> %2,682 iXLen %3)683 684 ret <vscale x 16 x i32> %a685}686 687define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {688; RV32-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64:689; RV32: # %bb.0: # %entry690; RV32-NEXT: addi sp, sp, -16691; RV32-NEXT: sw a0, 8(sp)692; RV32-NEXT: sw a1, 12(sp)693; RV32-NEXT: addi a0, sp, 8694; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu695; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t696; RV32-NEXT: addi sp, sp, 16697; RV32-NEXT: ret698;699; RV64-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64:700; RV64: # %bb.0: # %entry701; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma702; RV64-NEXT: vmerge.vxm v8, v8, a0, v0703; RV64-NEXT: ret704entry:705 %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(706 <vscale x 1 x i64> poison,707 <vscale x 1 x i64> %0,708 i64 %1,709 <vscale x 1 x i1> %2,710 iXLen %3)711 712 ret <vscale x 1 x i64> %a713}714 715define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {716; RV32-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64:717; RV32: # %bb.0: # %entry718; RV32-NEXT: addi sp, sp, -16719; RV32-NEXT: sw a0, 8(sp)720; RV32-NEXT: sw a1, 12(sp)721; RV32-NEXT: addi a0, sp, 8722; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu723; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t724; RV32-NEXT: addi sp, sp, 16725; RV32-NEXT: ret726;727; RV64-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64:728; RV64: # %bb.0: # %entry729; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma730; RV64-NEXT: vmerge.vxm v8, v8, a0, v0731; RV64-NEXT: ret732entry:733 %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(734 <vscale x 2 x i64> poison,735 <vscale x 2 x i64> %0,736 i64 %1,737 <vscale x 2 x i1> %2,738 iXLen %3)739 740 ret <vscale x 2 x i64> %a741}742 743define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {744; RV32-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64:745; RV32: # %bb.0: # %entry746; RV32-NEXT: addi sp, sp, -16747; RV32-NEXT: sw a0, 8(sp)748; RV32-NEXT: sw a1, 12(sp)749; RV32-NEXT: addi a0, sp, 8750; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu751; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t752; RV32-NEXT: addi sp, sp, 16753; RV32-NEXT: ret754;755; RV64-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64:756; RV64: # %bb.0: # %entry757; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma758; RV64-NEXT: vmerge.vxm v8, v8, a0, v0759; RV64-NEXT: ret760entry:761 %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(762 <vscale x 4 x i64> poison,763 <vscale x 4 x i64> %0,764 i64 %1,765 <vscale x 4 x i1> %2,766 iXLen %3)767 768 ret <vscale x 4 x i64> %a769}770 771define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {772; RV32-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:773; RV32: # %bb.0: # %entry774; RV32-NEXT: addi sp, sp, -16775; RV32-NEXT: sw a0, 8(sp)776; RV32-NEXT: sw a1, 12(sp)777; RV32-NEXT: addi a0, sp, 8778; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu779; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t780; RV32-NEXT: addi sp, sp, 16781; RV32-NEXT: ret782;783; RV64-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:784; RV64: # %bb.0: # %entry785; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma786; RV64-NEXT: vmerge.vxm v8, v8, a0, v0787; RV64-NEXT: ret788entry:789 %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(790 <vscale x 8 x i64> poison,791 <vscale x 8 x i64> %0,792 i64 %1,793 <vscale x 8 x i1> %2,794 iXLen %3)795 796 ret <vscale x 8 x i64> %a797}798 799define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {800; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma803; CHECK-NEXT: vmerge.vim v8, v8, 9, v0804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(807 <vscale x 1 x i8> poison,808 <vscale x 1 x i8> %0,809 i8 9,810 <vscale x 1 x i1> %1,811 iXLen %2)812 813 ret <vscale x 1 x i8> %a814}815 816define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {817; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8:818; CHECK: # %bb.0: # %entry819; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma820; CHECK-NEXT: vmerge.vim v8, v8, 9, v0821; CHECK-NEXT: ret822entry:823 %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(824 <vscale x 2 x i8> poison,825 <vscale x 2 x i8> %0,826 i8 9,827 <vscale x 2 x i1> %1,828 iXLen %2)829 830 ret <vscale x 2 x i8> %a831}832 833define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {834; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8:835; CHECK: # %bb.0: # %entry836; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma837; CHECK-NEXT: vmerge.vim v8, v8, 9, v0838; CHECK-NEXT: ret839entry:840 %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(841 <vscale x 4 x i8> poison,842 <vscale x 4 x i8> %0,843 i8 9,844 <vscale x 4 x i1> %1,845 iXLen %2)846 847 ret <vscale x 4 x i8> %a848}849 850define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {851; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8:852; CHECK: # %bb.0: # %entry853; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma854; CHECK-NEXT: vmerge.vim v8, v8, 9, v0855; CHECK-NEXT: ret856entry:857 %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(858 <vscale x 8 x i8> poison,859 <vscale x 8 x i8> %0,860 i8 9,861 <vscale x 8 x i1> %1,862 iXLen %2)863 864 ret <vscale x 8 x i8> %a865}866 867define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {868; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8:869; CHECK: # %bb.0: # %entry870; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma871; CHECK-NEXT: vmerge.vim v8, v8, 9, v0872; CHECK-NEXT: ret873entry:874 %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(875 <vscale x 16 x i8> poison,876 <vscale x 16 x i8> %0,877 i8 9,878 <vscale x 16 x i1> %1,879 iXLen %2)880 881 ret <vscale x 16 x i8> %a882}883 884define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {885; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8:886; CHECK: # %bb.0: # %entry887; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma888; CHECK-NEXT: vmerge.vim v8, v8, 9, v0889; CHECK-NEXT: ret890entry:891 %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(892 <vscale x 32 x i8> poison,893 <vscale x 32 x i8> %0,894 i8 9,895 <vscale x 32 x i1> %1,896 iXLen %2)897 898 ret <vscale x 32 x i8> %a899}900 901define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {902; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8:903; CHECK: # %bb.0: # %entry904; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma905; CHECK-NEXT: vmerge.vim v8, v8, 9, v0906; CHECK-NEXT: ret907entry:908 %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(909 <vscale x 64 x i8> poison,910 <vscale x 64 x i8> %0,911 i8 9,912 <vscale x 64 x i1> %1,913 iXLen %2)914 915 ret <vscale x 64 x i8> %a916}917 918define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {919; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16:920; CHECK: # %bb.0: # %entry921; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma922; CHECK-NEXT: vmerge.vim v8, v8, 9, v0923; CHECK-NEXT: ret924entry:925 %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(926 <vscale x 1 x i16> poison,927 <vscale x 1 x i16> %0,928 i16 9,929 <vscale x 1 x i1> %1,930 iXLen %2)931 932 ret <vscale x 1 x i16> %a933}934 935define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {936; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16:937; CHECK: # %bb.0: # %entry938; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma939; CHECK-NEXT: vmerge.vim v8, v8, 9, v0940; CHECK-NEXT: ret941entry:942 %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(943 <vscale x 2 x i16> poison,944 <vscale x 2 x i16> %0,945 i16 9,946 <vscale x 2 x i1> %1,947 iXLen %2)948 949 ret <vscale x 2 x i16> %a950}951 952define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {953; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16:954; CHECK: # %bb.0: # %entry955; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma956; CHECK-NEXT: vmerge.vim v8, v8, 9, v0957; CHECK-NEXT: ret958entry:959 %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(960 <vscale x 4 x i16> poison,961 <vscale x 4 x i16> %0,962 i16 9,963 <vscale x 4 x i1> %1,964 iXLen %2)965 966 ret <vscale x 4 x i16> %a967}968 969define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {970; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16:971; CHECK: # %bb.0: # %entry972; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma973; CHECK-NEXT: vmerge.vim v8, v8, 9, v0974; CHECK-NEXT: ret975entry:976 %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(977 <vscale x 8 x i16> poison,978 <vscale x 8 x i16> %0,979 i16 9,980 <vscale x 8 x i1> %1,981 iXLen %2)982 983 ret <vscale x 8 x i16> %a984}985 986define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {987; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16:988; CHECK: # %bb.0: # %entry989; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma990; CHECK-NEXT: vmerge.vim v8, v8, 9, v0991; CHECK-NEXT: ret992entry:993 %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(994 <vscale x 16 x i16> poison,995 <vscale x 16 x i16> %0,996 i16 9,997 <vscale x 16 x i1> %1,998 iXLen %2)999 1000 ret <vscale x 16 x i16> %a1001}1002 1003define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {1004; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16:1005; CHECK: # %bb.0: # %entry1006; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1007; CHECK-NEXT: vmerge.vim v8, v8, 9, v01008; CHECK-NEXT: ret1009entry:1010 %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(1011 <vscale x 32 x i16> poison,1012 <vscale x 32 x i16> %0,1013 i16 9,1014 <vscale x 32 x i1> %1,1015 iXLen %2)1016 1017 ret <vscale x 32 x i16> %a1018}1019 1020define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {1021; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32:1022; CHECK: # %bb.0: # %entry1023; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1024; CHECK-NEXT: vmerge.vim v8, v8, 9, v01025; CHECK-NEXT: ret1026entry:1027 %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(1028 <vscale x 1 x i32> poison,1029 <vscale x 1 x i32> %0,1030 i32 9,1031 <vscale x 1 x i1> %1,1032 iXLen %2)1033 1034 ret <vscale x 1 x i32> %a1035}1036 1037define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {1038; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32:1039; CHECK: # %bb.0: # %entry1040; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1041; CHECK-NEXT: vmerge.vim v8, v8, 9, v01042; CHECK-NEXT: ret1043entry:1044 %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(1045 <vscale x 2 x i32> poison,1046 <vscale x 2 x i32> %0,1047 i32 9,1048 <vscale x 2 x i1> %1,1049 iXLen %2)1050 1051 ret <vscale x 2 x i32> %a1052}1053 1054define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {1055; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32:1056; CHECK: # %bb.0: # %entry1057; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1058; CHECK-NEXT: vmerge.vim v8, v8, 9, v01059; CHECK-NEXT: ret1060entry:1061 %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(1062 <vscale x 4 x i32> poison,1063 <vscale x 4 x i32> %0,1064 i32 9,1065 <vscale x 4 x i1> %1,1066 iXLen %2)1067 1068 ret <vscale x 4 x i32> %a1069}1070 1071define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {1072; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32:1073; CHECK: # %bb.0: # %entry1074; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1075; CHECK-NEXT: vmerge.vim v8, v8, 9, v01076; CHECK-NEXT: ret1077entry:1078 %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(1079 <vscale x 8 x i32> poison,1080 <vscale x 8 x i32> %0,1081 i32 9,1082 <vscale x 8 x i1> %1,1083 iXLen %2)1084 1085 ret <vscale x 8 x i32> %a1086}1087 1088define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {1089; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32:1090; CHECK: # %bb.0: # %entry1091; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1092; CHECK-NEXT: vmerge.vim v8, v8, 9, v01093; CHECK-NEXT: ret1094entry:1095 %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(1096 <vscale x 16 x i32> poison,1097 <vscale x 16 x i32> %0,1098 i32 9,1099 <vscale x 16 x i1> %1,1100 iXLen %2)1101 1102 ret <vscale x 16 x i32> %a1103}1104 1105define <vscale x 1 x i64> @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {1106; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64:1107; CHECK: # %bb.0: # %entry1108; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1109; CHECK-NEXT: vmerge.vim v8, v8, 9, v01110; CHECK-NEXT: ret1111entry:1112 %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(1113 <vscale x 1 x i64> poison,1114 <vscale x 1 x i64> %0,1115 i64 9,1116 <vscale x 1 x i1> %1,1117 iXLen %2)1118 1119 ret <vscale x 1 x i64> %a1120}1121 1122define <vscale x 2 x i64> @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {1123; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64:1124; CHECK: # %bb.0: # %entry1125; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1126; CHECK-NEXT: vmerge.vim v8, v8, 9, v01127; CHECK-NEXT: ret1128entry:1129 %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(1130 <vscale x 2 x i64> poison,1131 <vscale x 2 x i64> %0,1132 i64 9,1133 <vscale x 2 x i1> %1,1134 iXLen %2)1135 1136 ret <vscale x 2 x i64> %a1137}1138 1139define <vscale x 4 x i64> @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {1140; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64:1141; CHECK: # %bb.0: # %entry1142; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1143; CHECK-NEXT: vmerge.vim v8, v8, 9, v01144; CHECK-NEXT: ret1145entry:1146 %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(1147 <vscale x 4 x i64> poison,1148 <vscale x 4 x i64> %0,1149 i64 9,1150 <vscale x 4 x i1> %1,1151 iXLen %2)1152 1153 ret <vscale x 4 x i64> %a1154}1155 1156define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {1157; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:1158; CHECK: # %bb.0: # %entry1159; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1160; CHECK-NEXT: vmerge.vim v8, v8, 9, v01161; CHECK-NEXT: ret1162entry:1163 %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(1164 <vscale x 8 x i64> poison,1165 <vscale x 8 x i64> %0,1166 i64 9,1167 <vscale x 8 x i1> %1,1168 iXLen %2)1169 1170 ret <vscale x 8 x i64> %a1171}1172 1173define <vscale x 1 x half> @intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1174; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16:1175; CHECK: # %bb.0: # %entry1176; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1177; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01178; CHECK-NEXT: ret1179entry:1180 %a = call <vscale x 1 x half> @llvm.riscv.vmerge.nxv1f16.nxv1f16(1181 <vscale x 1 x half> poison,1182 <vscale x 1 x half> %0,1183 <vscale x 1 x half> %1,1184 <vscale x 1 x i1> %2,1185 iXLen %3)1186 1187 ret <vscale x 1 x half> %a1188}1189 1190define <vscale x 2 x half> @intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1191; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16:1192; CHECK: # %bb.0: # %entry1193; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1194; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01195; CHECK-NEXT: ret1196entry:1197 %a = call <vscale x 2 x half> @llvm.riscv.vmerge.nxv2f16.nxv2f16(1198 <vscale x 2 x half> poison,1199 <vscale x 2 x half> %0,1200 <vscale x 2 x half> %1,1201 <vscale x 2 x i1> %2,1202 iXLen %3)1203 1204 ret <vscale x 2 x half> %a1205}1206 1207define <vscale x 4 x half> @intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1208; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16:1209; CHECK: # %bb.0: # %entry1210; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1211; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01212; CHECK-NEXT: ret1213entry:1214 %a = call <vscale x 4 x half> @llvm.riscv.vmerge.nxv4f16.nxv4f16(1215 <vscale x 4 x half> poison,1216 <vscale x 4 x half> %0,1217 <vscale x 4 x half> %1,1218 <vscale x 4 x i1> %2,1219 iXLen %3)1220 1221 ret <vscale x 4 x half> %a1222}1223 1224define <vscale x 8 x half> @intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1225; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16:1226; CHECK: # %bb.0: # %entry1227; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1228; CHECK-NEXT: vmerge.vvm v8, v8, v10, v01229; CHECK-NEXT: ret1230entry:1231 %a = call <vscale x 8 x half> @llvm.riscv.vmerge.nxv8f16.nxv8f16(1232 <vscale x 8 x half> poison,1233 <vscale x 8 x half> %0,1234 <vscale x 8 x half> %1,1235 <vscale x 8 x i1> %2,1236 iXLen %3)1237 1238 ret <vscale x 8 x half> %a1239}1240 1241define <vscale x 16 x half> @intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1242; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16:1243; CHECK: # %bb.0: # %entry1244; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1245; CHECK-NEXT: vmerge.vvm v8, v8, v12, v01246; CHECK-NEXT: ret1247entry:1248 %a = call <vscale x 16 x half> @llvm.riscv.vmerge.nxv16f16.nxv16f16(1249 <vscale x 16 x half> poison,1250 <vscale x 16 x half> %0,1251 <vscale x 16 x half> %1,1252 <vscale x 16 x i1> %2,1253 iXLen %3)1254 1255 ret <vscale x 16 x half> %a1256}1257 1258define <vscale x 32 x half> @intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1259; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16:1260; CHECK: # %bb.0: # %entry1261; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1262; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01263; CHECK-NEXT: ret1264entry:1265 %a = call <vscale x 32 x half> @llvm.riscv.vmerge.nxv32f16.nxv32f16(1266 <vscale x 32 x half> poison,1267 <vscale x 32 x half> %0,1268 <vscale x 32 x half> %1,1269 <vscale x 32 x i1> %2,1270 iXLen %3)1271 1272 ret <vscale x 32 x half> %a1273}1274 1275define <vscale x 1 x bfloat> @intrinsic_vmerge_vvm_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1276; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1bf16_nxv1bf16_nxv1bf16:1277; CHECK: # %bb.0: # %entry1278; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1279; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01280; CHECK-NEXT: ret1281entry:1282 %a = call <vscale x 1 x bfloat> @llvm.riscv.vmerge.nxv1bf16.nxv1bf16(1283 <vscale x 1 x bfloat> poison,1284 <vscale x 1 x bfloat> %0,1285 <vscale x 1 x bfloat> %1,1286 <vscale x 1 x i1> %2,1287 iXLen %3)1288 1289 ret <vscale x 1 x bfloat> %a1290}1291 1292define <vscale x 2 x bfloat> @intrinsic_vmerge_vvm_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1293; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2bf16_nxv2bf16_nxv2bf16:1294; CHECK: # %bb.0: # %entry1295; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1296; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01297; CHECK-NEXT: ret1298entry:1299 %a = call <vscale x 2 x bfloat> @llvm.riscv.vmerge.nxv2bf16.nxv2bf16(1300 <vscale x 2 x bfloat> poison,1301 <vscale x 2 x bfloat> %0,1302 <vscale x 2 x bfloat> %1,1303 <vscale x 2 x i1> %2,1304 iXLen %3)1305 1306 ret <vscale x 2 x bfloat> %a1307}1308 1309define <vscale x 4 x bfloat> @intrinsic_vmerge_vvm_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1310; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4bf16_nxv4bf16_nxv4bf16:1311; CHECK: # %bb.0: # %entry1312; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1313; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01314; CHECK-NEXT: ret1315entry:1316 %a = call <vscale x 4 x bfloat> @llvm.riscv.vmerge.nxv4bf16.nxv4bf16(1317 <vscale x 4 x bfloat> poison,1318 <vscale x 4 x bfloat> %0,1319 <vscale x 4 x bfloat> %1,1320 <vscale x 4 x i1> %2,1321 iXLen %3)1322 1323 ret <vscale x 4 x bfloat> %a1324}1325 1326define <vscale x 8 x bfloat> @intrinsic_vmerge_vvm_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1327; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8bf16_nxv8bf16_nxv8bf16:1328; CHECK: # %bb.0: # %entry1329; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1330; CHECK-NEXT: vmerge.vvm v8, v8, v10, v01331; CHECK-NEXT: ret1332entry:1333 %a = call <vscale x 8 x bfloat> @llvm.riscv.vmerge.nxv8bf16.nxv8bf16(1334 <vscale x 8 x bfloat> poison,1335 <vscale x 8 x bfloat> %0,1336 <vscale x 8 x bfloat> %1,1337 <vscale x 8 x i1> %2,1338 iXLen %3)1339 1340 ret <vscale x 8 x bfloat> %a1341}1342 1343define <vscale x 16 x bfloat> @intrinsic_vmerge_vvm_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1344; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16bf16_nxv16bf16_nxv16bf16:1345; CHECK: # %bb.0: # %entry1346; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1347; CHECK-NEXT: vmerge.vvm v8, v8, v12, v01348; CHECK-NEXT: ret1349entry:1350 %a = call <vscale x 16 x bfloat> @llvm.riscv.vmerge.nxv16bf16.nxv16bf16(1351 <vscale x 16 x bfloat> poison,1352 <vscale x 16 x bfloat> %0,1353 <vscale x 16 x bfloat> %1,1354 <vscale x 16 x i1> %2,1355 iXLen %3)1356 1357 ret <vscale x 16 x bfloat> %a1358}1359 1360define <vscale x 32 x bfloat> @intrinsic_vmerge_vvm_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1361; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32bf16_nxv32bf16_nxv32bf16:1362; CHECK: # %bb.0: # %entry1363; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1364; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01365; CHECK-NEXT: ret1366entry:1367 %a = call <vscale x 32 x bfloat> @llvm.riscv.vmerge.nxv32bf16.nxv32bf16(1368 <vscale x 32 x bfloat> poison,1369 <vscale x 32 x bfloat> %0,1370 <vscale x 32 x bfloat> %1,1371 <vscale x 32 x i1> %2,1372 iXLen %3)1373 1374 ret <vscale x 32 x bfloat> %a1375}1376 1377define <vscale x 1 x float> @intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1378; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32:1379; CHECK: # %bb.0: # %entry1380; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1381; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01382; CHECK-NEXT: ret1383entry:1384 %a = call <vscale x 1 x float> @llvm.riscv.vmerge.nxv1f32.nxv1f32(1385 <vscale x 1 x float> poison,1386 <vscale x 1 x float> %0,1387 <vscale x 1 x float> %1,1388 <vscale x 1 x i1> %2,1389 iXLen %3)1390 1391 ret <vscale x 1 x float> %a1392}1393 1394define <vscale x 2 x float> @intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1395; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32:1396; CHECK: # %bb.0: # %entry1397; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1398; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01399; CHECK-NEXT: ret1400entry:1401 %a = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(1402 <vscale x 2 x float> poison,1403 <vscale x 2 x float> %0,1404 <vscale x 2 x float> %1,1405 <vscale x 2 x i1> %2,1406 iXLen %3)1407 1408 ret <vscale x 2 x float> %a1409}1410 1411define <vscale x 4 x float> @intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1412; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32:1413; CHECK: # %bb.0: # %entry1414; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1415; CHECK-NEXT: vmerge.vvm v8, v8, v10, v01416; CHECK-NEXT: ret1417entry:1418 %a = call <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32.nxv4f32(1419 <vscale x 4 x float> poison,1420 <vscale x 4 x float> %0,1421 <vscale x 4 x float> %1,1422 <vscale x 4 x i1> %2,1423 iXLen %3)1424 1425 ret <vscale x 4 x float> %a1426}1427 1428define <vscale x 8 x float> @intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1429; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32:1430; CHECK: # %bb.0: # %entry1431; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1432; CHECK-NEXT: vmerge.vvm v8, v8, v12, v01433; CHECK-NEXT: ret1434entry:1435 %a = call <vscale x 8 x float> @llvm.riscv.vmerge.nxv8f32.nxv8f32(1436 <vscale x 8 x float> poison,1437 <vscale x 8 x float> %0,1438 <vscale x 8 x float> %1,1439 <vscale x 8 x i1> %2,1440 iXLen %3)1441 1442 ret <vscale x 8 x float> %a1443}1444 1445define <vscale x 16 x float> @intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1446; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32:1447; CHECK: # %bb.0: # %entry1448; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1449; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01450; CHECK-NEXT: ret1451entry:1452 %a = call <vscale x 16 x float> @llvm.riscv.vmerge.nxv16f32.nxv16f32(1453 <vscale x 16 x float> poison,1454 <vscale x 16 x float> %0,1455 <vscale x 16 x float> %1,1456 <vscale x 16 x i1> %2,1457 iXLen %3)1458 1459 ret <vscale x 16 x float> %a1460}1461 1462define <vscale x 1 x double> @intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1463; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64:1464; CHECK: # %bb.0: # %entry1465; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1466; CHECK-NEXT: vmerge.vvm v8, v8, v9, v01467; CHECK-NEXT: ret1468entry:1469 %a = call <vscale x 1 x double> @llvm.riscv.vmerge.nxv1f64.nxv1f64(1470 <vscale x 1 x double> poison,1471 <vscale x 1 x double> %0,1472 <vscale x 1 x double> %1,1473 <vscale x 1 x i1> %2,1474 iXLen %3)1475 1476 ret <vscale x 1 x double> %a1477}1478 1479define <vscale x 2 x double> @intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1480; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64:1481; CHECK: # %bb.0: # %entry1482; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1483; CHECK-NEXT: vmerge.vvm v8, v8, v10, v01484; CHECK-NEXT: ret1485entry:1486 %a = call <vscale x 2 x double> @llvm.riscv.vmerge.nxv2f64.nxv2f64(1487 <vscale x 2 x double> poison,1488 <vscale x 2 x double> %0,1489 <vscale x 2 x double> %1,1490 <vscale x 2 x i1> %2,1491 iXLen %3)1492 1493 ret <vscale x 2 x double> %a1494}1495 1496define <vscale x 4 x double> @intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1497; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64:1498; CHECK: # %bb.0: # %entry1499; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1500; CHECK-NEXT: vmerge.vvm v8, v8, v12, v01501; CHECK-NEXT: ret1502entry:1503 %a = call <vscale x 4 x double> @llvm.riscv.vmerge.nxv4f64.nxv4f64(1504 <vscale x 4 x double> poison,1505 <vscale x 4 x double> %0,1506 <vscale x 4 x double> %1,1507 <vscale x 4 x i1> %2,1508 iXLen %3)1509 1510 ret <vscale x 4 x double> %a1511}1512 1513define <vscale x 8 x double> @intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1514; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64:1515; CHECK: # %bb.0: # %entry1516; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1517; CHECK-NEXT: vmerge.vvm v8, v8, v16, v01518; CHECK-NEXT: ret1519entry:1520 %a = call <vscale x 8 x double> @llvm.riscv.vmerge.nxv8f64.nxv8f64(1521 <vscale x 8 x double> poison,1522 <vscale x 8 x double> %0,1523 <vscale x 8 x double> %1,1524 <vscale x 8 x i1> %2,1525 iXLen %3)1526 1527 ret <vscale x 8 x double> %a1528}1529