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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmfle_vv_nxv1bf16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vmfle.vv v0, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16(15 <vscale x 1 x bfloat> %0,16 <vscale x 1 x bfloat> %1,17 iXLen %2)18 19 ret <vscale x 1 x i1> %a20}21 22define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1bf16_nxv1bf16(<vscale x 1 x i1> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x bfloat> %3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1bf16_nxv1bf16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu26; CHECK-NEXT: vmv1r.v v11, v027; CHECK-NEXT: vmfle.vv v0, v8, v928; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t29; CHECK-NEXT: vmv1r.v v0, v1130; CHECK-NEXT: ret31entry:32 %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16(33 <vscale x 1 x bfloat> %1,34 <vscale x 1 x bfloat> %2,35 iXLen %4)36 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16(37 <vscale x 1 x i1> %0,38 <vscale x 1 x bfloat> %2,39 <vscale x 1 x bfloat> %3,40 <vscale x 1 x i1> %mask,41 iXLen %4)42 43 ret <vscale x 1 x i1> %a44}45 46define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmfle_vv_nxv2bf16_nxv2bf16:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma50; CHECK-NEXT: vmfle.vv v0, v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16(54 <vscale x 2 x bfloat> %0,55 <vscale x 2 x bfloat> %1,56 iXLen %2)57 58 ret <vscale x 2 x i1> %a59}60 61define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2bf16_nxv2bf16(<vscale x 2 x i1> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x bfloat> %3, iXLen %4) nounwind {62; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2bf16_nxv2bf16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu65; CHECK-NEXT: vmv1r.v v11, v066; CHECK-NEXT: vmfle.vv v0, v8, v967; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t68; CHECK-NEXT: vmv1r.v v0, v1169; CHECK-NEXT: ret70entry:71 %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16(72 <vscale x 2 x bfloat> %1,73 <vscale x 2 x bfloat> %2,74 iXLen %4)75 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16(76 <vscale x 2 x i1> %0,77 <vscale x 2 x bfloat> %2,78 <vscale x 2 x bfloat> %3,79 <vscale x 2 x i1> %mask,80 iXLen %4)81 82 ret <vscale x 2 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vmfle_vv_nxv4bf16_nxv4bf16:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma89; CHECK-NEXT: vmfle.vv v0, v8, v990; CHECK-NEXT: ret91entry:92 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16(93 <vscale x 4 x bfloat> %0,94 <vscale x 4 x bfloat> %1,95 iXLen %2)96 97 ret <vscale x 4 x i1> %a98}99 100define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4bf16_nxv4bf16(<vscale x 4 x i1> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x bfloat> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4bf16_nxv4bf16:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu104; CHECK-NEXT: vmv1r.v v11, v0105; CHECK-NEXT: vmfle.vv v0, v8, v9106; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t107; CHECK-NEXT: vmv.v.v v0, v11108; CHECK-NEXT: ret109entry:110 %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16(111 <vscale x 4 x bfloat> %1,112 <vscale x 4 x bfloat> %2,113 iXLen %4)114 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16(115 <vscale x 4 x i1> %0,116 <vscale x 4 x bfloat> %2,117 <vscale x 4 x bfloat> %3,118 <vscale x 4 x i1> %mask,119 iXLen %4)120 121 ret <vscale x 4 x i1> %a122}123 124define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vmfle_vv_nxv8bf16_nxv8bf16:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma128; CHECK-NEXT: vmfle.vv v0, v8, v10129; CHECK-NEXT: ret130entry:131 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16(132 <vscale x 8 x bfloat> %0,133 <vscale x 8 x bfloat> %1,134 iXLen %2)135 136 ret <vscale x 8 x i1> %a137}138 139define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8bf16_nxv8bf16(<vscale x 8 x i1> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8bf16_nxv8bf16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu143; CHECK-NEXT: vmv1r.v v14, v0144; CHECK-NEXT: vmfle.vv v0, v8, v10145; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t146; CHECK-NEXT: vmv1r.v v0, v14147; CHECK-NEXT: ret148entry:149 %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16(150 <vscale x 8 x bfloat> %1,151 <vscale x 8 x bfloat> %2,152 iXLen %4)153 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8bf16(154 <vscale x 8 x i1> %0,155 <vscale x 8 x bfloat> %2,156 <vscale x 8 x bfloat> %3,157 <vscale x 8 x i1> %mask,158 iXLen %4)159 160 ret <vscale x 8 x i1> %a161}162 163define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vmfle_vv_nxv16bf16_nxv16bf16:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma167; CHECK-NEXT: vmfle.vv v0, v8, v12168; CHECK-NEXT: ret169entry:170 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16(171 <vscale x 16 x bfloat> %0,172 <vscale x 16 x bfloat> %1,173 iXLen %2)174 175 ret <vscale x 16 x i1> %a176}177 178define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16bf16_nxv16bf16(<vscale x 16 x i1> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x bfloat> %3, iXLen %4) nounwind {179; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16bf16_nxv16bf16:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu182; CHECK-NEXT: vmv1r.v v20, v0183; CHECK-NEXT: vmfle.vv v0, v8, v12184; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t185; CHECK-NEXT: vmv1r.v v0, v20186; CHECK-NEXT: ret187entry:188 %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16(189 <vscale x 16 x bfloat> %1,190 <vscale x 16 x bfloat> %2,191 iXLen %4)192 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16bf16(193 <vscale x 16 x i1> %0,194 <vscale x 16 x bfloat> %2,195 <vscale x 16 x bfloat> %3,196 <vscale x 16 x i1> %mask,197 iXLen %4)198 199 ret <vscale x 16 x i1> %a200}201 202define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmfle_vf_nxv1bf16_bf16:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma206; CHECK-NEXT: vmfle.vf v0, v8, fa0207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1bf16.bf16(210 <vscale x 1 x bfloat> %0,211 bfloat %1,212 iXLen %2)213 214 ret <vscale x 1 x i1> %a215}216 217define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1bf16_bf16(<vscale x 1 x i1> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {218; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1bf16_bf16:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu221; CHECK-NEXT: vmv1r.v v10, v0222; CHECK-NEXT: vmv1r.v v0, v9223; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t224; CHECK-NEXT: vmv1r.v v0, v10225; CHECK-NEXT: ret226entry:227 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1bf16.bf16(228 <vscale x 1 x i1> %0,229 <vscale x 1 x bfloat> %1,230 bfloat %2,231 <vscale x 1 x i1> %3,232 iXLen %4)233 234 ret <vscale x 1 x i1> %a235}236 237define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {238; CHECK-LABEL: intrinsic_vmfle_vf_nxv2bf16_bf16:239; CHECK: # %bb.0: # %entry240; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma241; CHECK-NEXT: vmfle.vf v0, v8, fa0242; CHECK-NEXT: ret243entry:244 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2bf16.bf16(245 <vscale x 2 x bfloat> %0,246 bfloat %1,247 iXLen %2)248 249 ret <vscale x 2 x i1> %a250}251 252define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2bf16_bf16(<vscale x 2 x i1> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {253; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2bf16_bf16:254; CHECK: # %bb.0: # %entry255; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu256; CHECK-NEXT: vmv1r.v v10, v0257; CHECK-NEXT: vmv1r.v v0, v9258; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t259; CHECK-NEXT: vmv1r.v v0, v10260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2bf16.bf16(263 <vscale x 2 x i1> %0,264 <vscale x 2 x bfloat> %1,265 bfloat %2,266 <vscale x 2 x i1> %3,267 iXLen %4)268 269 ret <vscale x 2 x i1> %a270}271 272define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vmfle_vf_nxv4bf16_bf16:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma276; CHECK-NEXT: vmfle.vf v0, v8, fa0277; CHECK-NEXT: ret278entry:279 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4bf16.bf16(280 <vscale x 4 x bfloat> %0,281 bfloat %1,282 iXLen %2)283 284 ret <vscale x 4 x i1> %a285}286 287define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4bf16_bf16(<vscale x 4 x i1> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4bf16_bf16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu291; CHECK-NEXT: vmv1r.v v10, v0292; CHECK-NEXT: vmv1r.v v0, v9293; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t294; CHECK-NEXT: vmv.v.v v0, v10295; CHECK-NEXT: ret296entry:297 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4bf16.bf16(298 <vscale x 4 x i1> %0,299 <vscale x 4 x bfloat> %1,300 bfloat %2,301 <vscale x 4 x i1> %3,302 iXLen %4)303 304 ret <vscale x 4 x i1> %a305}306 307define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {308; CHECK-LABEL: intrinsic_vmfle_vf_nxv8bf16_bf16:309; CHECK: # %bb.0: # %entry310; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma311; CHECK-NEXT: vmfle.vf v0, v8, fa0312; CHECK-NEXT: ret313entry:314 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8bf16.bf16(315 <vscale x 8 x bfloat> %0,316 bfloat %1,317 iXLen %2)318 319 ret <vscale x 8 x i1> %a320}321 322define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8bf16_bf16(<vscale x 8 x i1> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {323; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8bf16_bf16:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu326; CHECK-NEXT: vmv1r.v v11, v0327; CHECK-NEXT: vmv1r.v v0, v10328; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t329; CHECK-NEXT: vmv1r.v v0, v11330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8bf16.bf16(333 <vscale x 8 x i1> %0,334 <vscale x 8 x bfloat> %1,335 bfloat %2,336 <vscale x 8 x i1> %3,337 iXLen %4)338 339 ret <vscale x 8 x i1> %a340}341 342define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {343; CHECK-LABEL: intrinsic_vmfle_vf_nxv16bf16_bf16:344; CHECK: # %bb.0: # %entry345; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma346; CHECK-NEXT: vmfle.vf v0, v8, fa0347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16bf16.bf16(350 <vscale x 16 x bfloat> %0,351 bfloat %1,352 iXLen %2)353 354 ret <vscale x 16 x i1> %a355}356 357define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16bf16_bf16(<vscale x 16 x i1> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {358; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16bf16_bf16:359; CHECK: # %bb.0: # %entry360; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu361; CHECK-NEXT: vmv1r.v v13, v0362; CHECK-NEXT: vmv1r.v v0, v12363; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t364; CHECK-NEXT: vmv1r.v v0, v13365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16bf16.bf16(368 <vscale x 16 x i1> %0,369 <vscale x 16 x bfloat> %1,370 bfloat %2,371 <vscale x 16 x i1> %3,372 iXLen %4)373 374 ret <vscale x 16 x i1> %a375}376 377