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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vmfle.vv v0, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(15 <vscale x 1 x half> %0,16 <vscale x 1 x half> %1,17 iXLen %2)18 19 ret <vscale x 1 x i1> %a20}21 22define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu26; CHECK-NEXT: vmv1r.v v11, v027; CHECK-NEXT: vmfle.vv v0, v8, v928; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t29; CHECK-NEXT: vmv1r.v v0, v1130; CHECK-NEXT: ret31entry:32 %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(33 <vscale x 1 x half> %1,34 <vscale x 1 x half> %2,35 iXLen %4)36 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(37 <vscale x 1 x i1> %0,38 <vscale x 1 x half> %2,39 <vscale x 1 x half> %3,40 <vscale x 1 x i1> %mask,41 iXLen %4)42 43 ret <vscale x 1 x i1> %a44}45 46define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma50; CHECK-NEXT: vmfle.vv v0, v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(54 <vscale x 2 x half> %0,55 <vscale x 2 x half> %1,56 iXLen %2)57 58 ret <vscale x 2 x i1> %a59}60 61define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {62; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu65; CHECK-NEXT: vmv1r.v v11, v066; CHECK-NEXT: vmfle.vv v0, v8, v967; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t68; CHECK-NEXT: vmv1r.v v0, v1169; CHECK-NEXT: ret70entry:71 %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(72 <vscale x 2 x half> %1,73 <vscale x 2 x half> %2,74 iXLen %4)75 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(76 <vscale x 2 x i1> %0,77 <vscale x 2 x half> %2,78 <vscale x 2 x half> %3,79 <vscale x 2 x i1> %mask,80 iXLen %4)81 82 ret <vscale x 2 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma89; CHECK-NEXT: vmfle.vv v0, v8, v990; CHECK-NEXT: ret91entry:92 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(93 <vscale x 4 x half> %0,94 <vscale x 4 x half> %1,95 iXLen %2)96 97 ret <vscale x 4 x i1> %a98}99 100define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu104; CHECK-NEXT: vmv1r.v v11, v0105; CHECK-NEXT: vmfle.vv v0, v8, v9106; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t107; CHECK-NEXT: vmv.v.v v0, v11108; CHECK-NEXT: ret109entry:110 %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(111 <vscale x 4 x half> %1,112 <vscale x 4 x half> %2,113 iXLen %4)114 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(115 <vscale x 4 x i1> %0,116 <vscale x 4 x half> %2,117 <vscale x 4 x half> %3,118 <vscale x 4 x i1> %mask,119 iXLen %4)120 121 ret <vscale x 4 x i1> %a122}123 124define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma128; CHECK-NEXT: vmfle.vv v0, v8, v10129; CHECK-NEXT: ret130entry:131 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(132 <vscale x 8 x half> %0,133 <vscale x 8 x half> %1,134 iXLen %2)135 136 ret <vscale x 8 x i1> %a137}138 139define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu143; CHECK-NEXT: vmv1r.v v14, v0144; CHECK-NEXT: vmfle.vv v0, v8, v10145; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t146; CHECK-NEXT: vmv1r.v v0, v14147; CHECK-NEXT: ret148entry:149 %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(150 <vscale x 8 x half> %1,151 <vscale x 8 x half> %2,152 iXLen %4)153 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(154 <vscale x 8 x i1> %0,155 <vscale x 8 x half> %2,156 <vscale x 8 x half> %3,157 <vscale x 8 x i1> %mask,158 iXLen %4)159 160 ret <vscale x 8 x i1> %a161}162 163define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma167; CHECK-NEXT: vmfle.vv v0, v8, v12168; CHECK-NEXT: ret169entry:170 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(171 <vscale x 16 x half> %0,172 <vscale x 16 x half> %1,173 iXLen %2)174 175 ret <vscale x 16 x i1> %a176}177 178define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {179; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu182; CHECK-NEXT: vmv1r.v v20, v0183; CHECK-NEXT: vmfle.vv v0, v8, v12184; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t185; CHECK-NEXT: vmv1r.v v0, v20186; CHECK-NEXT: ret187entry:188 %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(189 <vscale x 16 x half> %1,190 <vscale x 16 x half> %2,191 iXLen %4)192 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(193 <vscale x 16 x i1> %0,194 <vscale x 16 x half> %2,195 <vscale x 16 x half> %3,196 <vscale x 16 x i1> %mask,197 iXLen %4)198 199 ret <vscale x 16 x i1> %a200}201 202define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma206; CHECK-NEXT: vmfle.vv v0, v8, v9207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(210 <vscale x 1 x float> %0,211 <vscale x 1 x float> %1,212 iXLen %2)213 214 ret <vscale x 1 x i1> %a215}216 217define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {218; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu221; CHECK-NEXT: vmv1r.v v11, v0222; CHECK-NEXT: vmfle.vv v0, v8, v9223; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t224; CHECK-NEXT: vmv1r.v v0, v11225; CHECK-NEXT: ret226entry:227 %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(228 <vscale x 1 x float> %1,229 <vscale x 1 x float> %2,230 iXLen %4)231 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(232 <vscale x 1 x i1> %0,233 <vscale x 1 x float> %2,234 <vscale x 1 x float> %3,235 <vscale x 1 x i1> %mask,236 iXLen %4)237 238 ret <vscale x 1 x i1> %a239}240 241define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {242; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma245; CHECK-NEXT: vmfle.vv v0, v8, v9246; CHECK-NEXT: ret247entry:248 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(249 <vscale x 2 x float> %0,250 <vscale x 2 x float> %1,251 iXLen %2)252 253 ret <vscale x 2 x i1> %a254}255 256define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {257; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:258; CHECK: # %bb.0: # %entry259; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu260; CHECK-NEXT: vmv1r.v v11, v0261; CHECK-NEXT: vmfle.vv v0, v8, v9262; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t263; CHECK-NEXT: vmv.v.v v0, v11264; CHECK-NEXT: ret265entry:266 %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(267 <vscale x 2 x float> %1,268 <vscale x 2 x float> %2,269 iXLen %4)270 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(271 <vscale x 2 x i1> %0,272 <vscale x 2 x float> %2,273 <vscale x 2 x float> %3,274 <vscale x 2 x i1> %mask,275 iXLen %4)276 277 ret <vscale x 2 x i1> %a278}279 280define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {281; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32:282; CHECK: # %bb.0: # %entry283; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma284; CHECK-NEXT: vmfle.vv v0, v8, v10285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(288 <vscale x 4 x float> %0,289 <vscale x 4 x float> %1,290 iXLen %2)291 292 ret <vscale x 4 x i1> %a293}294 295define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu299; CHECK-NEXT: vmv1r.v v14, v0300; CHECK-NEXT: vmfle.vv v0, v8, v10301; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t302; CHECK-NEXT: vmv1r.v v0, v14303; CHECK-NEXT: ret304entry:305 %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(306 <vscale x 4 x float> %1,307 <vscale x 4 x float> %2,308 iXLen %4)309 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(310 <vscale x 4 x i1> %0,311 <vscale x 4 x float> %2,312 <vscale x 4 x float> %3,313 <vscale x 4 x i1> %mask,314 iXLen %4)315 316 ret <vscale x 4 x i1> %a317}318 319define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {320; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32:321; CHECK: # %bb.0: # %entry322; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma323; CHECK-NEXT: vmfle.vv v0, v8, v12324; CHECK-NEXT: ret325entry:326 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(327 <vscale x 8 x float> %0,328 <vscale x 8 x float> %1,329 iXLen %2)330 331 ret <vscale x 8 x i1> %a332}333 334define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {335; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu338; CHECK-NEXT: vmv1r.v v20, v0339; CHECK-NEXT: vmfle.vv v0, v8, v12340; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t341; CHECK-NEXT: vmv1r.v v0, v20342; CHECK-NEXT: ret343entry:344 %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(345 <vscale x 8 x float> %1,346 <vscale x 8 x float> %2,347 iXLen %4)348 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(349 <vscale x 8 x i1> %0,350 <vscale x 8 x float> %2,351 <vscale x 8 x float> %3,352 <vscale x 8 x i1> %mask,353 iXLen %4)354 355 ret <vscale x 8 x i1> %a356}357 358define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {359; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma362; CHECK-NEXT: vmfle.vv v0, v8, v9363; CHECK-NEXT: ret364entry:365 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(366 <vscale x 1 x double> %0,367 <vscale x 1 x double> %1,368 iXLen %2)369 370 ret <vscale x 1 x i1> %a371}372 373define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {374; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:375; CHECK: # %bb.0: # %entry376; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu377; CHECK-NEXT: vmv1r.v v11, v0378; CHECK-NEXT: vmfle.vv v0, v8, v9379; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t380; CHECK-NEXT: vmv.v.v v0, v11381; CHECK-NEXT: ret382entry:383 %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(384 <vscale x 1 x double> %1,385 <vscale x 1 x double> %2,386 iXLen %4)387 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(388 <vscale x 1 x i1> %0,389 <vscale x 1 x double> %2,390 <vscale x 1 x double> %3,391 <vscale x 1 x i1> %mask,392 iXLen %4)393 394 ret <vscale x 1 x i1> %a395}396 397define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma401; CHECK-NEXT: vmfle.vv v0, v8, v10402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(405 <vscale x 2 x double> %0,406 <vscale x 2 x double> %1,407 iXLen %2)408 409 ret <vscale x 2 x i1> %a410}411 412define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {413; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu416; CHECK-NEXT: vmv1r.v v14, v0417; CHECK-NEXT: vmfle.vv v0, v8, v10418; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t419; CHECK-NEXT: vmv1r.v v0, v14420; CHECK-NEXT: ret421entry:422 %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(423 <vscale x 2 x double> %1,424 <vscale x 2 x double> %2,425 iXLen %4)426 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(427 <vscale x 2 x i1> %0,428 <vscale x 2 x double> %2,429 <vscale x 2 x double> %3,430 <vscale x 2 x i1> %mask,431 iXLen %4)432 433 ret <vscale x 2 x i1> %a434}435 436define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma440; CHECK-NEXT: vmfle.vv v0, v8, v12441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(444 <vscale x 4 x double> %0,445 <vscale x 4 x double> %1,446 iXLen %2)447 448 ret <vscale x 4 x i1> %a449}450 451define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {452; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu455; CHECK-NEXT: vmv1r.v v20, v0456; CHECK-NEXT: vmfle.vv v0, v8, v12457; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t458; CHECK-NEXT: vmv1r.v v0, v20459; CHECK-NEXT: ret460entry:461 %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(462 <vscale x 4 x double> %1,463 <vscale x 4 x double> %2,464 iXLen %4)465 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(466 <vscale x 4 x i1> %0,467 <vscale x 4 x double> %2,468 <vscale x 4 x double> %3,469 <vscale x 4 x i1> %mask,470 iXLen %4)471 472 ret <vscale x 4 x i1> %a473}474 475define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:477; CHECK: # %bb.0: # %entry478; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma479; CHECK-NEXT: vmfle.vf v0, v8, fa0480; CHECK-NEXT: ret481entry:482 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(483 <vscale x 1 x half> %0,484 half %1,485 iXLen %2)486 487 ret <vscale x 1 x i1> %a488}489 490define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {491; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:492; CHECK: # %bb.0: # %entry493; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu494; CHECK-NEXT: vmv1r.v v10, v0495; CHECK-NEXT: vmv1r.v v0, v9496; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t497; CHECK-NEXT: vmv1r.v v0, v10498; CHECK-NEXT: ret499entry:500 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(501 <vscale x 1 x i1> %0,502 <vscale x 1 x half> %1,503 half %2,504 <vscale x 1 x i1> %3,505 iXLen %4)506 507 ret <vscale x 1 x i1> %a508}509 510define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {511; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:512; CHECK: # %bb.0: # %entry513; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma514; CHECK-NEXT: vmfle.vf v0, v8, fa0515; CHECK-NEXT: ret516entry:517 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(518 <vscale x 2 x half> %0,519 half %1,520 iXLen %2)521 522 ret <vscale x 2 x i1> %a523}524 525define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {526; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:527; CHECK: # %bb.0: # %entry528; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu529; CHECK-NEXT: vmv1r.v v10, v0530; CHECK-NEXT: vmv1r.v v0, v9531; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t532; CHECK-NEXT: vmv1r.v v0, v10533; CHECK-NEXT: ret534entry:535 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(536 <vscale x 2 x i1> %0,537 <vscale x 2 x half> %1,538 half %2,539 <vscale x 2 x i1> %3,540 iXLen %4)541 542 ret <vscale x 2 x i1> %a543}544 545define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {546; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:547; CHECK: # %bb.0: # %entry548; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma549; CHECK-NEXT: vmfle.vf v0, v8, fa0550; CHECK-NEXT: ret551entry:552 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(553 <vscale x 4 x half> %0,554 half %1,555 iXLen %2)556 557 ret <vscale x 4 x i1> %a558}559 560define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {561; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:562; CHECK: # %bb.0: # %entry563; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu564; CHECK-NEXT: vmv1r.v v10, v0565; CHECK-NEXT: vmv1r.v v0, v9566; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t567; CHECK-NEXT: vmv.v.v v0, v10568; CHECK-NEXT: ret569entry:570 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(571 <vscale x 4 x i1> %0,572 <vscale x 4 x half> %1,573 half %2,574 <vscale x 4 x i1> %3,575 iXLen %4)576 577 ret <vscale x 4 x i1> %a578}579 580define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {581; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma584; CHECK-NEXT: vmfle.vf v0, v8, fa0585; CHECK-NEXT: ret586entry:587 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(588 <vscale x 8 x half> %0,589 half %1,590 iXLen %2)591 592 ret <vscale x 8 x i1> %a593}594 595define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {596; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:597; CHECK: # %bb.0: # %entry598; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu599; CHECK-NEXT: vmv1r.v v11, v0600; CHECK-NEXT: vmv1r.v v0, v10601; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t602; CHECK-NEXT: vmv1r.v v0, v11603; CHECK-NEXT: ret604entry:605 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(606 <vscale x 8 x i1> %0,607 <vscale x 8 x half> %1,608 half %2,609 <vscale x 8 x i1> %3,610 iXLen %4)611 612 ret <vscale x 8 x i1> %a613}614 615define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {616; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma619; CHECK-NEXT: vmfle.vf v0, v8, fa0620; CHECK-NEXT: ret621entry:622 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(623 <vscale x 16 x half> %0,624 half %1,625 iXLen %2)626 627 ret <vscale x 16 x i1> %a628}629 630define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {631; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:632; CHECK: # %bb.0: # %entry633; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu634; CHECK-NEXT: vmv1r.v v13, v0635; CHECK-NEXT: vmv1r.v v0, v12636; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t637; CHECK-NEXT: vmv1r.v v0, v13638; CHECK-NEXT: ret639entry:640 %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(641 <vscale x 16 x i1> %0,642 <vscale x 16 x half> %1,643 half %2,644 <vscale x 16 x i1> %3,645 iXLen %4)646 647 ret <vscale x 16 x i1> %a648}649 650define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {651; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma654; CHECK-NEXT: vmfle.vf v0, v8, fa0655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(658 <vscale x 1 x float> %0,659 float %1,660 iXLen %2)661 662 ret <vscale x 1 x i1> %a663}664 665define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {666; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:667; CHECK: # %bb.0: # %entry668; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu669; CHECK-NEXT: vmv1r.v v10, v0670; CHECK-NEXT: vmv1r.v v0, v9671; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t672; CHECK-NEXT: vmv1r.v v0, v10673; CHECK-NEXT: ret674entry:675 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(676 <vscale x 1 x i1> %0,677 <vscale x 1 x float> %1,678 float %2,679 <vscale x 1 x i1> %3,680 iXLen %4)681 682 ret <vscale x 1 x i1> %a683}684 685define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {686; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:687; CHECK: # %bb.0: # %entry688; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma689; CHECK-NEXT: vmfle.vf v0, v8, fa0690; CHECK-NEXT: ret691entry:692 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(693 <vscale x 2 x float> %0,694 float %1,695 iXLen %2)696 697 ret <vscale x 2 x i1> %a698}699 700define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {701; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu704; CHECK-NEXT: vmv1r.v v10, v0705; CHECK-NEXT: vmv1r.v v0, v9706; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t707; CHECK-NEXT: vmv.v.v v0, v10708; CHECK-NEXT: ret709entry:710 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(711 <vscale x 2 x i1> %0,712 <vscale x 2 x float> %1,713 float %2,714 <vscale x 2 x i1> %3,715 iXLen %4)716 717 ret <vscale x 2 x i1> %a718}719 720define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {721; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:722; CHECK: # %bb.0: # %entry723; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma724; CHECK-NEXT: vmfle.vf v0, v8, fa0725; CHECK-NEXT: ret726entry:727 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(728 <vscale x 4 x float> %0,729 float %1,730 iXLen %2)731 732 ret <vscale x 4 x i1> %a733}734 735define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {736; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:737; CHECK: # %bb.0: # %entry738; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu739; CHECK-NEXT: vmv1r.v v11, v0740; CHECK-NEXT: vmv1r.v v0, v10741; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t742; CHECK-NEXT: vmv1r.v v0, v11743; CHECK-NEXT: ret744entry:745 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(746 <vscale x 4 x i1> %0,747 <vscale x 4 x float> %1,748 float %2,749 <vscale x 4 x i1> %3,750 iXLen %4)751 752 ret <vscale x 4 x i1> %a753}754 755define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {756; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:757; CHECK: # %bb.0: # %entry758; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma759; CHECK-NEXT: vmfle.vf v0, v8, fa0760; CHECK-NEXT: ret761entry:762 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(763 <vscale x 8 x float> %0,764 float %1,765 iXLen %2)766 767 ret <vscale x 8 x i1> %a768}769 770define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {771; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:772; CHECK: # %bb.0: # %entry773; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu774; CHECK-NEXT: vmv1r.v v13, v0775; CHECK-NEXT: vmv1r.v v0, v12776; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t777; CHECK-NEXT: vmv1r.v v0, v13778; CHECK-NEXT: ret779entry:780 %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(781 <vscale x 8 x i1> %0,782 <vscale x 8 x float> %1,783 float %2,784 <vscale x 8 x i1> %3,785 iXLen %4)786 787 ret <vscale x 8 x i1> %a788}789 790define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {791; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:792; CHECK: # %bb.0: # %entry793; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma794; CHECK-NEXT: vmfle.vf v0, v8, fa0795; CHECK-NEXT: ret796entry:797 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(798 <vscale x 1 x double> %0,799 double %1,800 iXLen %2)801 802 ret <vscale x 1 x i1> %a803}804 805define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {806; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:807; CHECK: # %bb.0: # %entry808; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu809; CHECK-NEXT: vmv1r.v v10, v0810; CHECK-NEXT: vmv1r.v v0, v9811; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t812; CHECK-NEXT: vmv.v.v v0, v10813; CHECK-NEXT: ret814entry:815 %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(816 <vscale x 1 x i1> %0,817 <vscale x 1 x double> %1,818 double %2,819 <vscale x 1 x i1> %3,820 iXLen %4)821 822 ret <vscale x 1 x i1> %a823}824 825define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {826; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:827; CHECK: # %bb.0: # %entry828; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma829; CHECK-NEXT: vmfle.vf v0, v8, fa0830; CHECK-NEXT: ret831entry:832 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(833 <vscale x 2 x double> %0,834 double %1,835 iXLen %2)836 837 ret <vscale x 2 x i1> %a838}839 840define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {841; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:842; CHECK: # %bb.0: # %entry843; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu844; CHECK-NEXT: vmv1r.v v11, v0845; CHECK-NEXT: vmv1r.v v0, v10846; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t847; CHECK-NEXT: vmv1r.v v0, v11848; CHECK-NEXT: ret849entry:850 %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(851 <vscale x 2 x i1> %0,852 <vscale x 2 x double> %1,853 double %2,854 <vscale x 2 x i1> %3,855 iXLen %4)856 857 ret <vscale x 2 x i1> %a858}859 860define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {861; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:862; CHECK: # %bb.0: # %entry863; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma864; CHECK-NEXT: vmfle.vf v0, v8, fa0865; CHECK-NEXT: ret866entry:867 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(868 <vscale x 4 x double> %0,869 double %1,870 iXLen %2)871 872 ret <vscale x 4 x i1> %a873}874 875define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {876; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:877; CHECK: # %bb.0: # %entry878; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu879; CHECK-NEXT: vmv1r.v v13, v0880; CHECK-NEXT: vmv1r.v v0, v12881; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t882; CHECK-NEXT: vmv1r.v v0, v13883; CHECK-NEXT: ret884entry:885 %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(886 <vscale x 4 x i1> %0,887 <vscale x 4 x double> %1,888 double %2,889 <vscale x 4 x i1> %3,890 iXLen %4)891 892 ret <vscale x 4 x i1> %a893}894