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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmnor.mm v0, v0, v812; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(15 <vscale x 1 x i1> %0,16 <vscale x 1 x i1> %1,17 iXLen %2)18 19 ret <vscale x 1 x i1> %a20}21 22define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {23; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma26; CHECK-NEXT: vmnor.mm v0, v0, v827; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(30 <vscale x 2 x i1> %0,31 <vscale x 2 x i1> %1,32 iXLen %2)33 34 ret <vscale x 2 x i1> %a35}36 37define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {38; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma41; CHECK-NEXT: vmnor.mm v0, v0, v842; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(45 <vscale x 4 x i1> %0,46 <vscale x 4 x i1> %1,47 iXLen %2)48 49 ret <vscale x 4 x i1> %a50}51 52define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {53; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma56; CHECK-NEXT: vmnor.mm v0, v0, v857; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(60 <vscale x 8 x i1> %0,61 <vscale x 8 x i1> %1,62 iXLen %2)63 64 ret <vscale x 8 x i1> %a65}66 67define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {68; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma71; CHECK-NEXT: vmnor.mm v0, v0, v872; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(75 <vscale x 16 x i1> %0,76 <vscale x 16 x i1> %1,77 iXLen %2)78 79 ret <vscale x 16 x i1> %a80}81 82define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {83; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma86; CHECK-NEXT: vmnor.mm v0, v0, v887; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(90 <vscale x 32 x i1> %0,91 <vscale x 32 x i1> %1,92 iXLen %2)93 94 ret <vscale x 32 x i1> %a95}96 97define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {98; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma101; CHECK-NEXT: vmnor.mm v0, v0, v8102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(105 <vscale x 64 x i1> %0,106 <vscale x 64 x i1> %1,107 iXLen %2)108 109 ret <vscale x 64 x i1> %a110}111