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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i1> @intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmsbc.vv v0, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.nxv1i8(15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 iXLen %2)18 19 ret <vscale x 1 x i1> %a20}21 22define <vscale x 2 x i1> @intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {23; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma26; CHECK-NEXT: vmsbc.vv v0, v8, v927; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.nxv2i8(30 <vscale x 2 x i8> %0,31 <vscale x 2 x i8> %1,32 iXLen %2)33 34 ret <vscale x 2 x i1> %a35}36 37define <vscale x 4 x i1> @intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {38; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma41; CHECK-NEXT: vmsbc.vv v0, v8, v942; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i8.nxv4i8(45 <vscale x 4 x i8> %0,46 <vscale x 4 x i8> %1,47 iXLen %2)48 49 ret <vscale x 4 x i1> %a50}51 52define <vscale x 8 x i1> @intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {53; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma56; CHECK-NEXT: vmsbc.vv v0, v8, v957; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i8.nxv8i8(60 <vscale x 8 x i8> %0,61 <vscale x 8 x i8> %1,62 iXLen %2)63 64 ret <vscale x 8 x i1> %a65}66 67define <vscale x 16 x i1> @intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {68; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma71; CHECK-NEXT: vmsbc.vv v0, v8, v1072; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i8.nxv16i8(75 <vscale x 16 x i8> %0,76 <vscale x 16 x i8> %1,77 iXLen %2)78 79 ret <vscale x 16 x i1> %a80}81 82define <vscale x 32 x i1> @intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {83; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma86; CHECK-NEXT: vmsbc.vv v0, v8, v1287; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.nxv32i8.nxv32i8(90 <vscale x 32 x i8> %0,91 <vscale x 32 x i8> %1,92 iXLen %2)93 94 ret <vscale x 32 x i1> %a95}96 97define <vscale x 64 x i1> @intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {98; CHECK-LABEL: intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma101; CHECK-NEXT: vmsbc.vv v0, v8, v16102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.nxv64i8.nxv64i8(105 <vscale x 64 x i8> %0,106 <vscale x 64 x i8> %1,107 iXLen %2)108 109 ret <vscale x 64 x i1> %a110}111 112define <vscale x 1 x i1> @intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {113; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma116; CHECK-NEXT: vmsbc.vv v0, v8, v9117; CHECK-NEXT: ret118entry:119 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i16.nxv1i16(120 <vscale x 1 x i16> %0,121 <vscale x 1 x i16> %1,122 iXLen %2)123 124 ret <vscale x 1 x i1> %a125}126 127define <vscale x 2 x i1> @intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {128; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma131; CHECK-NEXT: vmsbc.vv v0, v8, v9132; CHECK-NEXT: ret133entry:134 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i16.nxv2i16(135 <vscale x 2 x i16> %0,136 <vscale x 2 x i16> %1,137 iXLen %2)138 139 ret <vscale x 2 x i1> %a140}141 142define <vscale x 4 x i1> @intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {143; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma146; CHECK-NEXT: vmsbc.vv v0, v8, v9147; CHECK-NEXT: ret148entry:149 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i16.nxv4i16(150 <vscale x 4 x i16> %0,151 <vscale x 4 x i16> %1,152 iXLen %2)153 154 ret <vscale x 4 x i1> %a155}156 157define <vscale x 8 x i1> @intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {158; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma161; CHECK-NEXT: vmsbc.vv v0, v8, v10162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i16.nxv8i16(165 <vscale x 8 x i16> %0,166 <vscale x 8 x i16> %1,167 iXLen %2)168 169 ret <vscale x 8 x i1> %a170}171 172define <vscale x 16 x i1> @intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma176; CHECK-NEXT: vmsbc.vv v0, v8, v12177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i16.nxv16i16(180 <vscale x 16 x i16> %0,181 <vscale x 16 x i16> %1,182 iXLen %2)183 184 ret <vscale x 16 x i1> %a185}186 187define <vscale x 32 x i1> @intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {188; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma191; CHECK-NEXT: vmsbc.vv v0, v8, v16192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.nxv32i16.nxv32i16(195 <vscale x 32 x i16> %0,196 <vscale x 32 x i16> %1,197 iXLen %2)198 199 ret <vscale x 32 x i1> %a200}201 202define <vscale x 1 x i1> @intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma206; CHECK-NEXT: vmsbc.vv v0, v8, v9207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i32.nxv1i32(210 <vscale x 1 x i32> %0,211 <vscale x 1 x i32> %1,212 iXLen %2)213 214 ret <vscale x 1 x i1> %a215}216 217define <vscale x 2 x i1> @intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {218; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma221; CHECK-NEXT: vmsbc.vv v0, v8, v9222; CHECK-NEXT: ret223entry:224 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i32.nxv2i32(225 <vscale x 2 x i32> %0,226 <vscale x 2 x i32> %1,227 iXLen %2)228 229 ret <vscale x 2 x i1> %a230}231 232define <vscale x 4 x i1> @intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {233; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32:234; CHECK: # %bb.0: # %entry235; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma236; CHECK-NEXT: vmsbc.vv v0, v8, v10237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i32.nxv4i32(240 <vscale x 4 x i32> %0,241 <vscale x 4 x i32> %1,242 iXLen %2)243 244 ret <vscale x 4 x i1> %a245}246 247define <vscale x 8 x i1> @intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {248; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma251; CHECK-NEXT: vmsbc.vv v0, v8, v12252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i32.nxv8i32(255 <vscale x 8 x i32> %0,256 <vscale x 8 x i32> %1,257 iXLen %2)258 259 ret <vscale x 8 x i1> %a260}261 262define <vscale x 16 x i1> @intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {263; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma266; CHECK-NEXT: vmsbc.vv v0, v8, v16267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i32.nxv16i32(270 <vscale x 16 x i32> %0,271 <vscale x 16 x i32> %1,272 iXLen %2)273 274 ret <vscale x 16 x i1> %a275}276 277define <vscale x 1 x i1> @intrinsic_vmsbc_vv_nxv1i1_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {278; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i64_nxv1i64:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma281; CHECK-NEXT: vmsbc.vv v0, v8, v9282; CHECK-NEXT: ret283entry:284 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i64.nxv1i64(285 <vscale x 1 x i64> %0,286 <vscale x 1 x i64> %1,287 iXLen %2)288 289 ret <vscale x 1 x i1> %a290}291 292define <vscale x 2 x i1> @intrinsic_vmsbc_vv_nxv2i1_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {293; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i64_nxv2i64:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma296; CHECK-NEXT: vmsbc.vv v0, v8, v10297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.nxv2i64(300 <vscale x 2 x i64> %0,301 <vscale x 2 x i64> %1,302 iXLen %2)303 304 ret <vscale x 2 x i1> %a305}306 307define <vscale x 4 x i1> @intrinsic_vmsbc_vv_nxv4i1_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {308; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i64_nxv4i64:309; CHECK: # %bb.0: # %entry310; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma311; CHECK-NEXT: vmsbc.vv v0, v8, v12312; CHECK-NEXT: ret313entry:314 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.nxv4i64(315 <vscale x 4 x i64> %0,316 <vscale x 4 x i64> %1,317 iXLen %2)318 319 ret <vscale x 4 x i1> %a320}321 322define <vscale x 8 x i1> @intrinsic_vmsbc_vv_nxv8i1_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {323; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i64_nxv8i64:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma326; CHECK-NEXT: vmsbc.vv v0, v8, v16327; CHECK-NEXT: ret328entry:329 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.nxv8i64(330 <vscale x 8 x i64> %0,331 <vscale x 8 x i64> %1,332 iXLen %2)333 334 ret <vscale x 8 x i1> %a335}336 337define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma341; CHECK-NEXT: vmsbc.vx v0, v8, a0342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i8.i8(345 <vscale x 1 x i8> %0,346 i8 %1,347 iXLen %2)348 349 ret <vscale x 1 x i1> %a350}351 352define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {353; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8:354; CHECK: # %bb.0: # %entry355; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma356; CHECK-NEXT: vmsbc.vx v0, v8, a0357; CHECK-NEXT: ret358entry:359 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i8.i8(360 <vscale x 2 x i8> %0,361 i8 %1,362 iXLen %2)363 364 ret <vscale x 2 x i1> %a365}366 367define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {368; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8:369; CHECK: # %bb.0: # %entry370; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma371; CHECK-NEXT: vmsbc.vx v0, v8, a0372; CHECK-NEXT: ret373entry:374 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i8.i8(375 <vscale x 4 x i8> %0,376 i8 %1,377 iXLen %2)378 379 ret <vscale x 4 x i1> %a380}381 382define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {383; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8:384; CHECK: # %bb.0: # %entry385; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma386; CHECK-NEXT: vmsbc.vx v0, v8, a0387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i8.i8(390 <vscale x 8 x i8> %0,391 i8 %1,392 iXLen %2)393 394 ret <vscale x 8 x i1> %a395}396 397define <vscale x 16 x i1> @intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma401; CHECK-NEXT: vmsbc.vx v0, v8, a0402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i8.i8(405 <vscale x 16 x i8> %0,406 i8 %1,407 iXLen %2)408 409 ret <vscale x 16 x i1> %a410}411 412define <vscale x 32 x i1> @intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {413; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma416; CHECK-NEXT: vmsbc.vx v0, v8, a0417; CHECK-NEXT: ret418entry:419 %a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.nxv32i8.i8(420 <vscale x 32 x i8> %0,421 i8 %1,422 iXLen %2)423 424 ret <vscale x 32 x i1> %a425}426 427define <vscale x 64 x i1> @intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {428; CHECK-LABEL: intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma431; CHECK-NEXT: vmsbc.vx v0, v8, a0432; CHECK-NEXT: ret433entry:434 %a = call <vscale x 64 x i1> @llvm.riscv.vmsbc.nxv64i8.i8(435 <vscale x 64 x i8> %0,436 i8 %1,437 iXLen %2)438 439 ret <vscale x 64 x i1> %a440}441 442define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {443; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma446; CHECK-NEXT: vmsbc.vx v0, v8, a0447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i16.i16(450 <vscale x 1 x i16> %0,451 i16 %1,452 iXLen %2)453 454 ret <vscale x 1 x i1> %a455}456 457define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {458; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16:459; CHECK: # %bb.0: # %entry460; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma461; CHECK-NEXT: vmsbc.vx v0, v8, a0462; CHECK-NEXT: ret463entry:464 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i16.i16(465 <vscale x 2 x i16> %0,466 i16 %1,467 iXLen %2)468 469 ret <vscale x 2 x i1> %a470}471 472define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {473; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma476; CHECK-NEXT: vmsbc.vx v0, v8, a0477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i16.i16(480 <vscale x 4 x i16> %0,481 i16 %1,482 iXLen %2)483 484 ret <vscale x 4 x i1> %a485}486 487define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {488; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma491; CHECK-NEXT: vmsbc.vx v0, v8, a0492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i16.i16(495 <vscale x 8 x i16> %0,496 i16 %1,497 iXLen %2)498 499 ret <vscale x 8 x i1> %a500}501 502define <vscale x 16 x i1> @intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {503; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma506; CHECK-NEXT: vmsbc.vx v0, v8, a0507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i16.i16(510 <vscale x 16 x i16> %0,511 i16 %1,512 iXLen %2)513 514 ret <vscale x 16 x i1> %a515}516 517define <vscale x 32 x i1> @intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {518; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16:519; CHECK: # %bb.0: # %entry520; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma521; CHECK-NEXT: vmsbc.vx v0, v8, a0522; CHECK-NEXT: ret523entry:524 %a = call <vscale x 32 x i1> @llvm.riscv.vmsbc.nxv32i16.i16(525 <vscale x 32 x i16> %0,526 i16 %1,527 iXLen %2)528 529 ret <vscale x 32 x i1> %a530}531 532define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {533; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32:534; CHECK: # %bb.0: # %entry535; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma536; CHECK-NEXT: vmsbc.vx v0, v8, a0537; CHECK-NEXT: ret538entry:539 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i32.i32(540 <vscale x 1 x i32> %0,541 i32 %1,542 iXLen %2)543 544 ret <vscale x 1 x i1> %a545}546 547define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {548; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32:549; CHECK: # %bb.0: # %entry550; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma551; CHECK-NEXT: vmsbc.vx v0, v8, a0552; CHECK-NEXT: ret553entry:554 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i32.i32(555 <vscale x 2 x i32> %0,556 i32 %1,557 iXLen %2)558 559 ret <vscale x 2 x i1> %a560}561 562define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {563; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32:564; CHECK: # %bb.0: # %entry565; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma566; CHECK-NEXT: vmsbc.vx v0, v8, a0567; CHECK-NEXT: ret568entry:569 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i32.i32(570 <vscale x 4 x i32> %0,571 i32 %1,572 iXLen %2)573 574 ret <vscale x 4 x i1> %a575}576 577define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {578; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32:579; CHECK: # %bb.0: # %entry580; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma581; CHECK-NEXT: vmsbc.vx v0, v8, a0582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i32.i32(585 <vscale x 8 x i32> %0,586 i32 %1,587 iXLen %2)588 589 ret <vscale x 8 x i1> %a590}591 592define <vscale x 16 x i1> @intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {593; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32:594; CHECK: # %bb.0: # %entry595; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma596; CHECK-NEXT: vmsbc.vx v0, v8, a0597; CHECK-NEXT: ret598entry:599 %a = call <vscale x 16 x i1> @llvm.riscv.vmsbc.nxv16i32.i32(600 <vscale x 16 x i32> %0,601 i32 %1,602 iXLen %2)603 604 ret <vscale x 16 x i1> %a605}606 607define <vscale x 1 x i1> @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {608; RV32-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64:609; RV32: # %bb.0: # %entry610; RV32-NEXT: addi sp, sp, -16611; RV32-NEXT: sw a0, 8(sp)612; RV32-NEXT: sw a1, 12(sp)613; RV32-NEXT: addi a0, sp, 8614; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma615; RV32-NEXT: vlse64.v v9, (a0), zero616; RV32-NEXT: vmsbc.vv v0, v8, v9617; RV32-NEXT: addi sp, sp, 16618; RV32-NEXT: ret619;620; RV64-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64:621; RV64: # %bb.0: # %entry622; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma623; RV64-NEXT: vmsbc.vx v0, v8, a0624; RV64-NEXT: ret625entry:626 %a = call <vscale x 1 x i1> @llvm.riscv.vmsbc.nxv1i64.i64(627 <vscale x 1 x i64> %0,628 i64 %1,629 iXLen %2)630 631 ret <vscale x 1 x i1> %a632}633 634define <vscale x 2 x i1> @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {635; RV32-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64:636; RV32: # %bb.0: # %entry637; RV32-NEXT: addi sp, sp, -16638; RV32-NEXT: sw a0, 8(sp)639; RV32-NEXT: sw a1, 12(sp)640; RV32-NEXT: addi a0, sp, 8641; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma642; RV32-NEXT: vlse64.v v10, (a0), zero643; RV32-NEXT: vmsbc.vv v0, v8, v10644; RV32-NEXT: addi sp, sp, 16645; RV32-NEXT: ret646;647; RV64-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64:648; RV64: # %bb.0: # %entry649; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma650; RV64-NEXT: vmsbc.vx v0, v8, a0651; RV64-NEXT: ret652entry:653 %a = call <vscale x 2 x i1> @llvm.riscv.vmsbc.nxv2i64.i64(654 <vscale x 2 x i64> %0,655 i64 %1,656 iXLen %2)657 658 ret <vscale x 2 x i1> %a659}660 661define <vscale x 4 x i1> @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {662; RV32-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64:663; RV32: # %bb.0: # %entry664; RV32-NEXT: addi sp, sp, -16665; RV32-NEXT: sw a0, 8(sp)666; RV32-NEXT: sw a1, 12(sp)667; RV32-NEXT: addi a0, sp, 8668; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma669; RV32-NEXT: vlse64.v v12, (a0), zero670; RV32-NEXT: vmsbc.vv v0, v8, v12671; RV32-NEXT: addi sp, sp, 16672; RV32-NEXT: ret673;674; RV64-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64:675; RV64: # %bb.0: # %entry676; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma677; RV64-NEXT: vmsbc.vx v0, v8, a0678; RV64-NEXT: ret679entry:680 %a = call <vscale x 4 x i1> @llvm.riscv.vmsbc.nxv4i64.i64(681 <vscale x 4 x i64> %0,682 i64 %1,683 iXLen %2)684 685 ret <vscale x 4 x i1> %a686}687 688define <vscale x 8 x i1> @intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {689; RV32-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64:690; RV32: # %bb.0: # %entry691; RV32-NEXT: addi sp, sp, -16692; RV32-NEXT: sw a0, 8(sp)693; RV32-NEXT: sw a1, 12(sp)694; RV32-NEXT: addi a0, sp, 8695; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma696; RV32-NEXT: vlse64.v v16, (a0), zero697; RV32-NEXT: vmsbc.vv v0, v8, v16698; RV32-NEXT: addi sp, sp, 16699; RV32-NEXT: ret700;701; RV64-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64:702; RV64: # %bb.0: # %entry703; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma704; RV64-NEXT: vmsbc.vx v0, v8, a0705; RV64-NEXT: ret706entry:707 %a = call <vscale x 8 x i1> @llvm.riscv.vmsbc.nxv8i64.i64(708 <vscale x 8 x i64> %0,709 i64 %1,710 iXLen %2)711 712 ret <vscale x 8 x i1> %a713}714