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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vmset_m_pseudo_nxv1i1(iXLen %0) nounwind {8; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmset.m v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(15 iXLen %0)16 17 ret <vscale x 1 x i1> %a18}19 20define <vscale x 2 x i1> @intrinsic_vmset_m_pseudo_nxv2i1(iXLen %0) nounwind {21; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma24; CHECK-NEXT: vmset.m v025; CHECK-NEXT: ret26entry:27 %a = call <vscale x 2 x i1> @llvm.riscv.vmset.nxv2i1(28 iXLen %0)29 30 ret <vscale x 2 x i1> %a31}32 33define <vscale x 4 x i1> @intrinsic_vmset_m_pseudo_nxv4i1(iXLen %0) nounwind {34; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma37; CHECK-NEXT: vmset.m v038; CHECK-NEXT: ret39entry:40 %a = call <vscale x 4 x i1> @llvm.riscv.vmset.nxv4i1(41 iXLen %0)42 43 ret <vscale x 4 x i1> %a44}45 46define <vscale x 8 x i1> @intrinsic_vmset_m_pseudo_nxv8i1(iXLen %0) nounwind {47; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma50; CHECK-NEXT: vmset.m v051; CHECK-NEXT: ret52entry:53 %a = call <vscale x 8 x i1> @llvm.riscv.vmset.nxv8i1(54 iXLen %0)55 56 ret <vscale x 8 x i1> %a57}58 59define <vscale x 16 x i1> @intrinsic_vmset_m_pseudo_nxv16i1(iXLen %0) nounwind {60; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma63; CHECK-NEXT: vmset.m v064; CHECK-NEXT: ret65entry:66 %a = call <vscale x 16 x i1> @llvm.riscv.vmset.nxv16i1(67 iXLen %0)68 69 ret <vscale x 16 x i1> %a70}71 72define <vscale x 32 x i1> @intrinsic_vmset_m_pseudo_nxv32i1(iXLen %0) nounwind {73; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma76; CHECK-NEXT: vmset.m v077; CHECK-NEXT: ret78entry:79 %a = call <vscale x 32 x i1> @llvm.riscv.vmset.nxv32i1(80 iXLen %0)81 82 ret <vscale x 32 x i1> %a83}84 85define <vscale x 64 x i1> @intrinsic_vmset_m_pseudo_nxv64i1(iXLen %0) nounwind {86; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma89; CHECK-NEXT: vmset.m v090; CHECK-NEXT: ret91entry:92 %a = call <vscale x 64 x i1> @llvm.riscv.vmset.nxv64i1(93 iXLen %0)94 95 ret <vscale x 64 x i1> %a96}97