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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i1> @intrinsic_vmsge_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmsge_vv_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    vmsle.vv v0, v9, v812; CHECK-NEXT:    ret13entry:14  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(15    <vscale x 1 x i8> %0,16    <vscale x 1 x i8> %1,17    iXLen %2)18 19  ret <vscale x 1 x i1> %a20}21 22define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:24; CHECK:       # %bb.0: # %entry25; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu26; CHECK-NEXT:    vmv1r.v v11, v027; CHECK-NEXT:    vmsle.vv v0, v9, v828; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t29; CHECK-NEXT:    vmv1r.v v0, v1130; CHECK-NEXT:    ret31entry:32  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(33    <vscale x 1 x i8> %1,34    <vscale x 1 x i8> %2,35    iXLen %4)36  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(37    <vscale x 1 x i1> %0,38    <vscale x 1 x i8> %2,39    <vscale x 1 x i8> %3,40    <vscale x 1 x i1> %mask,41    iXLen %4)42 43  ret <vscale x 1 x i1> %a44}45 46define <vscale x 2 x i1> @intrinsic_vmsge_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmsge_vv_nxv2i8_nxv2i8:48; CHECK:       # %bb.0: # %entry49; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma50; CHECK-NEXT:    vmsle.vv v0, v9, v851; CHECK-NEXT:    ret52entry:53  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(54    <vscale x 2 x i8> %0,55    <vscale x 2 x i8> %1,56    iXLen %2)57 58  ret <vscale x 2 x i1> %a59}60 61define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, iXLen %4) nounwind {62; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:63; CHECK:       # %bb.0: # %entry64; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu65; CHECK-NEXT:    vmv1r.v v11, v066; CHECK-NEXT:    vmsle.vv v0, v9, v867; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t68; CHECK-NEXT:    vmv1r.v v0, v1169; CHECK-NEXT:    ret70entry:71  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(72    <vscale x 2 x i8> %1,73    <vscale x 2 x i8> %2,74    iXLen %4)75  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(76    <vscale x 2 x i1> %0,77    <vscale x 2 x i8> %2,78    <vscale x 2 x i8> %3,79    <vscale x 2 x i1> %mask,80    iXLen %4)81 82  ret <vscale x 2 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmsge_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vmsge_vv_nxv4i8_nxv4i8:87; CHECK:       # %bb.0: # %entry88; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma89; CHECK-NEXT:    vmsle.vv v0, v9, v890; CHECK-NEXT:    ret91entry:92  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(93    <vscale x 4 x i8> %0,94    <vscale x 4 x i8> %1,95    iXLen %2)96 97  ret <vscale x 4 x i1> %a98}99 100define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:102; CHECK:       # %bb.0: # %entry103; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu104; CHECK-NEXT:    vmv1r.v v11, v0105; CHECK-NEXT:    vmsle.vv v0, v9, v8106; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t107; CHECK-NEXT:    vmv1r.v v0, v11108; CHECK-NEXT:    ret109entry:110  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(111    <vscale x 4 x i8> %1,112    <vscale x 4 x i8> %2,113    iXLen %4)114  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(115    <vscale x 4 x i1> %0,116    <vscale x 4 x i8> %2,117    <vscale x 4 x i8> %3,118    <vscale x 4 x i1> %mask,119    iXLen %4)120 121  ret <vscale x 4 x i1> %a122}123 124define <vscale x 8 x i1> @intrinsic_vmsge_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vmsge_vv_nxv8i8_nxv8i8:126; CHECK:       # %bb.0: # %entry127; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma128; CHECK-NEXT:    vmsle.vv v0, v9, v8129; CHECK-NEXT:    ret130entry:131  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(132    <vscale x 8 x i8> %0,133    <vscale x 8 x i8> %1,134    iXLen %2)135 136  ret <vscale x 8 x i1> %a137}138 139define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu143; CHECK-NEXT:    vmv1r.v v11, v0144; CHECK-NEXT:    vmsle.vv v0, v9, v8145; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t146; CHECK-NEXT:    vmv.v.v v0, v11147; CHECK-NEXT:    ret148entry:149  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(150    <vscale x 8 x i8> %1,151    <vscale x 8 x i8> %2,152    iXLen %4)153  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(154    <vscale x 8 x i1> %0,155    <vscale x 8 x i8> %2,156    <vscale x 8 x i8> %3,157    <vscale x 8 x i1> %mask,158    iXLen %4)159 160  ret <vscale x 8 x i1> %a161}162 163define <vscale x 16 x i1> @intrinsic_vmsge_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vmsge_vv_nxv16i8_nxv16i8:165; CHECK:       # %bb.0: # %entry166; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma167; CHECK-NEXT:    vmsle.vv v0, v10, v8168; CHECK-NEXT:    ret169entry:170  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(171    <vscale x 16 x i8> %0,172    <vscale x 16 x i8> %1,173    iXLen %2)174 175  ret <vscale x 16 x i1> %a176}177 178define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, iXLen %4) nounwind {179; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:180; CHECK:       # %bb.0: # %entry181; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu182; CHECK-NEXT:    vmv1r.v v14, v0183; CHECK-NEXT:    vmsle.vv v0, v10, v8184; CHECK-NEXT:    vmsle.vv v14, v12, v10, v0.t185; CHECK-NEXT:    vmv1r.v v0, v14186; CHECK-NEXT:    ret187entry:188  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(189    <vscale x 16 x i8> %1,190    <vscale x 16 x i8> %2,191    iXLen %4)192  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(193    <vscale x 16 x i1> %0,194    <vscale x 16 x i8> %2,195    <vscale x 16 x i8> %3,196    <vscale x 16 x i1> %mask,197    iXLen %4)198 199  ret <vscale x 16 x i1> %a200}201 202define <vscale x 32 x i1> @intrinsic_vmsge_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmsge_vv_nxv32i8_nxv32i8:204; CHECK:       # %bb.0: # %entry205; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma206; CHECK-NEXT:    vmsle.vv v0, v12, v8207; CHECK-NEXT:    ret208entry:209  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(210    <vscale x 32 x i8> %0,211    <vscale x 32 x i8> %1,212    iXLen %2)213 214  ret <vscale x 32 x i1> %a215}216 217define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, iXLen %4) nounwind {218; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:219; CHECK:       # %bb.0: # %entry220; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu221; CHECK-NEXT:    vmv1r.v v20, v0222; CHECK-NEXT:    vmsle.vv v0, v12, v8223; CHECK-NEXT:    vmsle.vv v20, v16, v12, v0.t224; CHECK-NEXT:    vmv1r.v v0, v20225; CHECK-NEXT:    ret226entry:227  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(228    <vscale x 32 x i8> %1,229    <vscale x 32 x i8> %2,230    iXLen %4)231  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(232    <vscale x 32 x i1> %0,233    <vscale x 32 x i8> %2,234    <vscale x 32 x i8> %3,235    <vscale x 32 x i1> %mask,236    iXLen %4)237 238  ret <vscale x 32 x i1> %a239}240 241define <vscale x 1 x i1> @intrinsic_vmsge_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {242; CHECK-LABEL: intrinsic_vmsge_vv_nxv1i16_nxv1i16:243; CHECK:       # %bb.0: # %entry244; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma245; CHECK-NEXT:    vmsle.vv v0, v9, v8246; CHECK-NEXT:    ret247entry:248  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(249    <vscale x 1 x i16> %0,250    <vscale x 1 x i16> %1,251    iXLen %2)252 253  ret <vscale x 1 x i1> %a254}255 256define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, iXLen %4) nounwind {257; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:258; CHECK:       # %bb.0: # %entry259; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu260; CHECK-NEXT:    vmv1r.v v11, v0261; CHECK-NEXT:    vmsle.vv v0, v9, v8262; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t263; CHECK-NEXT:    vmv1r.v v0, v11264; CHECK-NEXT:    ret265entry:266  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(267    <vscale x 1 x i16> %1,268    <vscale x 1 x i16> %2,269    iXLen %4)270  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(271    <vscale x 1 x i1> %0,272    <vscale x 1 x i16> %2,273    <vscale x 1 x i16> %3,274    <vscale x 1 x i1> %mask,275    iXLen %4)276 277  ret <vscale x 1 x i1> %a278}279 280define <vscale x 2 x i1> @intrinsic_vmsge_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {281; CHECK-LABEL: intrinsic_vmsge_vv_nxv2i16_nxv2i16:282; CHECK:       # %bb.0: # %entry283; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma284; CHECK-NEXT:    vmsle.vv v0, v9, v8285; CHECK-NEXT:    ret286entry:287  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(288    <vscale x 2 x i16> %0,289    <vscale x 2 x i16> %1,290    iXLen %2)291 292  ret <vscale x 2 x i1> %a293}294 295define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:297; CHECK:       # %bb.0: # %entry298; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu299; CHECK-NEXT:    vmv1r.v v11, v0300; CHECK-NEXT:    vmsle.vv v0, v9, v8301; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t302; CHECK-NEXT:    vmv1r.v v0, v11303; CHECK-NEXT:    ret304entry:305  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(306    <vscale x 2 x i16> %1,307    <vscale x 2 x i16> %2,308    iXLen %4)309  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(310    <vscale x 2 x i1> %0,311    <vscale x 2 x i16> %2,312    <vscale x 2 x i16> %3,313    <vscale x 2 x i1> %mask,314    iXLen %4)315 316  ret <vscale x 2 x i1> %a317}318 319define <vscale x 4 x i1> @intrinsic_vmsge_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {320; CHECK-LABEL: intrinsic_vmsge_vv_nxv4i16_nxv4i16:321; CHECK:       # %bb.0: # %entry322; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma323; CHECK-NEXT:    vmsle.vv v0, v9, v8324; CHECK-NEXT:    ret325entry:326  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(327    <vscale x 4 x i16> %0,328    <vscale x 4 x i16> %1,329    iXLen %2)330 331  ret <vscale x 4 x i1> %a332}333 334define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, iXLen %4) nounwind {335; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:336; CHECK:       # %bb.0: # %entry337; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu338; CHECK-NEXT:    vmv1r.v v11, v0339; CHECK-NEXT:    vmsle.vv v0, v9, v8340; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t341; CHECK-NEXT:    vmv.v.v v0, v11342; CHECK-NEXT:    ret343entry:344  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(345    <vscale x 4 x i16> %1,346    <vscale x 4 x i16> %2,347    iXLen %4)348  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(349    <vscale x 4 x i1> %0,350    <vscale x 4 x i16> %2,351    <vscale x 4 x i16> %3,352    <vscale x 4 x i1> %mask,353    iXLen %4)354 355  ret <vscale x 4 x i1> %a356}357 358define <vscale x 8 x i1> @intrinsic_vmsge_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {359; CHECK-LABEL: intrinsic_vmsge_vv_nxv8i16_nxv8i16:360; CHECK:       # %bb.0: # %entry361; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma362; CHECK-NEXT:    vmsle.vv v0, v10, v8363; CHECK-NEXT:    ret364entry:365  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(366    <vscale x 8 x i16> %0,367    <vscale x 8 x i16> %1,368    iXLen %2)369 370  ret <vscale x 8 x i1> %a371}372 373define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, iXLen %4) nounwind {374; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:375; CHECK:       # %bb.0: # %entry376; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu377; CHECK-NEXT:    vmv1r.v v14, v0378; CHECK-NEXT:    vmsle.vv v0, v10, v8379; CHECK-NEXT:    vmsle.vv v14, v12, v10, v0.t380; CHECK-NEXT:    vmv1r.v v0, v14381; CHECK-NEXT:    ret382entry:383  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(384    <vscale x 8 x i16> %1,385    <vscale x 8 x i16> %2,386    iXLen %4)387  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(388    <vscale x 8 x i1> %0,389    <vscale x 8 x i16> %2,390    <vscale x 8 x i16> %3,391    <vscale x 8 x i1> %mask,392    iXLen %4)393 394  ret <vscale x 8 x i1> %a395}396 397define <vscale x 16 x i1> @intrinsic_vmsge_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmsge_vv_nxv16i16_nxv16i16:399; CHECK:       # %bb.0: # %entry400; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma401; CHECK-NEXT:    vmsle.vv v0, v12, v8402; CHECK-NEXT:    ret403entry:404  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(405    <vscale x 16 x i16> %0,406    <vscale x 16 x i16> %1,407    iXLen %2)408 409  ret <vscale x 16 x i1> %a410}411 412define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, iXLen %4) nounwind {413; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:414; CHECK:       # %bb.0: # %entry415; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu416; CHECK-NEXT:    vmv1r.v v20, v0417; CHECK-NEXT:    vmsle.vv v0, v12, v8418; CHECK-NEXT:    vmsle.vv v20, v16, v12, v0.t419; CHECK-NEXT:    vmv1r.v v0, v20420; CHECK-NEXT:    ret421entry:422  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(423    <vscale x 16 x i16> %1,424    <vscale x 16 x i16> %2,425    iXLen %4)426  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(427    <vscale x 16 x i1> %0,428    <vscale x 16 x i16> %2,429    <vscale x 16 x i16> %3,430    <vscale x 16 x i1> %mask,431    iXLen %4)432 433  ret <vscale x 16 x i1> %a434}435 436define <vscale x 1 x i1> @intrinsic_vmsge_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vmsge_vv_nxv1i32_nxv1i32:438; CHECK:       # %bb.0: # %entry439; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma440; CHECK-NEXT:    vmsle.vv v0, v9, v8441; CHECK-NEXT:    ret442entry:443  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(444    <vscale x 1 x i32> %0,445    <vscale x 1 x i32> %1,446    iXLen %2)447 448  ret <vscale x 1 x i1> %a449}450 451define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, iXLen %4) nounwind {452; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:453; CHECK:       # %bb.0: # %entry454; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu455; CHECK-NEXT:    vmv1r.v v11, v0456; CHECK-NEXT:    vmsle.vv v0, v9, v8457; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t458; CHECK-NEXT:    vmv1r.v v0, v11459; CHECK-NEXT:    ret460entry:461  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(462    <vscale x 1 x i32> %1,463    <vscale x 1 x i32> %2,464    iXLen %4)465  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(466    <vscale x 1 x i1> %0,467    <vscale x 1 x i32> %2,468    <vscale x 1 x i32> %3,469    <vscale x 1 x i1> %mask,470    iXLen %4)471 472  ret <vscale x 1 x i1> %a473}474 475define <vscale x 2 x i1> @intrinsic_vmsge_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vmsge_vv_nxv2i32_nxv2i32:477; CHECK:       # %bb.0: # %entry478; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma479; CHECK-NEXT:    vmsle.vv v0, v9, v8480; CHECK-NEXT:    ret481entry:482  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(483    <vscale x 2 x i32> %0,484    <vscale x 2 x i32> %1,485    iXLen %2)486 487  ret <vscale x 2 x i1> %a488}489 490define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, iXLen %4) nounwind {491; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:492; CHECK:       # %bb.0: # %entry493; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu494; CHECK-NEXT:    vmv1r.v v11, v0495; CHECK-NEXT:    vmsle.vv v0, v9, v8496; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t497; CHECK-NEXT:    vmv.v.v v0, v11498; CHECK-NEXT:    ret499entry:500  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(501    <vscale x 2 x i32> %1,502    <vscale x 2 x i32> %2,503    iXLen %4)504  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(505    <vscale x 2 x i1> %0,506    <vscale x 2 x i32> %2,507    <vscale x 2 x i32> %3,508    <vscale x 2 x i1> %mask,509    iXLen %4)510 511  ret <vscale x 2 x i1> %a512}513 514define <vscale x 4 x i1> @intrinsic_vmsge_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {515; CHECK-LABEL: intrinsic_vmsge_vv_nxv4i32_nxv4i32:516; CHECK:       # %bb.0: # %entry517; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma518; CHECK-NEXT:    vmsle.vv v0, v10, v8519; CHECK-NEXT:    ret520entry:521  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(522    <vscale x 4 x i32> %0,523    <vscale x 4 x i32> %1,524    iXLen %2)525 526  ret <vscale x 4 x i1> %a527}528 529define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:531; CHECK:       # %bb.0: # %entry532; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu533; CHECK-NEXT:    vmv1r.v v14, v0534; CHECK-NEXT:    vmsle.vv v0, v10, v8535; CHECK-NEXT:    vmsle.vv v14, v12, v10, v0.t536; CHECK-NEXT:    vmv1r.v v0, v14537; CHECK-NEXT:    ret538entry:539  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(540    <vscale x 4 x i32> %1,541    <vscale x 4 x i32> %2,542    iXLen %4)543  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(544    <vscale x 4 x i1> %0,545    <vscale x 4 x i32> %2,546    <vscale x 4 x i32> %3,547    <vscale x 4 x i1> %mask,548    iXLen %4)549 550  ret <vscale x 4 x i1> %a551}552 553define <vscale x 8 x i1> @intrinsic_vmsge_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {554; CHECK-LABEL: intrinsic_vmsge_vv_nxv8i32_nxv8i32:555; CHECK:       # %bb.0: # %entry556; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma557; CHECK-NEXT:    vmsle.vv v0, v12, v8558; CHECK-NEXT:    ret559entry:560  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(561    <vscale x 8 x i32> %0,562    <vscale x 8 x i32> %1,563    iXLen %2)564 565  ret <vscale x 8 x i1> %a566}567 568define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:570; CHECK:       # %bb.0: # %entry571; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu572; CHECK-NEXT:    vmv1r.v v20, v0573; CHECK-NEXT:    vmsle.vv v0, v12, v8574; CHECK-NEXT:    vmsle.vv v20, v16, v12, v0.t575; CHECK-NEXT:    vmv1r.v v0, v20576; CHECK-NEXT:    ret577entry:578  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(579    <vscale x 8 x i32> %1,580    <vscale x 8 x i32> %2,581    iXLen %4)582  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(583    <vscale x 8 x i1> %0,584    <vscale x 8 x i32> %2,585    <vscale x 8 x i32> %3,586    <vscale x 8 x i1> %mask,587    iXLen %4)588 589  ret <vscale x 8 x i1> %a590}591 592define <vscale x 1 x i1> @intrinsic_vmsge_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {593; CHECK-LABEL: intrinsic_vmsge_vv_nxv1i64_nxv1i64:594; CHECK:       # %bb.0: # %entry595; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma596; CHECK-NEXT:    vmsle.vv v0, v9, v8597; CHECK-NEXT:    ret598entry:599  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(600    <vscale x 1 x i64> %0,601    <vscale x 1 x i64> %1,602    iXLen %2)603 604  ret <vscale x 1 x i1> %a605}606 607define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, iXLen %4) nounwind {608; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:609; CHECK:       # %bb.0: # %entry610; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu611; CHECK-NEXT:    vmv1r.v v11, v0612; CHECK-NEXT:    vmsle.vv v0, v9, v8613; CHECK-NEXT:    vmsle.vv v11, v10, v9, v0.t614; CHECK-NEXT:    vmv.v.v v0, v11615; CHECK-NEXT:    ret616entry:617  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(618    <vscale x 1 x i64> %1,619    <vscale x 1 x i64> %2,620    iXLen %4)621  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(622    <vscale x 1 x i1> %0,623    <vscale x 1 x i64> %2,624    <vscale x 1 x i64> %3,625    <vscale x 1 x i1> %mask,626    iXLen %4)627 628  ret <vscale x 1 x i1> %a629}630 631define <vscale x 2 x i1> @intrinsic_vmsge_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {632; CHECK-LABEL: intrinsic_vmsge_vv_nxv2i64_nxv2i64:633; CHECK:       # %bb.0: # %entry634; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma635; CHECK-NEXT:    vmsle.vv v0, v10, v8636; CHECK-NEXT:    ret637entry:638  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(639    <vscale x 2 x i64> %0,640    <vscale x 2 x i64> %1,641    iXLen %2)642 643  ret <vscale x 2 x i1> %a644}645 646define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, iXLen %4) nounwind {647; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:648; CHECK:       # %bb.0: # %entry649; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu650; CHECK-NEXT:    vmv1r.v v14, v0651; CHECK-NEXT:    vmsle.vv v0, v10, v8652; CHECK-NEXT:    vmsle.vv v14, v12, v10, v0.t653; CHECK-NEXT:    vmv1r.v v0, v14654; CHECK-NEXT:    ret655entry:656  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(657    <vscale x 2 x i64> %1,658    <vscale x 2 x i64> %2,659    iXLen %4)660  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(661    <vscale x 2 x i1> %0,662    <vscale x 2 x i64> %2,663    <vscale x 2 x i64> %3,664    <vscale x 2 x i1> %mask,665    iXLen %4)666 667  ret <vscale x 2 x i1> %a668}669 670define <vscale x 4 x i1> @intrinsic_vmsge_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vmsge_vv_nxv4i64_nxv4i64:672; CHECK:       # %bb.0: # %entry673; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT:    vmsle.vv v0, v12, v8675; CHECK-NEXT:    ret676entry:677  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(678    <vscale x 4 x i64> %0,679    <vscale x 4 x i64> %1,680    iXLen %2)681 682  ret <vscale x 4 x i1> %a683}684 685define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, iXLen %4) nounwind {686; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:687; CHECK:       # %bb.0: # %entry688; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu689; CHECK-NEXT:    vmv1r.v v20, v0690; CHECK-NEXT:    vmsle.vv v0, v12, v8691; CHECK-NEXT:    vmsle.vv v20, v16, v12, v0.t692; CHECK-NEXT:    vmv1r.v v0, v20693; CHECK-NEXT:    ret694entry:695  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(696    <vscale x 4 x i64> %1,697    <vscale x 4 x i64> %2,698    iXLen %4)699  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(700    <vscale x 4 x i1> %0,701    <vscale x 4 x i64> %2,702    <vscale x 4 x i64> %3,703    <vscale x 4 x i1> %mask,704    iXLen %4)705 706  ret <vscale x 4 x i1> %a707}708 709define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {710; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i8_i8:711; CHECK:       # %bb.0: # %entry712; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma713; CHECK-NEXT:    vmslt.vx v8, v8, a0714; CHECK-NEXT:    vmnot.m v0, v8715; CHECK-NEXT:    ret716entry:717  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(718    <vscale x 1 x i8> %0,719    i8 %1,720    iXLen %2)721 722  ret <vscale x 1 x i1> %a723}724 725define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {726; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:727; CHECK:       # %bb.0: # %entry728; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu729; CHECK-NEXT:    vmv1r.v v10, v0730; CHECK-NEXT:    vmv1r.v v0, v9731; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t732; CHECK-NEXT:    vmxor.mm v0, v10, v9733; CHECK-NEXT:    ret734entry:735  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(736    <vscale x 1 x i1> %0,737    <vscale x 1 x i8> %1,738    i8 %2,739    <vscale x 1 x i1> %3,740    iXLen %4)741 742  ret <vscale x 1 x i1> %a743}744 745define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {746; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i8_i8:747; CHECK:       # %bb.0: # %entry748; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma749; CHECK-NEXT:    vmslt.vx v8, v8, a0750; CHECK-NEXT:    vmnot.m v0, v8751; CHECK-NEXT:    ret752entry:753  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(754    <vscale x 2 x i8> %0,755    i8 %1,756    iXLen %2)757 758  ret <vscale x 2 x i1> %a759}760 761define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {762; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:763; CHECK:       # %bb.0: # %entry764; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu765; CHECK-NEXT:    vmv1r.v v10, v0766; CHECK-NEXT:    vmv1r.v v0, v9767; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t768; CHECK-NEXT:    vmxor.mm v0, v10, v9769; CHECK-NEXT:    ret770entry:771  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(772    <vscale x 2 x i1> %0,773    <vscale x 2 x i8> %1,774    i8 %2,775    <vscale x 2 x i1> %3,776    iXLen %4)777 778  ret <vscale x 2 x i1> %a779}780 781define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {782; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i8_i8:783; CHECK:       # %bb.0: # %entry784; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma785; CHECK-NEXT:    vmslt.vx v8, v8, a0786; CHECK-NEXT:    vmnot.m v0, v8787; CHECK-NEXT:    ret788entry:789  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(790    <vscale x 4 x i8> %0,791    i8 %1,792    iXLen %2)793 794  ret <vscale x 4 x i1> %a795}796 797define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {798; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:799; CHECK:       # %bb.0: # %entry800; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu801; CHECK-NEXT:    vmv1r.v v10, v0802; CHECK-NEXT:    vmv1r.v v0, v9803; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t804; CHECK-NEXT:    vmxor.mm v0, v10, v9805; CHECK-NEXT:    ret806entry:807  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(808    <vscale x 4 x i1> %0,809    <vscale x 4 x i8> %1,810    i8 %2,811    <vscale x 4 x i1> %3,812    iXLen %4)813 814  ret <vscale x 4 x i1> %a815}816 817define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8_1(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {818; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8_1:819; CHECK:       # %bb.0: # %entry820; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu821; CHECK-NEXT:    vmv1r.v v10, v0822; CHECK-NEXT:    li a0, 99823; CHECK-NEXT:    vmv1r.v v0, v9824; CHECK-NEXT:    vmsgt.vx v10, v8, a0, v0.t825; CHECK-NEXT:    vmv1r.v v0, v10826; CHECK-NEXT:    ret827entry:828  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(829    <vscale x 4 x i1> %0,830    <vscale x 4 x i8> %1,831    i8 100,832    <vscale x 4 x i1> %2,833    iXLen %3)834 835  ret <vscale x 4 x i1> %a836}837 838define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8_2(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {839; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8_2:840; CHECK:       # %bb.0: # %entry841; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma842; CHECK-NEXT:    vmor.mm v0, v9, v0843; CHECK-NEXT:    ret844entry:845  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(846    <vscale x 4 x i1> %0,847    <vscale x 4 x i8> %1,848    i8 -128,849    <vscale x 4 x i1> %2,850    iXLen %3)851 852  ret <vscale x 4 x i1> %a853}854 855define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {856; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i8_i8:857; CHECK:       # %bb.0: # %entry858; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma859; CHECK-NEXT:    vmslt.vx v8, v8, a0860; CHECK-NEXT:    vmnot.m v0, v8861; CHECK-NEXT:    ret862entry:863  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(864    <vscale x 8 x i8> %0,865    i8 %1,866    iXLen %2)867 868  ret <vscale x 8 x i1> %a869}870 871define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {872; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:873; CHECK:       # %bb.0: # %entry874; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu875; CHECK-NEXT:    vmv1r.v v10, v0876; CHECK-NEXT:    vmv1r.v v0, v9877; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t878; CHECK-NEXT:    vmxor.mm v0, v10, v9879; CHECK-NEXT:    ret880entry:881  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(882    <vscale x 8 x i1> %0,883    <vscale x 8 x i8> %1,884    i8 %2,885    <vscale x 8 x i1> %3,886    iXLen %4)887 888  ret <vscale x 8 x i1> %a889}890 891define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {892; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i8_i8:893; CHECK:       # %bb.0: # %entry894; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma895; CHECK-NEXT:    vmslt.vx v10, v8, a0896; CHECK-NEXT:    vmnot.m v0, v10897; CHECK-NEXT:    ret898entry:899  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(900    <vscale x 16 x i8> %0,901    i8 %1,902    iXLen %2)903 904  ret <vscale x 16 x i1> %a905}906 907define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {908; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:909; CHECK:       # %bb.0: # %entry910; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu911; CHECK-NEXT:    vmv1r.v v11, v0912; CHECK-NEXT:    vmv1r.v v0, v10913; CHECK-NEXT:    vmslt.vx v11, v8, a0, v0.t914; CHECK-NEXT:    vmxor.mm v0, v11, v10915; CHECK-NEXT:    ret916entry:917  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(918    <vscale x 16 x i1> %0,919    <vscale x 16 x i8> %1,920    i8 %2,921    <vscale x 16 x i1> %3,922    iXLen %4)923 924  ret <vscale x 16 x i1> %a925}926 927define <vscale x 32 x i1> @intrinsic_vmsge_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {928; CHECK-LABEL: intrinsic_vmsge_vx_nxv32i8_i8:929; CHECK:       # %bb.0: # %entry930; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma931; CHECK-NEXT:    vmslt.vx v12, v8, a0932; CHECK-NEXT:    vmnot.m v0, v12933; CHECK-NEXT:    ret934entry:935  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(936    <vscale x 32 x i8> %0,937    i8 %1,938    iXLen %2)939 940  ret <vscale x 32 x i1> %a941}942 943define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {944; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:945; CHECK:       # %bb.0: # %entry946; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu947; CHECK-NEXT:    vmv1r.v v13, v0948; CHECK-NEXT:    vmv1r.v v0, v12949; CHECK-NEXT:    vmslt.vx v13, v8, a0, v0.t950; CHECK-NEXT:    vmxor.mm v0, v13, v12951; CHECK-NEXT:    ret952entry:953  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(954    <vscale x 32 x i1> %0,955    <vscale x 32 x i8> %1,956    i8 %2,957    <vscale x 32 x i1> %3,958    iXLen %4)959 960  ret <vscale x 32 x i1> %a961}962 963define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {964; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i16_i16:965; CHECK:       # %bb.0: # %entry966; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma967; CHECK-NEXT:    vmslt.vx v8, v8, a0968; CHECK-NEXT:    vmnot.m v0, v8969; CHECK-NEXT:    ret970entry:971  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(972    <vscale x 1 x i16> %0,973    i16 %1,974    iXLen %2)975 976  ret <vscale x 1 x i1> %a977}978 979define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {980; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:981; CHECK:       # %bb.0: # %entry982; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu983; CHECK-NEXT:    vmv1r.v v10, v0984; CHECK-NEXT:    vmv1r.v v0, v9985; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t986; CHECK-NEXT:    vmxor.mm v0, v10, v9987; CHECK-NEXT:    ret988entry:989  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(990    <vscale x 1 x i1> %0,991    <vscale x 1 x i16> %1,992    i16 %2,993    <vscale x 1 x i1> %3,994    iXLen %4)995 996  ret <vscale x 1 x i1> %a997}998 999define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1000; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i16_i16:1001; CHECK:       # %bb.0: # %entry1002; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1003; CHECK-NEXT:    vmslt.vx v8, v8, a01004; CHECK-NEXT:    vmnot.m v0, v81005; CHECK-NEXT:    ret1006entry:1007  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(1008    <vscale x 2 x i16> %0,1009    i16 %1,1010    iXLen %2)1011 1012  ret <vscale x 2 x i1> %a1013}1014 1015define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1016; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:1017; CHECK:       # %bb.0: # %entry1018; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1019; CHECK-NEXT:    vmv1r.v v10, v01020; CHECK-NEXT:    vmv1r.v v0, v91021; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t1022; CHECK-NEXT:    vmxor.mm v0, v10, v91023; CHECK-NEXT:    ret1024entry:1025  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(1026    <vscale x 2 x i1> %0,1027    <vscale x 2 x i16> %1,1028    i16 %2,1029    <vscale x 2 x i1> %3,1030    iXLen %4)1031 1032  ret <vscale x 2 x i1> %a1033}1034 1035define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1036; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i16_i16:1037; CHECK:       # %bb.0: # %entry1038; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1039; CHECK-NEXT:    vmslt.vx v8, v8, a01040; CHECK-NEXT:    vmnot.m v0, v81041; CHECK-NEXT:    ret1042entry:1043  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(1044    <vscale x 4 x i16> %0,1045    i16 %1,1046    iXLen %2)1047 1048  ret <vscale x 4 x i1> %a1049}1050 1051define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1052; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:1053; CHECK:       # %bb.0: # %entry1054; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1055; CHECK-NEXT:    vmv1r.v v10, v01056; CHECK-NEXT:    vmv1r.v v0, v91057; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t1058; CHECK-NEXT:    vmxor.mm v0, v10, v91059; CHECK-NEXT:    ret1060entry:1061  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(1062    <vscale x 4 x i1> %0,1063    <vscale x 4 x i16> %1,1064    i16 %2,1065    <vscale x 4 x i1> %3,1066    iXLen %4)1067 1068  ret <vscale x 4 x i1> %a1069}1070 1071define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1072; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i16_i16:1073; CHECK:       # %bb.0: # %entry1074; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1075; CHECK-NEXT:    vmslt.vx v10, v8, a01076; CHECK-NEXT:    vmnot.m v0, v101077; CHECK-NEXT:    ret1078entry:1079  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(1080    <vscale x 8 x i16> %0,1081    i16 %1,1082    iXLen %2)1083 1084  ret <vscale x 8 x i1> %a1085}1086 1087define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1088; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:1089; CHECK:       # %bb.0: # %entry1090; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1091; CHECK-NEXT:    vmv1r.v v11, v01092; CHECK-NEXT:    vmv1r.v v0, v101093; CHECK-NEXT:    vmslt.vx v11, v8, a0, v0.t1094; CHECK-NEXT:    vmxor.mm v0, v11, v101095; CHECK-NEXT:    ret1096entry:1097  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(1098    <vscale x 8 x i1> %0,1099    <vscale x 8 x i16> %1,1100    i16 %2,1101    <vscale x 8 x i1> %3,1102    iXLen %4)1103 1104  ret <vscale x 8 x i1> %a1105}1106 1107define <vscale x 16 x i1> @intrinsic_vmsge_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1108; CHECK-LABEL: intrinsic_vmsge_vx_nxv16i16_i16:1109; CHECK:       # %bb.0: # %entry1110; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1111; CHECK-NEXT:    vmslt.vx v12, v8, a01112; CHECK-NEXT:    vmnot.m v0, v121113; CHECK-NEXT:    ret1114entry:1115  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(1116    <vscale x 16 x i16> %0,1117    i16 %1,1118    iXLen %2)1119 1120  ret <vscale x 16 x i1> %a1121}1122 1123define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1124; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:1125; CHECK:       # %bb.0: # %entry1126; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1127; CHECK-NEXT:    vmv1r.v v13, v01128; CHECK-NEXT:    vmv1r.v v0, v121129; CHECK-NEXT:    vmslt.vx v13, v8, a0, v0.t1130; CHECK-NEXT:    vmxor.mm v0, v13, v121131; CHECK-NEXT:    ret1132entry:1133  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(1134    <vscale x 16 x i1> %0,1135    <vscale x 16 x i16> %1,1136    i16 %2,1137    <vscale x 16 x i1> %3,1138    iXLen %4)1139 1140  ret <vscale x 16 x i1> %a1141}1142 1143define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1144; CHECK-LABEL: intrinsic_vmsge_vx_nxv1i32_i32:1145; CHECK:       # %bb.0: # %entry1146; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1147; CHECK-NEXT:    vmslt.vx v8, v8, a01148; CHECK-NEXT:    vmnot.m v0, v81149; CHECK-NEXT:    ret1150entry:1151  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(1152    <vscale x 1 x i32> %0,1153    i32 %1,1154    iXLen %2)1155 1156  ret <vscale x 1 x i1> %a1157}1158 1159define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1160; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:1161; CHECK:       # %bb.0: # %entry1162; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1163; CHECK-NEXT:    vmv1r.v v10, v01164; CHECK-NEXT:    vmv1r.v v0, v91165; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t1166; CHECK-NEXT:    vmxor.mm v0, v10, v91167; CHECK-NEXT:    ret1168entry:1169  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(1170    <vscale x 1 x i1> %0,1171    <vscale x 1 x i32> %1,1172    i32 %2,1173    <vscale x 1 x i1> %3,1174    iXLen %4)1175 1176  ret <vscale x 1 x i1> %a1177}1178 1179define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1180; CHECK-LABEL: intrinsic_vmsge_vx_nxv2i32_i32:1181; CHECK:       # %bb.0: # %entry1182; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1183; CHECK-NEXT:    vmslt.vx v8, v8, a01184; CHECK-NEXT:    vmnot.m v0, v81185; CHECK-NEXT:    ret1186entry:1187  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(1188    <vscale x 2 x i32> %0,1189    i32 %1,1190    iXLen %2)1191 1192  ret <vscale x 2 x i1> %a1193}1194 1195define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1196; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:1197; CHECK:       # %bb.0: # %entry1198; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1199; CHECK-NEXT:    vmv1r.v v10, v01200; CHECK-NEXT:    vmv1r.v v0, v91201; CHECK-NEXT:    vmslt.vx v10, v8, a0, v0.t1202; CHECK-NEXT:    vmxor.mm v0, v10, v91203; CHECK-NEXT:    ret1204entry:1205  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(1206    <vscale x 2 x i1> %0,1207    <vscale x 2 x i32> %1,1208    i32 %2,1209    <vscale x 2 x i1> %3,1210    iXLen %4)1211 1212  ret <vscale x 2 x i1> %a1213}1214 1215define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1216; CHECK-LABEL: intrinsic_vmsge_vx_nxv4i32_i32:1217; CHECK:       # %bb.0: # %entry1218; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1219; CHECK-NEXT:    vmslt.vx v10, v8, a01220; CHECK-NEXT:    vmnot.m v0, v101221; CHECK-NEXT:    ret1222entry:1223  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(1224    <vscale x 4 x i32> %0,1225    i32 %1,1226    iXLen %2)1227 1228  ret <vscale x 4 x i1> %a1229}1230 1231define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1232; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:1233; CHECK:       # %bb.0: # %entry1234; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1235; CHECK-NEXT:    vmv1r.v v11, v01236; CHECK-NEXT:    vmv1r.v v0, v101237; CHECK-NEXT:    vmslt.vx v11, v8, a0, v0.t1238; CHECK-NEXT:    vmxor.mm v0, v11, v101239; CHECK-NEXT:    ret1240entry:1241  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(1242    <vscale x 4 x i1> %0,1243    <vscale x 4 x i32> %1,1244    i32 %2,1245    <vscale x 4 x i1> %3,1246    iXLen %4)1247 1248  ret <vscale x 4 x i1> %a1249}1250 1251define <vscale x 8 x i1> @intrinsic_vmsge_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1252; CHECK-LABEL: intrinsic_vmsge_vx_nxv8i32_i32:1253; CHECK:       # %bb.0: # %entry1254; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1255; CHECK-NEXT:    vmslt.vx v12, v8, a01256; CHECK-NEXT:    vmnot.m v0, v121257; CHECK-NEXT:    ret1258entry:1259  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(1260    <vscale x 8 x i32> %0,1261    i32 %1,1262    iXLen %2)1263 1264  ret <vscale x 8 x i1> %a1265}1266 1267define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1268; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:1269; CHECK:       # %bb.0: # %entry1270; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1271; CHECK-NEXT:    vmv1r.v v13, v01272; CHECK-NEXT:    vmv1r.v v0, v121273; CHECK-NEXT:    vmslt.vx v13, v8, a0, v0.t1274; CHECK-NEXT:    vmxor.mm v0, v13, v121275; CHECK-NEXT:    ret1276entry:1277  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(1278    <vscale x 8 x i1> %0,1279    <vscale x 8 x i32> %1,1280    i32 %2,1281    <vscale x 8 x i1> %3,1282    iXLen %4)1283 1284  ret <vscale x 8 x i1> %a1285}1286 1287define <vscale x 1 x i1> @intrinsic_vmsge_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1288; RV32-LABEL: intrinsic_vmsge_vx_nxv1i64_i64:1289; RV32:       # %bb.0: # %entry1290; RV32-NEXT:    addi sp, sp, -161291; RV32-NEXT:    sw a0, 8(sp)1292; RV32-NEXT:    sw a1, 12(sp)1293; RV32-NEXT:    addi a0, sp, 81294; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1295; RV32-NEXT:    vlse64.v v9, (a0), zero1296; RV32-NEXT:    vmsle.vv v0, v9, v81297; RV32-NEXT:    addi sp, sp, 161298; RV32-NEXT:    ret1299;1300; RV64-LABEL: intrinsic_vmsge_vx_nxv1i64_i64:1301; RV64:       # %bb.0: # %entry1302; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1303; RV64-NEXT:    vmslt.vx v8, v8, a01304; RV64-NEXT:    vmnot.m v0, v81305; RV64-NEXT:    ret1306entry:1307  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(1308    <vscale x 1 x i64> %0,1309    i64 %1,1310    iXLen %2)1311 1312  ret <vscale x 1 x i1> %a1313}1314 1315define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1316; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:1317; RV32:       # %bb.0: # %entry1318; RV32-NEXT:    addi sp, sp, -161319; RV32-NEXT:    sw a0, 8(sp)1320; RV32-NEXT:    sw a1, 12(sp)1321; RV32-NEXT:    addi a0, sp, 81322; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu1323; RV32-NEXT:    vlse64.v v11, (a0), zero1324; RV32-NEXT:    vmv1r.v v10, v01325; RV32-NEXT:    vmv1r.v v0, v91326; RV32-NEXT:    vmsle.vv v10, v11, v8, v0.t1327; RV32-NEXT:    vmv.v.v v0, v101328; RV32-NEXT:    addi sp, sp, 161329; RV32-NEXT:    ret1330;1331; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:1332; RV64:       # %bb.0: # %entry1333; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1334; RV64-NEXT:    vmv1r.v v10, v01335; RV64-NEXT:    vmv1r.v v0, v91336; RV64-NEXT:    vmslt.vx v10, v8, a0, v0.t1337; RV64-NEXT:    vmxor.mm v0, v10, v91338; RV64-NEXT:    ret1339entry:1340  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(1341    <vscale x 1 x i1> %0,1342    <vscale x 1 x i64> %1,1343    i64 %2,1344    <vscale x 1 x i1> %3,1345    iXLen %4)1346 1347  ret <vscale x 1 x i1> %a1348}1349 1350define <vscale x 2 x i1> @intrinsic_vmsge_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1351; RV32-LABEL: intrinsic_vmsge_vx_nxv2i64_i64:1352; RV32:       # %bb.0: # %entry1353; RV32-NEXT:    addi sp, sp, -161354; RV32-NEXT:    sw a0, 8(sp)1355; RV32-NEXT:    sw a1, 12(sp)1356; RV32-NEXT:    addi a0, sp, 81357; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1358; RV32-NEXT:    vlse64.v v10, (a0), zero1359; RV32-NEXT:    vmsle.vv v0, v10, v81360; RV32-NEXT:    addi sp, sp, 161361; RV32-NEXT:    ret1362;1363; RV64-LABEL: intrinsic_vmsge_vx_nxv2i64_i64:1364; RV64:       # %bb.0: # %entry1365; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1366; RV64-NEXT:    vmslt.vx v10, v8, a01367; RV64-NEXT:    vmnot.m v0, v101368; RV64-NEXT:    ret1369entry:1370  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(1371    <vscale x 2 x i64> %0,1372    i64 %1,1373    iXLen %2)1374 1375  ret <vscale x 2 x i1> %a1376}1377 1378define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1379; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:1380; RV32:       # %bb.0: # %entry1381; RV32-NEXT:    addi sp, sp, -161382; RV32-NEXT:    sw a0, 8(sp)1383; RV32-NEXT:    sw a1, 12(sp)1384; RV32-NEXT:    addi a0, sp, 81385; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu1386; RV32-NEXT:    vlse64.v v12, (a0), zero1387; RV32-NEXT:    vmv1r.v v11, v01388; RV32-NEXT:    vmv1r.v v0, v101389; RV32-NEXT:    vmsle.vv v11, v12, v8, v0.t1390; RV32-NEXT:    vmv1r.v v0, v111391; RV32-NEXT:    addi sp, sp, 161392; RV32-NEXT:    ret1393;1394; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:1395; RV64:       # %bb.0: # %entry1396; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1397; RV64-NEXT:    vmv1r.v v11, v01398; RV64-NEXT:    vmv1r.v v0, v101399; RV64-NEXT:    vmslt.vx v11, v8, a0, v0.t1400; RV64-NEXT:    vmxor.mm v0, v11, v101401; RV64-NEXT:    ret1402entry:1403  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(1404    <vscale x 2 x i1> %0,1405    <vscale x 2 x i64> %1,1406    i64 %2,1407    <vscale x 2 x i1> %3,1408    iXLen %4)1409 1410  ret <vscale x 2 x i1> %a1411}1412 1413define <vscale x 4 x i1> @intrinsic_vmsge_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1414; RV32-LABEL: intrinsic_vmsge_vx_nxv4i64_i64:1415; RV32:       # %bb.0: # %entry1416; RV32-NEXT:    addi sp, sp, -161417; RV32-NEXT:    sw a0, 8(sp)1418; RV32-NEXT:    sw a1, 12(sp)1419; RV32-NEXT:    addi a0, sp, 81420; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1421; RV32-NEXT:    vlse64.v v12, (a0), zero1422; RV32-NEXT:    vmsle.vv v0, v12, v81423; RV32-NEXT:    addi sp, sp, 161424; RV32-NEXT:    ret1425;1426; RV64-LABEL: intrinsic_vmsge_vx_nxv4i64_i64:1427; RV64:       # %bb.0: # %entry1428; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1429; RV64-NEXT:    vmslt.vx v12, v8, a01430; RV64-NEXT:    vmnot.m v0, v121431; RV64-NEXT:    ret1432entry:1433  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(1434    <vscale x 4 x i64> %0,1435    i64 %1,1436    iXLen %2)1437 1438  ret <vscale x 4 x i1> %a1439}1440 1441define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1442; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:1443; RV32:       # %bb.0: # %entry1444; RV32-NEXT:    addi sp, sp, -161445; RV32-NEXT:    sw a0, 8(sp)1446; RV32-NEXT:    sw a1, 12(sp)1447; RV32-NEXT:    addi a0, sp, 81448; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu1449; RV32-NEXT:    vlse64.v v16, (a0), zero1450; RV32-NEXT:    vmv1r.v v13, v01451; RV32-NEXT:    vmv1r.v v0, v121452; RV32-NEXT:    vmsle.vv v13, v16, v8, v0.t1453; RV32-NEXT:    vmv1r.v v0, v131454; RV32-NEXT:    addi sp, sp, 161455; RV32-NEXT:    ret1456;1457; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:1458; RV64:       # %bb.0: # %entry1459; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1460; RV64-NEXT:    vmv1r.v v13, v01461; RV64-NEXT:    vmv1r.v v0, v121462; RV64-NEXT:    vmslt.vx v13, v8, a0, v0.t1463; RV64-NEXT:    vmxor.mm v0, v13, v121464; RV64-NEXT:    ret1465entry:1466  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(1467    <vscale x 4 x i1> %0,1468    <vscale x 4 x i64> %1,1469    i64 %2,1470    <vscale x 4 x i1> %3,1471    iXLen %4)1472 1473  ret <vscale x 4 x i1> %a1474}1475 1476define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1477; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i8_i8:1478; CHECK:       # %bb.0: # %entry1479; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1480; CHECK-NEXT:    vmsgt.vi v0, v8, -161481; CHECK-NEXT:    ret1482entry:1483  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(1484    <vscale x 1 x i8> %0,1485    i8 -15,1486    iXLen %1)1487 1488  ret <vscale x 1 x i1> %a1489}1490 1491define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1492; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i8_i8:1493; CHECK:       # %bb.0: # %entry1494; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu1495; CHECK-NEXT:    vmv1r.v v10, v01496; CHECK-NEXT:    vmv1r.v v0, v91497; CHECK-NEXT:    vmsgt.vi v10, v8, -15, v0.t1498; CHECK-NEXT:    vmv1r.v v0, v101499; CHECK-NEXT:    ret1500entry:1501  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(1502    <vscale x 1 x i1> %0,1503    <vscale x 1 x i8> %1,1504    i8 -14,1505    <vscale x 1 x i1> %2,1506    iXLen %3)1507 1508  ret <vscale x 1 x i1> %a1509}1510 1511define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1512; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i8_i8:1513; CHECK:       # %bb.0: # %entry1514; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1515; CHECK-NEXT:    vmsgt.vi v0, v8, -141516; CHECK-NEXT:    ret1517entry:1518  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(1519    <vscale x 2 x i8> %0,1520    i8 -13,1521    iXLen %1)1522 1523  ret <vscale x 2 x i1> %a1524}1525 1526define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1527; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i8_i8:1528; CHECK:       # %bb.0: # %entry1529; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu1530; CHECK-NEXT:    vmv1r.v v10, v01531; CHECK-NEXT:    vmv1r.v v0, v91532; CHECK-NEXT:    vmsgt.vi v10, v8, -13, v0.t1533; CHECK-NEXT:    vmv1r.v v0, v101534; CHECK-NEXT:    ret1535entry:1536  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(1537    <vscale x 2 x i1> %0,1538    <vscale x 2 x i8> %1,1539    i8 -12,1540    <vscale x 2 x i1> %2,1541    iXLen %3)1542 1543  ret <vscale x 2 x i1> %a1544}1545 1546define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1547; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8:1548; CHECK:       # %bb.0: # %entry1549; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1550; CHECK-NEXT:    vmsgt.vi v0, v8, -121551; CHECK-NEXT:    ret1552entry:1553  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(1554    <vscale x 4 x i8> %0,1555    i8 -11,1556    iXLen %1)1557 1558  ret <vscale x 4 x i1> %a1559}1560 1561define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8_1(<vscale x 4 x i8> %0, iXLen %1) nounwind {1562; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8_1:1563; CHECK:       # %bb.0: # %entry1564; CHECK-NEXT:    li a1, 991565; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1566; CHECK-NEXT:    vmsgt.vx v0, v8, a11567; CHECK-NEXT:    ret1568entry:1569  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(1570    <vscale x 4 x i8> %0,1571    i8 100,1572    iXLen %1)1573 1574  ret <vscale x 4 x i1> %a1575}1576 1577define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8_2(<vscale x 4 x i8> %0, iXLen %1) nounwind {1578; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8_2:1579; CHECK:       # %bb.0: # %entry1580; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1581; CHECK-NEXT:    vmset.m v01582; CHECK-NEXT:    ret1583entry:1584  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(1585    <vscale x 4 x i8> %0,1586    i8 -128,1587    iXLen %1)1588 1589  ret <vscale x 4 x i1> %a1590}1591 1592define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1593; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i8_i8:1594; CHECK:       # %bb.0: # %entry1595; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu1596; CHECK-NEXT:    vmv1r.v v10, v01597; CHECK-NEXT:    vmv1r.v v0, v91598; CHECK-NEXT:    vmsgt.vi v10, v8, -11, v0.t1599; CHECK-NEXT:    vmv1r.v v0, v101600; CHECK-NEXT:    ret1601entry:1602  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(1603    <vscale x 4 x i1> %0,1604    <vscale x 4 x i8> %1,1605    i8 -10,1606    <vscale x 4 x i1> %2,1607    iXLen %3)1608 1609  ret <vscale x 4 x i1> %a1610}1611 1612define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1613; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i8_i8:1614; CHECK:       # %bb.0: # %entry1615; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1616; CHECK-NEXT:    vmsgt.vi v0, v8, -101617; CHECK-NEXT:    ret1618entry:1619  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(1620    <vscale x 8 x i8> %0,1621    i8 -9,1622    iXLen %1)1623 1624  ret <vscale x 8 x i1> %a1625}1626 1627define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1628; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i8_i8:1629; CHECK:       # %bb.0: # %entry1630; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu1631; CHECK-NEXT:    vmv1r.v v10, v01632; CHECK-NEXT:    vmv1r.v v0, v91633; CHECK-NEXT:    vmsgt.vi v10, v8, -9, v0.t1634; CHECK-NEXT:    vmv.v.v v0, v101635; CHECK-NEXT:    ret1636entry:1637  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(1638    <vscale x 8 x i1> %0,1639    <vscale x 8 x i8> %1,1640    i8 -8,1641    <vscale x 8 x i1> %2,1642    iXLen %3)1643 1644  ret <vscale x 8 x i1> %a1645}1646 1647define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1648; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i8_i8:1649; CHECK:       # %bb.0: # %entry1650; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1651; CHECK-NEXT:    vmsgt.vi v0, v8, -81652; CHECK-NEXT:    ret1653entry:1654  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(1655    <vscale x 16 x i8> %0,1656    i8 -7,1657    iXLen %1)1658 1659  ret <vscale x 16 x i1> %a1660}1661 1662define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1663; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i8_i8:1664; CHECK:       # %bb.0: # %entry1665; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu1666; CHECK-NEXT:    vmv1r.v v11, v01667; CHECK-NEXT:    vmv1r.v v0, v101668; CHECK-NEXT:    vmsgt.vi v11, v8, -7, v0.t1669; CHECK-NEXT:    vmv1r.v v0, v111670; CHECK-NEXT:    ret1671entry:1672  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(1673    <vscale x 16 x i1> %0,1674    <vscale x 16 x i8> %1,1675    i8 -6,1676    <vscale x 16 x i1> %2,1677    iXLen %3)1678 1679  ret <vscale x 16 x i1> %a1680}1681 1682define <vscale x 32 x i1> @intrinsic_vmsge_vi_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1683; CHECK-LABEL: intrinsic_vmsge_vi_nxv32i8_i8:1684; CHECK:       # %bb.0: # %entry1685; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1686; CHECK-NEXT:    vmsgt.vi v0, v8, -61687; CHECK-NEXT:    ret1688entry:1689  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(1690    <vscale x 32 x i8> %0,1691    i8 -5,1692    iXLen %1)1693 1694  ret <vscale x 32 x i1> %a1695}1696 1697define <vscale x 32 x i1> @intrinsic_vmsge_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1698; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv32i8_i8:1699; CHECK:       # %bb.0: # %entry1700; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu1701; CHECK-NEXT:    vmv1r.v v13, v01702; CHECK-NEXT:    vmv1r.v v0, v121703; CHECK-NEXT:    vmsgt.vi v13, v8, -5, v0.t1704; CHECK-NEXT:    vmv1r.v v0, v131705; CHECK-NEXT:    ret1706entry:1707  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(1708    <vscale x 32 x i1> %0,1709    <vscale x 32 x i8> %1,1710    i8 -4,1711    <vscale x 32 x i1> %2,1712    iXLen %3)1713 1714  ret <vscale x 32 x i1> %a1715}1716 1717define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1718; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i16_i16:1719; CHECK:       # %bb.0: # %entry1720; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1721; CHECK-NEXT:    vmsgt.vi v0, v8, -41722; CHECK-NEXT:    ret1723entry:1724  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(1725    <vscale x 1 x i16> %0,1726    i16 -3,1727    iXLen %1)1728 1729  ret <vscale x 1 x i1> %a1730}1731 1732define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1733; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i16_i16:1734; CHECK:       # %bb.0: # %entry1735; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu1736; CHECK-NEXT:    vmv1r.v v10, v01737; CHECK-NEXT:    vmv1r.v v0, v91738; CHECK-NEXT:    vmsgt.vi v10, v8, -3, v0.t1739; CHECK-NEXT:    vmv1r.v v0, v101740; CHECK-NEXT:    ret1741entry:1742  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(1743    <vscale x 1 x i1> %0,1744    <vscale x 1 x i16> %1,1745    i16 -2,1746    <vscale x 1 x i1> %2,1747    iXLen %3)1748 1749  ret <vscale x 1 x i1> %a1750}1751 1752define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1753; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i16_i16:1754; CHECK:       # %bb.0: # %entry1755; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1756; CHECK-NEXT:    vmsgt.vi v0, v8, -21757; CHECK-NEXT:    ret1758entry:1759  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(1760    <vscale x 2 x i16> %0,1761    i16 -1,1762    iXLen %1)1763 1764  ret <vscale x 2 x i1> %a1765}1766 1767define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1768; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i16_i16:1769; CHECK:       # %bb.0: # %entry1770; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu1771; CHECK-NEXT:    vmv1r.v v10, v01772; CHECK-NEXT:    vmv1r.v v0, v91773; CHECK-NEXT:    vmsgt.vi v10, v8, -1, v0.t1774; CHECK-NEXT:    vmv1r.v v0, v101775; CHECK-NEXT:    ret1776entry:1777  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(1778    <vscale x 2 x i1> %0,1779    <vscale x 2 x i16> %1,1780    i16 0,1781    <vscale x 2 x i1> %2,1782    iXLen %3)1783 1784  ret <vscale x 2 x i1> %a1785}1786 1787define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1788; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i16_i16:1789; CHECK:       # %bb.0: # %entry1790; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1791; CHECK-NEXT:    vmsgt.vi v0, v8, -11792; CHECK-NEXT:    ret1793entry:1794  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(1795    <vscale x 4 x i16> %0,1796    i16 0,1797    iXLen %1)1798 1799  ret <vscale x 4 x i1> %a1800}1801 1802define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1803; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i16_i16:1804; CHECK:       # %bb.0: # %entry1805; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu1806; CHECK-NEXT:    vmv1r.v v10, v01807; CHECK-NEXT:    vmv1r.v v0, v91808; CHECK-NEXT:    vmsgt.vi v10, v8, 0, v0.t1809; CHECK-NEXT:    vmv.v.v v0, v101810; CHECK-NEXT:    ret1811entry:1812  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(1813    <vscale x 4 x i1> %0,1814    <vscale x 4 x i16> %1,1815    i16 1,1816    <vscale x 4 x i1> %2,1817    iXLen %3)1818 1819  ret <vscale x 4 x i1> %a1820}1821 1822define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1823; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i16_i16:1824; CHECK:       # %bb.0: # %entry1825; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1826; CHECK-NEXT:    vmsgt.vi v0, v8, 11827; CHECK-NEXT:    ret1828entry:1829  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(1830    <vscale x 8 x i16> %0,1831    i16 2,1832    iXLen %1)1833 1834  ret <vscale x 8 x i1> %a1835}1836 1837define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1838; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i16_i16:1839; CHECK:       # %bb.0: # %entry1840; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu1841; CHECK-NEXT:    vmv1r.v v11, v01842; CHECK-NEXT:    vmv1r.v v0, v101843; CHECK-NEXT:    vmsgt.vi v11, v8, 2, v0.t1844; CHECK-NEXT:    vmv1r.v v0, v111845; CHECK-NEXT:    ret1846entry:1847  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(1848    <vscale x 8 x i1> %0,1849    <vscale x 8 x i16> %1,1850    i16 3,1851    <vscale x 8 x i1> %2,1852    iXLen %3)1853 1854  ret <vscale x 8 x i1> %a1855}1856 1857define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1858; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i16_i16:1859; CHECK:       # %bb.0: # %entry1860; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1861; CHECK-NEXT:    vmsgt.vi v0, v8, 31862; CHECK-NEXT:    ret1863entry:1864  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(1865    <vscale x 16 x i16> %0,1866    i16 4,1867    iXLen %1)1868 1869  ret <vscale x 16 x i1> %a1870}1871 1872define <vscale x 16 x i1> @intrinsic_vmsge_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1873; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv16i16_i16:1874; CHECK:       # %bb.0: # %entry1875; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu1876; CHECK-NEXT:    vmv1r.v v13, v01877; CHECK-NEXT:    vmv1r.v v0, v121878; CHECK-NEXT:    vmsgt.vi v13, v8, 4, v0.t1879; CHECK-NEXT:    vmv1r.v v0, v131880; CHECK-NEXT:    ret1881entry:1882  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(1883    <vscale x 16 x i1> %0,1884    <vscale x 16 x i16> %1,1885    i16 5,1886    <vscale x 16 x i1> %2,1887    iXLen %3)1888 1889  ret <vscale x 16 x i1> %a1890}1891 1892define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {1893; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i32_i32:1894; CHECK:       # %bb.0: # %entry1895; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1896; CHECK-NEXT:    vmsgt.vi v0, v8, 51897; CHECK-NEXT:    ret1898entry:1899  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(1900    <vscale x 1 x i32> %0,1901    i32 6,1902    iXLen %1)1903 1904  ret <vscale x 1 x i1> %a1905}1906 1907define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1908; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i32_i32:1909; CHECK:       # %bb.0: # %entry1910; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu1911; CHECK-NEXT:    vmv1r.v v10, v01912; CHECK-NEXT:    vmv1r.v v0, v91913; CHECK-NEXT:    vmsgt.vi v10, v8, 6, v0.t1914; CHECK-NEXT:    vmv1r.v v0, v101915; CHECK-NEXT:    ret1916entry:1917  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(1918    <vscale x 1 x i1> %0,1919    <vscale x 1 x i32> %1,1920    i32 7,1921    <vscale x 1 x i1> %2,1922    iXLen %3)1923 1924  ret <vscale x 1 x i1> %a1925}1926 1927define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {1928; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i32_i32:1929; CHECK:       # %bb.0: # %entry1930; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1931; CHECK-NEXT:    vmsgt.vi v0, v8, 71932; CHECK-NEXT:    ret1933entry:1934  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(1935    <vscale x 2 x i32> %0,1936    i32 8,1937    iXLen %1)1938 1939  ret <vscale x 2 x i1> %a1940}1941 1942define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1943; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i32_i32:1944; CHECK:       # %bb.0: # %entry1945; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu1946; CHECK-NEXT:    vmv1r.v v10, v01947; CHECK-NEXT:    vmv1r.v v0, v91948; CHECK-NEXT:    vmsgt.vi v10, v8, 8, v0.t1949; CHECK-NEXT:    vmv.v.v v0, v101950; CHECK-NEXT:    ret1951entry:1952  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(1953    <vscale x 2 x i1> %0,1954    <vscale x 2 x i32> %1,1955    i32 9,1956    <vscale x 2 x i1> %2,1957    iXLen %3)1958 1959  ret <vscale x 2 x i1> %a1960}1961 1962define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {1963; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i32_i32:1964; CHECK:       # %bb.0: # %entry1965; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1966; CHECK-NEXT:    vmsgt.vi v0, v8, 91967; CHECK-NEXT:    ret1968entry:1969  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(1970    <vscale x 4 x i32> %0,1971    i32 10,1972    iXLen %1)1973 1974  ret <vscale x 4 x i1> %a1975}1976 1977define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1978; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i32_i32:1979; CHECK:       # %bb.0: # %entry1980; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu1981; CHECK-NEXT:    vmv1r.v v11, v01982; CHECK-NEXT:    vmv1r.v v0, v101983; CHECK-NEXT:    vmsgt.vi v11, v8, 10, v0.t1984; CHECK-NEXT:    vmv1r.v v0, v111985; CHECK-NEXT:    ret1986entry:1987  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(1988    <vscale x 4 x i1> %0,1989    <vscale x 4 x i32> %1,1990    i32 11,1991    <vscale x 4 x i1> %2,1992    iXLen %3)1993 1994  ret <vscale x 4 x i1> %a1995}1996 1997define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {1998; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i32_i32:1999; CHECK:       # %bb.0: # %entry2000; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2001; CHECK-NEXT:    vmsgt.vi v0, v8, 112002; CHECK-NEXT:    ret2003entry:2004  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(2005    <vscale x 8 x i32> %0,2006    i32 12,2007    iXLen %1)2008 2009  ret <vscale x 8 x i1> %a2010}2011 2012define <vscale x 8 x i1> @intrinsic_vmsge_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2013; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv8i32_i32:2014; CHECK:       # %bb.0: # %entry2015; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu2016; CHECK-NEXT:    vmv1r.v v13, v02017; CHECK-NEXT:    vmv1r.v v0, v122018; CHECK-NEXT:    vmsgt.vi v13, v8, 12, v0.t2019; CHECK-NEXT:    vmv1r.v v0, v132020; CHECK-NEXT:    ret2021entry:2022  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(2023    <vscale x 8 x i1> %0,2024    <vscale x 8 x i32> %1,2025    i32 13,2026    <vscale x 8 x i1> %2,2027    iXLen %3)2028 2029  ret <vscale x 8 x i1> %a2030}2031 2032define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {2033; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i64_i64:2034; CHECK:       # %bb.0: # %entry2035; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2036; CHECK-NEXT:    vmsgt.vi v0, v8, 82037; CHECK-NEXT:    ret2038entry:2039  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(2040    <vscale x 1 x i64> %0,2041    i64 9,2042    iXLen %1)2043 2044  ret <vscale x 1 x i1> %a2045}2046 2047define <vscale x 1 x i1> @intrinsic_vmsge_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2048; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv1i64_i64:2049; CHECK:       # %bb.0: # %entry2050; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu2051; CHECK-NEXT:    vmv1r.v v10, v02052; CHECK-NEXT:    vmv1r.v v0, v92053; CHECK-NEXT:    vmsgt.vi v10, v8, 8, v0.t2054; CHECK-NEXT:    vmv.v.v v0, v102055; CHECK-NEXT:    ret2056entry:2057  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(2058    <vscale x 1 x i1> %0,2059    <vscale x 1 x i64> %1,2060    i64 9,2061    <vscale x 1 x i1> %2,2062    iXLen %3)2063 2064  ret <vscale x 1 x i1> %a2065}2066 2067define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {2068; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i64_i64:2069; CHECK:       # %bb.0: # %entry2070; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2071; CHECK-NEXT:    vmsgt.vi v0, v8, 82072; CHECK-NEXT:    ret2073entry:2074  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(2075    <vscale x 2 x i64> %0,2076    i64 9,2077    iXLen %1)2078 2079  ret <vscale x 2 x i1> %a2080}2081 2082define <vscale x 2 x i1> @intrinsic_vmsge_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2083; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv2i64_i64:2084; CHECK:       # %bb.0: # %entry2085; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu2086; CHECK-NEXT:    vmv1r.v v11, v02087; CHECK-NEXT:    vmv1r.v v0, v102088; CHECK-NEXT:    vmsgt.vi v11, v8, 8, v0.t2089; CHECK-NEXT:    vmv1r.v v0, v112090; CHECK-NEXT:    ret2091entry:2092  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(2093    <vscale x 2 x i1> %0,2094    <vscale x 2 x i64> %1,2095    i64 9,2096    <vscale x 2 x i1> %2,2097    iXLen %3)2098 2099  ret <vscale x 2 x i1> %a2100}2101 2102define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2103; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i64_i64:2104; CHECK:       # %bb.0: # %entry2105; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2106; CHECK-NEXT:    vmsgt.vi v0, v8, 82107; CHECK-NEXT:    ret2108entry:2109  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(2110    <vscale x 4 x i64> %0,2111    i64 9,2112    iXLen %1)2113 2114  ret <vscale x 4 x i1> %a2115}2116 2117define <vscale x 4 x i1> @intrinsic_vmsge_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2118; CHECK-LABEL: intrinsic_vmsge_mask_vi_nxv4i64_i64:2119; CHECK:       # %bb.0: # %entry2120; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu2121; CHECK-NEXT:    vmv1r.v v13, v02122; CHECK-NEXT:    vmv1r.v v0, v122123; CHECK-NEXT:    vmsgt.vi v13, v8, 8, v0.t2124; CHECK-NEXT:    vmv1r.v v0, v132125; CHECK-NEXT:    ret2126entry:2127  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(2128    <vscale x 4 x i1> %0,2129    <vscale x 4 x i64> %1,2130    i64 9,2131    <vscale x 4 x i1> %2,2132    iXLen %3)2133 2134  ret <vscale x 4 x i1> %a2135}2136 2137; Test cases where the mask and maskedoff are the same value.2138define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, iXLen %3) nounwind {2139; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8:2140; CHECK:       # %bb.0: # %entry2141; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma2142; CHECK-NEXT:    vmslt.vx v8, v8, a02143; CHECK-NEXT:    vmandn.mm v0, v0, v82144; CHECK-NEXT:    ret2145entry:2146  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(2147    <vscale x 1 x i1> %0,2148    <vscale x 1 x i8> %1,2149    i8 %2,2150    <vscale x 1 x i1> %0,2151    iXLen %3)2152 2153  ret <vscale x 1 x i1> %a2154}2155 2156define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, iXLen %3) nounwind {2157; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8:2158; CHECK:       # %bb.0: # %entry2159; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma2160; CHECK-NEXT:    vmslt.vx v8, v8, a02161; CHECK-NEXT:    vmandn.mm v0, v0, v82162; CHECK-NEXT:    ret2163entry:2164  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(2165    <vscale x 2 x i1> %0,2166    <vscale x 2 x i8> %1,2167    i8 %2,2168    <vscale x 2 x i1> %0,2169    iXLen %3)2170 2171  ret <vscale x 2 x i1> %a2172}2173 2174define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, iXLen %3) nounwind {2175; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8:2176; CHECK:       # %bb.0: # %entry2177; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma2178; CHECK-NEXT:    vmslt.vx v8, v8, a02179; CHECK-NEXT:    vmandn.mm v0, v0, v82180; CHECK-NEXT:    ret2181entry:2182  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(2183    <vscale x 4 x i1> %0,2184    <vscale x 4 x i8> %1,2185    i8 %2,2186    <vscale x 4 x i1> %0,2187    iXLen %3)2188 2189  ret <vscale x 4 x i1> %a2190}2191 2192define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, iXLen %3) nounwind {2193; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8:2194; CHECK:       # %bb.0: # %entry2195; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma2196; CHECK-NEXT:    vmslt.vx v8, v8, a02197; CHECK-NEXT:    vmandn.mm v0, v0, v82198; CHECK-NEXT:    ret2199entry:2200  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(2201    <vscale x 8 x i1> %0,2202    <vscale x 8 x i8> %1,2203    i8 %2,2204    <vscale x 8 x i1> %0,2205    iXLen %3)2206 2207  ret <vscale x 8 x i1> %a2208}2209 2210define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, iXLen %3) nounwind {2211; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8:2212; CHECK:       # %bb.0: # %entry2213; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma2214; CHECK-NEXT:    vmslt.vx v10, v8, a02215; CHECK-NEXT:    vmandn.mm v0, v0, v102216; CHECK-NEXT:    ret2217entry:2218  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(2219    <vscale x 16 x i1> %0,2220    <vscale x 16 x i8> %1,2221    i8 %2,2222    <vscale x 16 x i1> %0,2223    iXLen %3)2224 2225  ret <vscale x 16 x i1> %a2226}2227 2228define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, iXLen %3) nounwind {2229; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8:2230; CHECK:       # %bb.0: # %entry2231; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma2232; CHECK-NEXT:    vmslt.vx v12, v8, a02233; CHECK-NEXT:    vmandn.mm v0, v0, v122234; CHECK-NEXT:    ret2235entry:2236  %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(2237    <vscale x 32 x i1> %0,2238    <vscale x 32 x i8> %1,2239    i8 %2,2240    <vscale x 32 x i1> %0,2241    iXLen %3)2242 2243  ret <vscale x 32 x i1> %a2244}2245 2246define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, iXLen %3) nounwind {2247; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16:2248; CHECK:       # %bb.0: # %entry2249; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2250; CHECK-NEXT:    vmslt.vx v8, v8, a02251; CHECK-NEXT:    vmandn.mm v0, v0, v82252; CHECK-NEXT:    ret2253entry:2254  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(2255    <vscale x 1 x i1> %0,2256    <vscale x 1 x i16> %1,2257    i16 %2,2258    <vscale x 1 x i1> %0,2259    iXLen %3)2260 2261  ret <vscale x 1 x i1> %a2262}2263 2264define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, iXLen %3) nounwind {2265; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16:2266; CHECK:       # %bb.0: # %entry2267; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2268; CHECK-NEXT:    vmslt.vx v8, v8, a02269; CHECK-NEXT:    vmandn.mm v0, v0, v82270; CHECK-NEXT:    ret2271entry:2272  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(2273    <vscale x 2 x i1> %0,2274    <vscale x 2 x i16> %1,2275    i16 %2,2276    <vscale x 2 x i1> %0,2277    iXLen %3)2278 2279  ret <vscale x 2 x i1> %a2280}2281 2282define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, iXLen %3) nounwind {2283; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16:2284; CHECK:       # %bb.0: # %entry2285; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2286; CHECK-NEXT:    vmslt.vx v8, v8, a02287; CHECK-NEXT:    vmandn.mm v0, v0, v82288; CHECK-NEXT:    ret2289entry:2290  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(2291    <vscale x 4 x i1> %0,2292    <vscale x 4 x i16> %1,2293    i16 %2,2294    <vscale x 4 x i1> %0,2295    iXLen %3)2296 2297  ret <vscale x 4 x i1> %a2298}2299 2300define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, iXLen %3) nounwind {2301; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16:2302; CHECK:       # %bb.0: # %entry2303; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2304; CHECK-NEXT:    vmslt.vx v10, v8, a02305; CHECK-NEXT:    vmandn.mm v0, v0, v102306; CHECK-NEXT:    ret2307entry:2308  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(2309    <vscale x 8 x i1> %0,2310    <vscale x 8 x i16> %1,2311    i16 %2,2312    <vscale x 8 x i1> %0,2313    iXLen %3)2314 2315  ret <vscale x 8 x i1> %a2316}2317 2318define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, iXLen %3) nounwind {2319; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16:2320; CHECK:       # %bb.0: # %entry2321; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2322; CHECK-NEXT:    vmslt.vx v12, v8, a02323; CHECK-NEXT:    vmandn.mm v0, v0, v122324; CHECK-NEXT:    ret2325entry:2326  %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(2327    <vscale x 16 x i1> %0,2328    <vscale x 16 x i16> %1,2329    i16 %2,2330    <vscale x 16 x i1> %0,2331    iXLen %3)2332 2333  ret <vscale x 16 x i1> %a2334}2335 2336define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {2337; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32:2338; CHECK:       # %bb.0: # %entry2339; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2340; CHECK-NEXT:    vmslt.vx v8, v8, a02341; CHECK-NEXT:    vmandn.mm v0, v0, v82342; CHECK-NEXT:    ret2343entry:2344  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(2345    <vscale x 1 x i1> %0,2346    <vscale x 1 x i32> %1,2347    i32 %2,2348    <vscale x 1 x i1> %0,2349    iXLen %3)2350 2351  ret <vscale x 1 x i1> %a2352}2353 2354define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {2355; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32:2356; CHECK:       # %bb.0: # %entry2357; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2358; CHECK-NEXT:    vmslt.vx v8, v8, a02359; CHECK-NEXT:    vmandn.mm v0, v0, v82360; CHECK-NEXT:    ret2361entry:2362  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(2363    <vscale x 2 x i1> %0,2364    <vscale x 2 x i32> %1,2365    i32 %2,2366    <vscale x 2 x i1> %0,2367    iXLen %3)2368 2369  ret <vscale x 2 x i1> %a2370}2371 2372define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {2373; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32:2374; CHECK:       # %bb.0: # %entry2375; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2376; CHECK-NEXT:    vmslt.vx v10, v8, a02377; CHECK-NEXT:    vmandn.mm v0, v0, v102378; CHECK-NEXT:    ret2379entry:2380  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(2381    <vscale x 4 x i1> %0,2382    <vscale x 4 x i32> %1,2383    i32 %2,2384    <vscale x 4 x i1> %0,2385    iXLen %3)2386 2387  ret <vscale x 4 x i1> %a2388}2389 2390define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {2391; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32:2392; CHECK:       # %bb.0: # %entry2393; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2394; CHECK-NEXT:    vmslt.vx v12, v8, a02395; CHECK-NEXT:    vmandn.mm v0, v0, v122396; CHECK-NEXT:    ret2397entry:2398  %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(2399    <vscale x 8 x i1> %0,2400    <vscale x 8 x i32> %1,2401    i32 %2,2402    <vscale x 8 x i1> %0,2403    iXLen %3)2404 2405  ret <vscale x 8 x i1> %a2406}2407 2408define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {2409; RV32-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:2410; RV32:       # %bb.0: # %entry2411; RV32-NEXT:    addi sp, sp, -162412; RV32-NEXT:    sw a0, 8(sp)2413; RV32-NEXT:    sw a1, 12(sp)2414; RV32-NEXT:    addi a0, sp, 82415; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu2416; RV32-NEXT:    vlse64.v v9, (a0), zero2417; RV32-NEXT:    vmsle.vv v0, v9, v8, v0.t2418; RV32-NEXT:    addi sp, sp, 162419; RV32-NEXT:    ret2420;2421; RV64-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:2422; RV64:       # %bb.0: # %entry2423; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2424; RV64-NEXT:    vmslt.vx v8, v8, a02425; RV64-NEXT:    vmandn.mm v0, v0, v82426; RV64-NEXT:    ret2427entry:2428  %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(2429    <vscale x 1 x i1> %0,2430    <vscale x 1 x i64> %1,2431    i64 %2,2432    <vscale x 1 x i1> %0,2433    iXLen %3)2434 2435  ret <vscale x 1 x i1> %a2436}2437 2438define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, iXLen %3) nounwind {2439; RV32-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:2440; RV32:       # %bb.0: # %entry2441; RV32-NEXT:    addi sp, sp, -162442; RV32-NEXT:    sw a0, 8(sp)2443; RV32-NEXT:    sw a1, 12(sp)2444; RV32-NEXT:    addi a0, sp, 82445; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu2446; RV32-NEXT:    vlse64.v v12, (a0), zero2447; RV32-NEXT:    vmv1r.v v10, v02448; RV32-NEXT:    vmsle.vv v10, v12, v8, v0.t2449; RV32-NEXT:    vmv1r.v v0, v102450; RV32-NEXT:    addi sp, sp, 162451; RV32-NEXT:    ret2452;2453; RV64-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:2454; RV64:       # %bb.0: # %entry2455; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2456; RV64-NEXT:    vmslt.vx v10, v8, a02457; RV64-NEXT:    vmandn.mm v0, v0, v102458; RV64-NEXT:    ret2459entry:2460  %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(2461    <vscale x 2 x i1> %0,2462    <vscale x 2 x i64> %1,2463    i64 %2,2464    <vscale x 2 x i1> %0,2465    iXLen %3)2466 2467  ret <vscale x 2 x i1> %a2468}2469 2470define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, iXLen %3) nounwind {2471; RV32-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:2472; RV32:       # %bb.0: # %entry2473; RV32-NEXT:    addi sp, sp, -162474; RV32-NEXT:    sw a0, 8(sp)2475; RV32-NEXT:    sw a1, 12(sp)2476; RV32-NEXT:    addi a0, sp, 82477; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu2478; RV32-NEXT:    vlse64.v v16, (a0), zero2479; RV32-NEXT:    vmv1r.v v12, v02480; RV32-NEXT:    vmsle.vv v12, v16, v8, v0.t2481; RV32-NEXT:    vmv1r.v v0, v122482; RV32-NEXT:    addi sp, sp, 162483; RV32-NEXT:    ret2484;2485; RV64-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:2486; RV64:       # %bb.0: # %entry2487; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2488; RV64-NEXT:    vmslt.vx v12, v8, a02489; RV64-NEXT:    vmandn.mm v0, v0, v122490; RV64-NEXT:    ret2491entry:2492  %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(2493    <vscale x 4 x i1> %0,2494    <vscale x 4 x i64> %1,2495    i64 %2,2496    <vscale x 4 x i1> %0,2497    iXLen %3)2498 2499  ret <vscale x 4 x i1> %a2500}2501