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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i1> @intrinsic_vmsgeu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    vmsleu.vv v0, v9, v812; CHECK-NEXT:    ret13entry:14  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(15    <vscale x 1 x i8> %0,16    <vscale x 1 x i8> %1,17    iXLen %2)18 19  ret <vscale x 1 x i1> %a20}21 22define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:24; CHECK:       # %bb.0: # %entry25; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu26; CHECK-NEXT:    vmv1r.v v11, v027; CHECK-NEXT:    vmsleu.vv v0, v9, v828; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t29; CHECK-NEXT:    vmv1r.v v0, v1130; CHECK-NEXT:    ret31entry:32  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(33    <vscale x 1 x i8> %1,34    <vscale x 1 x i8> %2,35    iXLen %4)36  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(37    <vscale x 1 x i1> %0,38    <vscale x 1 x i8> %2,39    <vscale x 1 x i8> %3,40    <vscale x 1 x i1> %mask,41    iXLen %4)42 43  ret <vscale x 1 x i1> %a44}45 46define <vscale x 2 x i1> @intrinsic_vmsgeu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i8_nxv2i8:48; CHECK:       # %bb.0: # %entry49; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma50; CHECK-NEXT:    vmsleu.vv v0, v9, v851; CHECK-NEXT:    ret52entry:53  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(54    <vscale x 2 x i8> %0,55    <vscale x 2 x i8> %1,56    iXLen %2)57 58  ret <vscale x 2 x i1> %a59}60 61define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, iXLen %4) nounwind {62; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:63; CHECK:       # %bb.0: # %entry64; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu65; CHECK-NEXT:    vmv1r.v v11, v066; CHECK-NEXT:    vmsleu.vv v0, v9, v867; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t68; CHECK-NEXT:    vmv1r.v v0, v1169; CHECK-NEXT:    ret70entry:71  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(72    <vscale x 2 x i8> %1,73    <vscale x 2 x i8> %2,74    iXLen %4)75  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(76    <vscale x 2 x i1> %0,77    <vscale x 2 x i8> %2,78    <vscale x 2 x i8> %3,79    <vscale x 2 x i1> %mask,80    iXLen %4)81 82  ret <vscale x 2 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmsgeu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i8_nxv4i8:87; CHECK:       # %bb.0: # %entry88; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma89; CHECK-NEXT:    vmsleu.vv v0, v9, v890; CHECK-NEXT:    ret91entry:92  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(93    <vscale x 4 x i8> %0,94    <vscale x 4 x i8> %1,95    iXLen %2)96 97  ret <vscale x 4 x i1> %a98}99 100define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:102; CHECK:       # %bb.0: # %entry103; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu104; CHECK-NEXT:    vmv1r.v v11, v0105; CHECK-NEXT:    vmsleu.vv v0, v9, v8106; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t107; CHECK-NEXT:    vmv1r.v v0, v11108; CHECK-NEXT:    ret109entry:110  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(111    <vscale x 4 x i8> %1,112    <vscale x 4 x i8> %2,113    iXLen %4)114  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(115    <vscale x 4 x i1> %0,116    <vscale x 4 x i8> %2,117    <vscale x 4 x i8> %3,118    <vscale x 4 x i1> %mask,119    iXLen %4)120 121  ret <vscale x 4 x i1> %a122}123 124define <vscale x 8 x i1> @intrinsic_vmsgeu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i8_nxv8i8:126; CHECK:       # %bb.0: # %entry127; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma128; CHECK-NEXT:    vmsleu.vv v0, v9, v8129; CHECK-NEXT:    ret130entry:131  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(132    <vscale x 8 x i8> %0,133    <vscale x 8 x i8> %1,134    iXLen %2)135 136  ret <vscale x 8 x i1> %a137}138 139define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu143; CHECK-NEXT:    vmv1r.v v11, v0144; CHECK-NEXT:    vmsleu.vv v0, v9, v8145; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t146; CHECK-NEXT:    vmv.v.v v0, v11147; CHECK-NEXT:    ret148entry:149  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(150    <vscale x 8 x i8> %1,151    <vscale x 8 x i8> %2,152    iXLen %4)153  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(154    <vscale x 8 x i1> %0,155    <vscale x 8 x i8> %2,156    <vscale x 8 x i8> %3,157    <vscale x 8 x i1> %mask,158    iXLen %4)159 160  ret <vscale x 8 x i1> %a161}162 163define <vscale x 16 x i1> @intrinsic_vmsgeu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv16i8_nxv16i8:165; CHECK:       # %bb.0: # %entry166; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma167; CHECK-NEXT:    vmsleu.vv v0, v10, v8168; CHECK-NEXT:    ret169entry:170  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(171    <vscale x 16 x i8> %0,172    <vscale x 16 x i8> %1,173    iXLen %2)174 175  ret <vscale x 16 x i1> %a176}177 178define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, iXLen %4) nounwind {179; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:180; CHECK:       # %bb.0: # %entry181; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu182; CHECK-NEXT:    vmv1r.v v14, v0183; CHECK-NEXT:    vmsleu.vv v0, v10, v8184; CHECK-NEXT:    vmsleu.vv v14, v12, v10, v0.t185; CHECK-NEXT:    vmv1r.v v0, v14186; CHECK-NEXT:    ret187entry:188  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(189    <vscale x 16 x i8> %1,190    <vscale x 16 x i8> %2,191    iXLen %4)192  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(193    <vscale x 16 x i1> %0,194    <vscale x 16 x i8> %2,195    <vscale x 16 x i8> %3,196    <vscale x 16 x i1> %mask,197    iXLen %4)198 199  ret <vscale x 16 x i1> %a200}201 202define <vscale x 32 x i1> @intrinsic_vmsgeu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv32i8_nxv32i8:204; CHECK:       # %bb.0: # %entry205; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma206; CHECK-NEXT:    vmsleu.vv v0, v12, v8207; CHECK-NEXT:    ret208entry:209  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(210    <vscale x 32 x i8> %0,211    <vscale x 32 x i8> %1,212    iXLen %2)213 214  ret <vscale x 32 x i1> %a215}216 217define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, iXLen %4) nounwind {218; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:219; CHECK:       # %bb.0: # %entry220; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu221; CHECK-NEXT:    vmv1r.v v20, v0222; CHECK-NEXT:    vmsleu.vv v0, v12, v8223; CHECK-NEXT:    vmsleu.vv v20, v16, v12, v0.t224; CHECK-NEXT:    vmv1r.v v0, v20225; CHECK-NEXT:    ret226entry:227  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(228    <vscale x 32 x i8> %1,229    <vscale x 32 x i8> %2,230    iXLen %4)231  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(232    <vscale x 32 x i1> %0,233    <vscale x 32 x i8> %2,234    <vscale x 32 x i8> %3,235    <vscale x 32 x i1> %mask,236    iXLen %4)237 238  ret <vscale x 32 x i1> %a239}240 241define <vscale x 1 x i1> @intrinsic_vmsgeu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {242; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i16_nxv1i16:243; CHECK:       # %bb.0: # %entry244; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma245; CHECK-NEXT:    vmsleu.vv v0, v9, v8246; CHECK-NEXT:    ret247entry:248  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(249    <vscale x 1 x i16> %0,250    <vscale x 1 x i16> %1,251    iXLen %2)252 253  ret <vscale x 1 x i1> %a254}255 256define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, iXLen %4) nounwind {257; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:258; CHECK:       # %bb.0: # %entry259; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu260; CHECK-NEXT:    vmv1r.v v11, v0261; CHECK-NEXT:    vmsleu.vv v0, v9, v8262; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t263; CHECK-NEXT:    vmv1r.v v0, v11264; CHECK-NEXT:    ret265entry:266  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(267    <vscale x 1 x i16> %1,268    <vscale x 1 x i16> %2,269    iXLen %4)270  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(271    <vscale x 1 x i1> %0,272    <vscale x 1 x i16> %2,273    <vscale x 1 x i16> %3,274    <vscale x 1 x i1> %mask,275    iXLen %4)276 277  ret <vscale x 1 x i1> %a278}279 280define <vscale x 2 x i1> @intrinsic_vmsgeu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {281; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i16_nxv2i16:282; CHECK:       # %bb.0: # %entry283; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma284; CHECK-NEXT:    vmsleu.vv v0, v9, v8285; CHECK-NEXT:    ret286entry:287  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(288    <vscale x 2 x i16> %0,289    <vscale x 2 x i16> %1,290    iXLen %2)291 292  ret <vscale x 2 x i1> %a293}294 295define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:297; CHECK:       # %bb.0: # %entry298; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu299; CHECK-NEXT:    vmv1r.v v11, v0300; CHECK-NEXT:    vmsleu.vv v0, v9, v8301; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t302; CHECK-NEXT:    vmv1r.v v0, v11303; CHECK-NEXT:    ret304entry:305  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(306    <vscale x 2 x i16> %1,307    <vscale x 2 x i16> %2,308    iXLen %4)309  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(310    <vscale x 2 x i1> %0,311    <vscale x 2 x i16> %2,312    <vscale x 2 x i16> %3,313    <vscale x 2 x i1> %mask,314    iXLen %4)315 316  ret <vscale x 2 x i1> %a317}318 319define <vscale x 4 x i1> @intrinsic_vmsgeu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {320; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i16_nxv4i16:321; CHECK:       # %bb.0: # %entry322; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma323; CHECK-NEXT:    vmsleu.vv v0, v9, v8324; CHECK-NEXT:    ret325entry:326  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(327    <vscale x 4 x i16> %0,328    <vscale x 4 x i16> %1,329    iXLen %2)330 331  ret <vscale x 4 x i1> %a332}333 334define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, iXLen %4) nounwind {335; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:336; CHECK:       # %bb.0: # %entry337; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu338; CHECK-NEXT:    vmv1r.v v11, v0339; CHECK-NEXT:    vmsleu.vv v0, v9, v8340; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t341; CHECK-NEXT:    vmv.v.v v0, v11342; CHECK-NEXT:    ret343entry:344  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(345    <vscale x 4 x i16> %1,346    <vscale x 4 x i16> %2,347    iXLen %4)348  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(349    <vscale x 4 x i1> %0,350    <vscale x 4 x i16> %2,351    <vscale x 4 x i16> %3,352    <vscale x 4 x i1> %mask,353    iXLen %4)354 355  ret <vscale x 4 x i1> %a356}357 358define <vscale x 8 x i1> @intrinsic_vmsgeu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {359; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i16_nxv8i16:360; CHECK:       # %bb.0: # %entry361; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma362; CHECK-NEXT:    vmsleu.vv v0, v10, v8363; CHECK-NEXT:    ret364entry:365  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(366    <vscale x 8 x i16> %0,367    <vscale x 8 x i16> %1,368    iXLen %2)369 370  ret <vscale x 8 x i1> %a371}372 373define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, iXLen %4) nounwind {374; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:375; CHECK:       # %bb.0: # %entry376; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu377; CHECK-NEXT:    vmv1r.v v14, v0378; CHECK-NEXT:    vmsleu.vv v0, v10, v8379; CHECK-NEXT:    vmsleu.vv v14, v12, v10, v0.t380; CHECK-NEXT:    vmv1r.v v0, v14381; CHECK-NEXT:    ret382entry:383  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(384    <vscale x 8 x i16> %1,385    <vscale x 8 x i16> %2,386    iXLen %4)387  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(388    <vscale x 8 x i1> %0,389    <vscale x 8 x i16> %2,390    <vscale x 8 x i16> %3,391    <vscale x 8 x i1> %mask,392    iXLen %4)393 394  ret <vscale x 8 x i1> %a395}396 397define <vscale x 16 x i1> @intrinsic_vmsgeu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv16i16_nxv16i16:399; CHECK:       # %bb.0: # %entry400; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma401; CHECK-NEXT:    vmsleu.vv v0, v12, v8402; CHECK-NEXT:    ret403entry:404  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(405    <vscale x 16 x i16> %0,406    <vscale x 16 x i16> %1,407    iXLen %2)408 409  ret <vscale x 16 x i1> %a410}411 412define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, iXLen %4) nounwind {413; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:414; CHECK:       # %bb.0: # %entry415; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu416; CHECK-NEXT:    vmv1r.v v20, v0417; CHECK-NEXT:    vmsleu.vv v0, v12, v8418; CHECK-NEXT:    vmsleu.vv v20, v16, v12, v0.t419; CHECK-NEXT:    vmv1r.v v0, v20420; CHECK-NEXT:    ret421entry:422  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(423    <vscale x 16 x i16> %1,424    <vscale x 16 x i16> %2,425    iXLen %4)426  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(427    <vscale x 16 x i1> %0,428    <vscale x 16 x i16> %2,429    <vscale x 16 x i16> %3,430    <vscale x 16 x i1> %mask,431    iXLen %4)432 433  ret <vscale x 16 x i1> %a434}435 436define <vscale x 1 x i1> @intrinsic_vmsgeu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i32_nxv1i32:438; CHECK:       # %bb.0: # %entry439; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma440; CHECK-NEXT:    vmsleu.vv v0, v9, v8441; CHECK-NEXT:    ret442entry:443  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(444    <vscale x 1 x i32> %0,445    <vscale x 1 x i32> %1,446    iXLen %2)447 448  ret <vscale x 1 x i1> %a449}450 451define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, iXLen %4) nounwind {452; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:453; CHECK:       # %bb.0: # %entry454; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu455; CHECK-NEXT:    vmv1r.v v11, v0456; CHECK-NEXT:    vmsleu.vv v0, v9, v8457; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t458; CHECK-NEXT:    vmv1r.v v0, v11459; CHECK-NEXT:    ret460entry:461  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(462    <vscale x 1 x i32> %1,463    <vscale x 1 x i32> %2,464    iXLen %4)465  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(466    <vscale x 1 x i1> %0,467    <vscale x 1 x i32> %2,468    <vscale x 1 x i32> %3,469    <vscale x 1 x i1> %mask,470    iXLen %4)471 472  ret <vscale x 1 x i1> %a473}474 475define <vscale x 2 x i1> @intrinsic_vmsgeu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i32_nxv2i32:477; CHECK:       # %bb.0: # %entry478; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma479; CHECK-NEXT:    vmsleu.vv v0, v9, v8480; CHECK-NEXT:    ret481entry:482  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(483    <vscale x 2 x i32> %0,484    <vscale x 2 x i32> %1,485    iXLen %2)486 487  ret <vscale x 2 x i1> %a488}489 490define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, iXLen %4) nounwind {491; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:492; CHECK:       # %bb.0: # %entry493; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu494; CHECK-NEXT:    vmv1r.v v11, v0495; CHECK-NEXT:    vmsleu.vv v0, v9, v8496; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t497; CHECK-NEXT:    vmv.v.v v0, v11498; CHECK-NEXT:    ret499entry:500  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(501    <vscale x 2 x i32> %1,502    <vscale x 2 x i32> %2,503    iXLen %4)504  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(505    <vscale x 2 x i1> %0,506    <vscale x 2 x i32> %2,507    <vscale x 2 x i32> %3,508    <vscale x 2 x i1> %mask,509    iXLen %4)510 511  ret <vscale x 2 x i1> %a512}513 514define <vscale x 4 x i1> @intrinsic_vmsgeu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {515; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i32_nxv4i32:516; CHECK:       # %bb.0: # %entry517; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma518; CHECK-NEXT:    vmsleu.vv v0, v10, v8519; CHECK-NEXT:    ret520entry:521  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(522    <vscale x 4 x i32> %0,523    <vscale x 4 x i32> %1,524    iXLen %2)525 526  ret <vscale x 4 x i1> %a527}528 529define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:531; CHECK:       # %bb.0: # %entry532; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu533; CHECK-NEXT:    vmv1r.v v14, v0534; CHECK-NEXT:    vmsleu.vv v0, v10, v8535; CHECK-NEXT:    vmsleu.vv v14, v12, v10, v0.t536; CHECK-NEXT:    vmv1r.v v0, v14537; CHECK-NEXT:    ret538entry:539  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(540    <vscale x 4 x i32> %1,541    <vscale x 4 x i32> %2,542    iXLen %4)543  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(544    <vscale x 4 x i1> %0,545    <vscale x 4 x i32> %2,546    <vscale x 4 x i32> %3,547    <vscale x 4 x i1> %mask,548    iXLen %4)549 550  ret <vscale x 4 x i1> %a551}552 553define <vscale x 8 x i1> @intrinsic_vmsgeu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {554; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv8i32_nxv8i32:555; CHECK:       # %bb.0: # %entry556; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma557; CHECK-NEXT:    vmsleu.vv v0, v12, v8558; CHECK-NEXT:    ret559entry:560  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(561    <vscale x 8 x i32> %0,562    <vscale x 8 x i32> %1,563    iXLen %2)564 565  ret <vscale x 8 x i1> %a566}567 568define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:570; CHECK:       # %bb.0: # %entry571; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu572; CHECK-NEXT:    vmv1r.v v20, v0573; CHECK-NEXT:    vmsleu.vv v0, v12, v8574; CHECK-NEXT:    vmsleu.vv v20, v16, v12, v0.t575; CHECK-NEXT:    vmv1r.v v0, v20576; CHECK-NEXT:    ret577entry:578  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(579    <vscale x 8 x i32> %1,580    <vscale x 8 x i32> %2,581    iXLen %4)582  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(583    <vscale x 8 x i1> %0,584    <vscale x 8 x i32> %2,585    <vscale x 8 x i32> %3,586    <vscale x 8 x i1> %mask,587    iXLen %4)588 589  ret <vscale x 8 x i1> %a590}591 592define <vscale x 1 x i1> @intrinsic_vmsgeu_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {593; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv1i64_nxv1i64:594; CHECK:       # %bb.0: # %entry595; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma596; CHECK-NEXT:    vmsleu.vv v0, v9, v8597; CHECK-NEXT:    ret598entry:599  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(600    <vscale x 1 x i64> %0,601    <vscale x 1 x i64> %1,602    iXLen %2)603 604  ret <vscale x 1 x i1> %a605}606 607define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, iXLen %4) nounwind {608; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:609; CHECK:       # %bb.0: # %entry610; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu611; CHECK-NEXT:    vmv1r.v v11, v0612; CHECK-NEXT:    vmsleu.vv v0, v9, v8613; CHECK-NEXT:    vmsleu.vv v11, v10, v9, v0.t614; CHECK-NEXT:    vmv.v.v v0, v11615; CHECK-NEXT:    ret616entry:617  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(618    <vscale x 1 x i64> %1,619    <vscale x 1 x i64> %2,620    iXLen %4)621  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(622    <vscale x 1 x i1> %0,623    <vscale x 1 x i64> %2,624    <vscale x 1 x i64> %3,625    <vscale x 1 x i1> %mask,626    iXLen %4)627 628  ret <vscale x 1 x i1> %a629}630 631define <vscale x 2 x i1> @intrinsic_vmsgeu_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {632; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv2i64_nxv2i64:633; CHECK:       # %bb.0: # %entry634; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma635; CHECK-NEXT:    vmsleu.vv v0, v10, v8636; CHECK-NEXT:    ret637entry:638  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(639    <vscale x 2 x i64> %0,640    <vscale x 2 x i64> %1,641    iXLen %2)642 643  ret <vscale x 2 x i1> %a644}645 646define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, iXLen %4) nounwind {647; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:648; CHECK:       # %bb.0: # %entry649; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu650; CHECK-NEXT:    vmv1r.v v14, v0651; CHECK-NEXT:    vmsleu.vv v0, v10, v8652; CHECK-NEXT:    vmsleu.vv v14, v12, v10, v0.t653; CHECK-NEXT:    vmv1r.v v0, v14654; CHECK-NEXT:    ret655entry:656  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(657    <vscale x 2 x i64> %1,658    <vscale x 2 x i64> %2,659    iXLen %4)660  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(661    <vscale x 2 x i1> %0,662    <vscale x 2 x i64> %2,663    <vscale x 2 x i64> %3,664    <vscale x 2 x i1> %mask,665    iXLen %4)666 667  ret <vscale x 2 x i1> %a668}669 670define <vscale x 4 x i1> @intrinsic_vmsgeu_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vmsgeu_vv_nxv4i64_nxv4i64:672; CHECK:       # %bb.0: # %entry673; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT:    vmsleu.vv v0, v12, v8675; CHECK-NEXT:    ret676entry:677  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(678    <vscale x 4 x i64> %0,679    <vscale x 4 x i64> %1,680    iXLen %2)681 682  ret <vscale x 4 x i1> %a683}684 685define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, iXLen %4) nounwind {686; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:687; CHECK:       # %bb.0: # %entry688; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu689; CHECK-NEXT:    vmv1r.v v20, v0690; CHECK-NEXT:    vmsleu.vv v0, v12, v8691; CHECK-NEXT:    vmsleu.vv v20, v16, v12, v0.t692; CHECK-NEXT:    vmv1r.v v0, v20693; CHECK-NEXT:    ret694entry:695  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(696    <vscale x 4 x i64> %1,697    <vscale x 4 x i64> %2,698    iXLen %4)699  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(700    <vscale x 4 x i1> %0,701    <vscale x 4 x i64> %2,702    <vscale x 4 x i64> %3,703    <vscale x 4 x i1> %mask,704    iXLen %4)705 706  ret <vscale x 4 x i1> %a707}708 709define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {710; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i8_i8:711; CHECK:       # %bb.0: # %entry712; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma713; CHECK-NEXT:    vmsltu.vx v8, v8, a0714; CHECK-NEXT:    vmnot.m v0, v8715; CHECK-NEXT:    ret716entry:717  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(718    <vscale x 1 x i8> %0,719    i8 %1,720    iXLen %2)721 722  ret <vscale x 1 x i1> %a723}724 725define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {726; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:727; CHECK:       # %bb.0: # %entry728; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu729; CHECK-NEXT:    vmv1r.v v10, v0730; CHECK-NEXT:    vmv1r.v v0, v9731; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t732; CHECK-NEXT:    vmxor.mm v0, v10, v9733; CHECK-NEXT:    ret734entry:735  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(736    <vscale x 1 x i1> %0,737    <vscale x 1 x i8> %1,738    i8 %2,739    <vscale x 1 x i1> %3,740    iXLen %4)741 742  ret <vscale x 1 x i1> %a743}744 745define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {746; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i8_i8:747; CHECK:       # %bb.0: # %entry748; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma749; CHECK-NEXT:    vmsltu.vx v8, v8, a0750; CHECK-NEXT:    vmnot.m v0, v8751; CHECK-NEXT:    ret752entry:753  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(754    <vscale x 2 x i8> %0,755    i8 %1,756    iXLen %2)757 758  ret <vscale x 2 x i1> %a759}760 761define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {762; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:763; CHECK:       # %bb.0: # %entry764; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu765; CHECK-NEXT:    vmv1r.v v10, v0766; CHECK-NEXT:    vmv1r.v v0, v9767; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t768; CHECK-NEXT:    vmxor.mm v0, v10, v9769; CHECK-NEXT:    ret770entry:771  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(772    <vscale x 2 x i1> %0,773    <vscale x 2 x i8> %1,774    i8 %2,775    <vscale x 2 x i1> %3,776    iXLen %4)777 778  ret <vscale x 2 x i1> %a779}780 781define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {782; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i8_i8:783; CHECK:       # %bb.0: # %entry784; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma785; CHECK-NEXT:    vmsltu.vx v8, v8, a0786; CHECK-NEXT:    vmnot.m v0, v8787; CHECK-NEXT:    ret788entry:789  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(790    <vscale x 4 x i8> %0,791    i8 %1,792    iXLen %2)793 794  ret <vscale x 4 x i1> %a795}796 797define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {798; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:799; CHECK:       # %bb.0: # %entry800; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu801; CHECK-NEXT:    vmv1r.v v10, v0802; CHECK-NEXT:    vmv1r.v v0, v9803; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t804; CHECK-NEXT:    vmxor.mm v0, v10, v9805; CHECK-NEXT:    ret806entry:807  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(808    <vscale x 4 x i1> %0,809    <vscale x 4 x i8> %1,810    i8 %2,811    <vscale x 4 x i1> %3,812    iXLen %4)813 814  ret <vscale x 4 x i1> %a815}816 817define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {818; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i8_i8:819; CHECK:       # %bb.0: # %entry820; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma821; CHECK-NEXT:    vmsltu.vx v8, v8, a0822; CHECK-NEXT:    vmnot.m v0, v8823; CHECK-NEXT:    ret824entry:825  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(826    <vscale x 8 x i8> %0,827    i8 %1,828    iXLen %2)829 830  ret <vscale x 8 x i1> %a831}832 833define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {834; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:835; CHECK:       # %bb.0: # %entry836; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu837; CHECK-NEXT:    vmv1r.v v10, v0838; CHECK-NEXT:    vmv1r.v v0, v9839; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t840; CHECK-NEXT:    vmxor.mm v0, v10, v9841; CHECK-NEXT:    ret842entry:843  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(844    <vscale x 8 x i1> %0,845    <vscale x 8 x i8> %1,846    i8 %2,847    <vscale x 8 x i1> %3,848    iXLen %4)849 850  ret <vscale x 8 x i1> %a851}852 853define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {854; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i8_i8:855; CHECK:       # %bb.0: # %entry856; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma857; CHECK-NEXT:    vmsltu.vx v10, v8, a0858; CHECK-NEXT:    vmnot.m v0, v10859; CHECK-NEXT:    ret860entry:861  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(862    <vscale x 16 x i8> %0,863    i8 %1,864    iXLen %2)865 866  ret <vscale x 16 x i1> %a867}868 869define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {870; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:871; CHECK:       # %bb.0: # %entry872; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu873; CHECK-NEXT:    vmv1r.v v11, v0874; CHECK-NEXT:    vmv1r.v v0, v10875; CHECK-NEXT:    vmsltu.vx v11, v8, a0, v0.t876; CHECK-NEXT:    vmxor.mm v0, v11, v10877; CHECK-NEXT:    ret878entry:879  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(880    <vscale x 16 x i1> %0,881    <vscale x 16 x i8> %1,882    i8 %2,883    <vscale x 16 x i1> %3,884    iXLen %4)885 886  ret <vscale x 16 x i1> %a887}888 889define <vscale x 32 x i1> @intrinsic_vmsgeu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {890; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv32i8_i8:891; CHECK:       # %bb.0: # %entry892; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma893; CHECK-NEXT:    vmsltu.vx v12, v8, a0894; CHECK-NEXT:    vmnot.m v0, v12895; CHECK-NEXT:    ret896entry:897  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(898    <vscale x 32 x i8> %0,899    i8 %1,900    iXLen %2)901 902  ret <vscale x 32 x i1> %a903}904 905define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {906; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:907; CHECK:       # %bb.0: # %entry908; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu909; CHECK-NEXT:    vmv1r.v v13, v0910; CHECK-NEXT:    vmv1r.v v0, v12911; CHECK-NEXT:    vmsltu.vx v13, v8, a0, v0.t912; CHECK-NEXT:    vmxor.mm v0, v13, v12913; CHECK-NEXT:    ret914entry:915  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(916    <vscale x 32 x i1> %0,917    <vscale x 32 x i8> %1,918    i8 %2,919    <vscale x 32 x i1> %3,920    iXLen %4)921 922  ret <vscale x 32 x i1> %a923}924 925define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {926; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i16_i16:927; CHECK:       # %bb.0: # %entry928; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma929; CHECK-NEXT:    vmsltu.vx v8, v8, a0930; CHECK-NEXT:    vmnot.m v0, v8931; CHECK-NEXT:    ret932entry:933  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(934    <vscale x 1 x i16> %0,935    i16 %1,936    iXLen %2)937 938  ret <vscale x 1 x i1> %a939}940 941define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {942; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:943; CHECK:       # %bb.0: # %entry944; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu945; CHECK-NEXT:    vmv1r.v v10, v0946; CHECK-NEXT:    vmv1r.v v0, v9947; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t948; CHECK-NEXT:    vmxor.mm v0, v10, v9949; CHECK-NEXT:    ret950entry:951  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(952    <vscale x 1 x i1> %0,953    <vscale x 1 x i16> %1,954    i16 %2,955    <vscale x 1 x i1> %3,956    iXLen %4)957 958  ret <vscale x 1 x i1> %a959}960 961define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {962; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i16_i16:963; CHECK:       # %bb.0: # %entry964; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma965; CHECK-NEXT:    vmsltu.vx v8, v8, a0966; CHECK-NEXT:    vmnot.m v0, v8967; CHECK-NEXT:    ret968entry:969  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(970    <vscale x 2 x i16> %0,971    i16 %1,972    iXLen %2)973 974  ret <vscale x 2 x i1> %a975}976 977define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {978; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:979; CHECK:       # %bb.0: # %entry980; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu981; CHECK-NEXT:    vmv1r.v v10, v0982; CHECK-NEXT:    vmv1r.v v0, v9983; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t984; CHECK-NEXT:    vmxor.mm v0, v10, v9985; CHECK-NEXT:    ret986entry:987  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(988    <vscale x 2 x i1> %0,989    <vscale x 2 x i16> %1,990    i16 %2,991    <vscale x 2 x i1> %3,992    iXLen %4)993 994  ret <vscale x 2 x i1> %a995}996 997define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {998; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i16_i16:999; CHECK:       # %bb.0: # %entry1000; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1001; CHECK-NEXT:    vmsltu.vx v8, v8, a01002; CHECK-NEXT:    vmnot.m v0, v81003; CHECK-NEXT:    ret1004entry:1005  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(1006    <vscale x 4 x i16> %0,1007    i16 %1,1008    iXLen %2)1009 1010  ret <vscale x 4 x i1> %a1011}1012 1013define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1014; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:1015; CHECK:       # %bb.0: # %entry1016; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1017; CHECK-NEXT:    vmv1r.v v10, v01018; CHECK-NEXT:    vmv1r.v v0, v91019; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t1020; CHECK-NEXT:    vmxor.mm v0, v10, v91021; CHECK-NEXT:    ret1022entry:1023  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(1024    <vscale x 4 x i1> %0,1025    <vscale x 4 x i16> %1,1026    i16 %2,1027    <vscale x 4 x i1> %3,1028    iXLen %4)1029 1030  ret <vscale x 4 x i1> %a1031}1032 1033define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1034; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i16_i16:1035; CHECK:       # %bb.0: # %entry1036; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1037; CHECK-NEXT:    vmsltu.vx v10, v8, a01038; CHECK-NEXT:    vmnot.m v0, v101039; CHECK-NEXT:    ret1040entry:1041  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(1042    <vscale x 8 x i16> %0,1043    i16 %1,1044    iXLen %2)1045 1046  ret <vscale x 8 x i1> %a1047}1048 1049define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1050; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:1051; CHECK:       # %bb.0: # %entry1052; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1053; CHECK-NEXT:    vmv1r.v v11, v01054; CHECK-NEXT:    vmv1r.v v0, v101055; CHECK-NEXT:    vmsltu.vx v11, v8, a0, v0.t1056; CHECK-NEXT:    vmxor.mm v0, v11, v101057; CHECK-NEXT:    ret1058entry:1059  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(1060    <vscale x 8 x i1> %0,1061    <vscale x 8 x i16> %1,1062    i16 %2,1063    <vscale x 8 x i1> %3,1064    iXLen %4)1065 1066  ret <vscale x 8 x i1> %a1067}1068 1069define <vscale x 16 x i1> @intrinsic_vmsgeu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1070; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv16i16_i16:1071; CHECK:       # %bb.0: # %entry1072; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1073; CHECK-NEXT:    vmsltu.vx v12, v8, a01074; CHECK-NEXT:    vmnot.m v0, v121075; CHECK-NEXT:    ret1076entry:1077  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(1078    <vscale x 16 x i16> %0,1079    i16 %1,1080    iXLen %2)1081 1082  ret <vscale x 16 x i1> %a1083}1084 1085define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1086; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:1087; CHECK:       # %bb.0: # %entry1088; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1089; CHECK-NEXT:    vmv1r.v v13, v01090; CHECK-NEXT:    vmv1r.v v0, v121091; CHECK-NEXT:    vmsltu.vx v13, v8, a0, v0.t1092; CHECK-NEXT:    vmxor.mm v0, v13, v121093; CHECK-NEXT:    ret1094entry:1095  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(1096    <vscale x 16 x i1> %0,1097    <vscale x 16 x i16> %1,1098    i16 %2,1099    <vscale x 16 x i1> %3,1100    iXLen %4)1101 1102  ret <vscale x 16 x i1> %a1103}1104 1105define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1106; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv1i32_i32:1107; CHECK:       # %bb.0: # %entry1108; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1109; CHECK-NEXT:    vmsltu.vx v8, v8, a01110; CHECK-NEXT:    vmnot.m v0, v81111; CHECK-NEXT:    ret1112entry:1113  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(1114    <vscale x 1 x i32> %0,1115    i32 %1,1116    iXLen %2)1117 1118  ret <vscale x 1 x i1> %a1119}1120 1121define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1122; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:1123; CHECK:       # %bb.0: # %entry1124; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1125; CHECK-NEXT:    vmv1r.v v10, v01126; CHECK-NEXT:    vmv1r.v v0, v91127; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t1128; CHECK-NEXT:    vmxor.mm v0, v10, v91129; CHECK-NEXT:    ret1130entry:1131  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(1132    <vscale x 1 x i1> %0,1133    <vscale x 1 x i32> %1,1134    i32 %2,1135    <vscale x 1 x i1> %3,1136    iXLen %4)1137 1138  ret <vscale x 1 x i1> %a1139}1140 1141define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1142; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv2i32_i32:1143; CHECK:       # %bb.0: # %entry1144; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1145; CHECK-NEXT:    vmsltu.vx v8, v8, a01146; CHECK-NEXT:    vmnot.m v0, v81147; CHECK-NEXT:    ret1148entry:1149  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(1150    <vscale x 2 x i32> %0,1151    i32 %1,1152    iXLen %2)1153 1154  ret <vscale x 2 x i1> %a1155}1156 1157define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1158; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:1159; CHECK:       # %bb.0: # %entry1160; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1161; CHECK-NEXT:    vmv1r.v v10, v01162; CHECK-NEXT:    vmv1r.v v0, v91163; CHECK-NEXT:    vmsltu.vx v10, v8, a0, v0.t1164; CHECK-NEXT:    vmxor.mm v0, v10, v91165; CHECK-NEXT:    ret1166entry:1167  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(1168    <vscale x 2 x i1> %0,1169    <vscale x 2 x i32> %1,1170    i32 %2,1171    <vscale x 2 x i1> %3,1172    iXLen %4)1173 1174  ret <vscale x 2 x i1> %a1175}1176 1177define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1178; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv4i32_i32:1179; CHECK:       # %bb.0: # %entry1180; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1181; CHECK-NEXT:    vmsltu.vx v10, v8, a01182; CHECK-NEXT:    vmnot.m v0, v101183; CHECK-NEXT:    ret1184entry:1185  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(1186    <vscale x 4 x i32> %0,1187    i32 %1,1188    iXLen %2)1189 1190  ret <vscale x 4 x i1> %a1191}1192 1193define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1194; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:1195; CHECK:       # %bb.0: # %entry1196; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1197; CHECK-NEXT:    vmv1r.v v11, v01198; CHECK-NEXT:    vmv1r.v v0, v101199; CHECK-NEXT:    vmsltu.vx v11, v8, a0, v0.t1200; CHECK-NEXT:    vmxor.mm v0, v11, v101201; CHECK-NEXT:    ret1202entry:1203  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(1204    <vscale x 4 x i1> %0,1205    <vscale x 4 x i32> %1,1206    i32 %2,1207    <vscale x 4 x i1> %3,1208    iXLen %4)1209 1210  ret <vscale x 4 x i1> %a1211}1212 1213define <vscale x 8 x i1> @intrinsic_vmsgeu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1214; CHECK-LABEL: intrinsic_vmsgeu_vx_nxv8i32_i32:1215; CHECK:       # %bb.0: # %entry1216; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1217; CHECK-NEXT:    vmsltu.vx v12, v8, a01218; CHECK-NEXT:    vmnot.m v0, v121219; CHECK-NEXT:    ret1220entry:1221  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(1222    <vscale x 8 x i32> %0,1223    i32 %1,1224    iXLen %2)1225 1226  ret <vscale x 8 x i1> %a1227}1228 1229define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1230; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:1231; CHECK:       # %bb.0: # %entry1232; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1233; CHECK-NEXT:    vmv1r.v v13, v01234; CHECK-NEXT:    vmv1r.v v0, v121235; CHECK-NEXT:    vmsltu.vx v13, v8, a0, v0.t1236; CHECK-NEXT:    vmxor.mm v0, v13, v121237; CHECK-NEXT:    ret1238entry:1239  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(1240    <vscale x 8 x i1> %0,1241    <vscale x 8 x i32> %1,1242    i32 %2,1243    <vscale x 8 x i1> %3,1244    iXLen %4)1245 1246  ret <vscale x 8 x i1> %a1247}1248 1249define <vscale x 1 x i1> @intrinsic_vmsgeu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1250; RV32-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64:1251; RV32:       # %bb.0: # %entry1252; RV32-NEXT:    addi sp, sp, -161253; RV32-NEXT:    sw a0, 8(sp)1254; RV32-NEXT:    sw a1, 12(sp)1255; RV32-NEXT:    addi a0, sp, 81256; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1257; RV32-NEXT:    vlse64.v v9, (a0), zero1258; RV32-NEXT:    vmsleu.vv v0, v9, v81259; RV32-NEXT:    addi sp, sp, 161260; RV32-NEXT:    ret1261;1262; RV64-LABEL: intrinsic_vmsgeu_vx_nxv1i64_i64:1263; RV64:       # %bb.0: # %entry1264; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1265; RV64-NEXT:    vmsltu.vx v8, v8, a01266; RV64-NEXT:    vmnot.m v0, v81267; RV64-NEXT:    ret1268entry:1269  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(1270    <vscale x 1 x i64> %0,1271    i64 %1,1272    iXLen %2)1273 1274  ret <vscale x 1 x i1> %a1275}1276 1277define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1278; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:1279; RV32:       # %bb.0: # %entry1280; RV32-NEXT:    addi sp, sp, -161281; RV32-NEXT:    sw a0, 8(sp)1282; RV32-NEXT:    sw a1, 12(sp)1283; RV32-NEXT:    addi a0, sp, 81284; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu1285; RV32-NEXT:    vlse64.v v11, (a0), zero1286; RV32-NEXT:    vmv1r.v v10, v01287; RV32-NEXT:    vmv1r.v v0, v91288; RV32-NEXT:    vmsleu.vv v10, v11, v8, v0.t1289; RV32-NEXT:    vmv.v.v v0, v101290; RV32-NEXT:    addi sp, sp, 161291; RV32-NEXT:    ret1292;1293; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:1294; RV64:       # %bb.0: # %entry1295; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1296; RV64-NEXT:    vmv1r.v v10, v01297; RV64-NEXT:    vmv1r.v v0, v91298; RV64-NEXT:    vmsltu.vx v10, v8, a0, v0.t1299; RV64-NEXT:    vmxor.mm v0, v10, v91300; RV64-NEXT:    ret1301entry:1302  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(1303    <vscale x 1 x i1> %0,1304    <vscale x 1 x i64> %1,1305    i64 %2,1306    <vscale x 1 x i1> %3,1307    iXLen %4)1308 1309  ret <vscale x 1 x i1> %a1310}1311 1312define <vscale x 2 x i1> @intrinsic_vmsgeu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1313; RV32-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64:1314; RV32:       # %bb.0: # %entry1315; RV32-NEXT:    addi sp, sp, -161316; RV32-NEXT:    sw a0, 8(sp)1317; RV32-NEXT:    sw a1, 12(sp)1318; RV32-NEXT:    addi a0, sp, 81319; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1320; RV32-NEXT:    vlse64.v v10, (a0), zero1321; RV32-NEXT:    vmsleu.vv v0, v10, v81322; RV32-NEXT:    addi sp, sp, 161323; RV32-NEXT:    ret1324;1325; RV64-LABEL: intrinsic_vmsgeu_vx_nxv2i64_i64:1326; RV64:       # %bb.0: # %entry1327; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1328; RV64-NEXT:    vmsltu.vx v10, v8, a01329; RV64-NEXT:    vmnot.m v0, v101330; RV64-NEXT:    ret1331entry:1332  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(1333    <vscale x 2 x i64> %0,1334    i64 %1,1335    iXLen %2)1336 1337  ret <vscale x 2 x i1> %a1338}1339 1340define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1341; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:1342; RV32:       # %bb.0: # %entry1343; RV32-NEXT:    addi sp, sp, -161344; RV32-NEXT:    sw a0, 8(sp)1345; RV32-NEXT:    sw a1, 12(sp)1346; RV32-NEXT:    addi a0, sp, 81347; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu1348; RV32-NEXT:    vlse64.v v12, (a0), zero1349; RV32-NEXT:    vmv1r.v v11, v01350; RV32-NEXT:    vmv1r.v v0, v101351; RV32-NEXT:    vmsleu.vv v11, v12, v8, v0.t1352; RV32-NEXT:    vmv1r.v v0, v111353; RV32-NEXT:    addi sp, sp, 161354; RV32-NEXT:    ret1355;1356; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:1357; RV64:       # %bb.0: # %entry1358; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1359; RV64-NEXT:    vmv1r.v v11, v01360; RV64-NEXT:    vmv1r.v v0, v101361; RV64-NEXT:    vmsltu.vx v11, v8, a0, v0.t1362; RV64-NEXT:    vmxor.mm v0, v11, v101363; RV64-NEXT:    ret1364entry:1365  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(1366    <vscale x 2 x i1> %0,1367    <vscale x 2 x i64> %1,1368    i64 %2,1369    <vscale x 2 x i1> %3,1370    iXLen %4)1371 1372  ret <vscale x 2 x i1> %a1373}1374 1375define <vscale x 4 x i1> @intrinsic_vmsgeu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1376; RV32-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64:1377; RV32:       # %bb.0: # %entry1378; RV32-NEXT:    addi sp, sp, -161379; RV32-NEXT:    sw a0, 8(sp)1380; RV32-NEXT:    sw a1, 12(sp)1381; RV32-NEXT:    addi a0, sp, 81382; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1383; RV32-NEXT:    vlse64.v v12, (a0), zero1384; RV32-NEXT:    vmsleu.vv v0, v12, v81385; RV32-NEXT:    addi sp, sp, 161386; RV32-NEXT:    ret1387;1388; RV64-LABEL: intrinsic_vmsgeu_vx_nxv4i64_i64:1389; RV64:       # %bb.0: # %entry1390; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1391; RV64-NEXT:    vmsltu.vx v12, v8, a01392; RV64-NEXT:    vmnot.m v0, v121393; RV64-NEXT:    ret1394entry:1395  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(1396    <vscale x 4 x i64> %0,1397    i64 %1,1398    iXLen %2)1399 1400  ret <vscale x 4 x i1> %a1401}1402 1403define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1404; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:1405; RV32:       # %bb.0: # %entry1406; RV32-NEXT:    addi sp, sp, -161407; RV32-NEXT:    sw a0, 8(sp)1408; RV32-NEXT:    sw a1, 12(sp)1409; RV32-NEXT:    addi a0, sp, 81410; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu1411; RV32-NEXT:    vlse64.v v16, (a0), zero1412; RV32-NEXT:    vmv1r.v v13, v01413; RV32-NEXT:    vmv1r.v v0, v121414; RV32-NEXT:    vmsleu.vv v13, v16, v8, v0.t1415; RV32-NEXT:    vmv1r.v v0, v131416; RV32-NEXT:    addi sp, sp, 161417; RV32-NEXT:    ret1418;1419; RV64-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:1420; RV64:       # %bb.0: # %entry1421; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1422; RV64-NEXT:    vmv1r.v v13, v01423; RV64-NEXT:    vmv1r.v v0, v121424; RV64-NEXT:    vmsltu.vx v13, v8, a0, v0.t1425; RV64-NEXT:    vmxor.mm v0, v13, v121426; RV64-NEXT:    ret1427entry:1428  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(1429    <vscale x 4 x i1> %0,1430    <vscale x 4 x i64> %1,1431    i64 %2,1432    <vscale x 4 x i1> %3,1433    iXLen %4)1434 1435  ret <vscale x 4 x i1> %a1436}1437 1438define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1439; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8:1440; CHECK:       # %bb.0: # %entry1441; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1442; CHECK-NEXT:    vmsgtu.vi v0, v8, -161443; CHECK-NEXT:    ret1444entry:1445  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(1446    <vscale x 1 x i8> %0,1447    i8 -15,1448    iXLen %1)1449 1450  ret <vscale x 1 x i1> %a1451}1452 1453define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1454; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i8_i8:1455; CHECK:       # %bb.0: # %entry1456; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu1457; CHECK-NEXT:    vmv1r.v v10, v01458; CHECK-NEXT:    vmv1r.v v0, v91459; CHECK-NEXT:    vmsgtu.vi v10, v8, -15, v0.t1460; CHECK-NEXT:    vmv1r.v v0, v101461; CHECK-NEXT:    ret1462entry:1463  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(1464    <vscale x 1 x i1> %0,1465    <vscale x 1 x i8> %1,1466    i8 -14,1467    <vscale x 1 x i1> %2,1468    iXLen %3)1469 1470  ret <vscale x 1 x i1> %a1471}1472 1473define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1474; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8:1475; CHECK:       # %bb.0: # %entry1476; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1477; CHECK-NEXT:    vmsgtu.vi v0, v8, -141478; CHECK-NEXT:    ret1479entry:1480  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(1481    <vscale x 2 x i8> %0,1482    i8 -13,1483    iXLen %1)1484 1485  ret <vscale x 2 x i1> %a1486}1487 1488define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1489; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i8_i8:1490; CHECK:       # %bb.0: # %entry1491; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu1492; CHECK-NEXT:    vmv1r.v v10, v01493; CHECK-NEXT:    vmv1r.v v0, v91494; CHECK-NEXT:    vmsgtu.vi v10, v8, -13, v0.t1495; CHECK-NEXT:    vmv1r.v v0, v101496; CHECK-NEXT:    ret1497entry:1498  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(1499    <vscale x 2 x i1> %0,1500    <vscale x 2 x i8> %1,1501    i8 -12,1502    <vscale x 2 x i1> %2,1503    iXLen %3)1504 1505  ret <vscale x 2 x i1> %a1506}1507 1508define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1509; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8:1510; CHECK:       # %bb.0: # %entry1511; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1512; CHECK-NEXT:    vmsgtu.vi v0, v8, -121513; CHECK-NEXT:    ret1514entry:1515  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(1516    <vscale x 4 x i8> %0,1517    i8 -11,1518    iXLen %1)1519 1520  ret <vscale x 4 x i1> %a1521}1522 1523define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1524; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8:1525; CHECK:       # %bb.0: # %entry1526; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu1527; CHECK-NEXT:    vmv1r.v v10, v01528; CHECK-NEXT:    vmv1r.v v0, v91529; CHECK-NEXT:    vmsgtu.vi v10, v8, -11, v0.t1530; CHECK-NEXT:    vmv1r.v v0, v101531; CHECK-NEXT:    ret1532entry:1533  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(1534    <vscale x 4 x i1> %0,1535    <vscale x 4 x i8> %1,1536    i8 -10,1537    <vscale x 4 x i1> %2,1538    iXLen %3)1539 1540  ret <vscale x 4 x i1> %a1541}1542 1543define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8_1(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1544; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i8_i8_1:1545; CHECK:       # %bb.0: # %entry1546; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu1547; CHECK-NEXT:    vmv1r.v v10, v01548; CHECK-NEXT:    li a0, 991549; CHECK-NEXT:    vmv1r.v v0, v91550; CHECK-NEXT:    vmsgtu.vx v10, v8, a0, v0.t1551; CHECK-NEXT:    vmv1r.v v0, v101552; CHECK-NEXT:    ret1553entry:1554  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(1555    <vscale x 4 x i1> %0,1556    <vscale x 4 x i8> %1,1557    i8 100,1558    <vscale x 4 x i1> %2,1559    iXLen %3)1560 1561  ret <vscale x 4 x i1> %a1562}1563 1564define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1565; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8:1566; CHECK:       # %bb.0: # %entry1567; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1568; CHECK-NEXT:    vmsgtu.vi v0, v8, -101569; CHECK-NEXT:    ret1570entry:1571  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(1572    <vscale x 8 x i8> %0,1573    i8 -9,1574    iXLen %1)1575 1576  ret <vscale x 8 x i1> %a1577}1578 1579define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1580; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i8_i8:1581; CHECK:       # %bb.0: # %entry1582; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu1583; CHECK-NEXT:    vmv1r.v v10, v01584; CHECK-NEXT:    vmv1r.v v0, v91585; CHECK-NEXT:    vmsgtu.vi v10, v8, -9, v0.t1586; CHECK-NEXT:    vmv.v.v v0, v101587; CHECK-NEXT:    ret1588entry:1589  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(1590    <vscale x 8 x i1> %0,1591    <vscale x 8 x i8> %1,1592    i8 -8,1593    <vscale x 8 x i1> %2,1594    iXLen %3)1595 1596  ret <vscale x 8 x i1> %a1597}1598 1599define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1600; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8:1601; CHECK:       # %bb.0: # %entry1602; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1603; CHECK-NEXT:    vmsgtu.vi v0, v8, -81604; CHECK-NEXT:    ret1605entry:1606  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(1607    <vscale x 16 x i8> %0,1608    i8 -7,1609    iXLen %1)1610 1611  ret <vscale x 16 x i1> %a1612}1613 1614define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1615; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i8_i8:1616; CHECK:       # %bb.0: # %entry1617; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu1618; CHECK-NEXT:    vmv1r.v v11, v01619; CHECK-NEXT:    vmv1r.v v0, v101620; CHECK-NEXT:    vmsgtu.vi v11, v8, -7, v0.t1621; CHECK-NEXT:    vmv1r.v v0, v111622; CHECK-NEXT:    ret1623entry:1624  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(1625    <vscale x 16 x i1> %0,1626    <vscale x 16 x i8> %1,1627    i8 -6,1628    <vscale x 16 x i1> %2,1629    iXLen %3)1630 1631  ret <vscale x 16 x i1> %a1632}1633 1634define <vscale x 32 x i1> @intrinsic_vmsgeu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1635; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8:1636; CHECK:       # %bb.0: # %entry1637; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1638; CHECK-NEXT:    vmsgtu.vi v0, v8, -61639; CHECK-NEXT:    ret1640entry:1641  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(1642    <vscale x 32 x i8> %0,1643    i8 -5,1644    iXLen %1)1645 1646  ret <vscale x 32 x i1> %a1647}1648 1649define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1650; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv32i8_i8:1651; CHECK:       # %bb.0: # %entry1652; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu1653; CHECK-NEXT:    vmv1r.v v13, v01654; CHECK-NEXT:    vmv1r.v v0, v121655; CHECK-NEXT:    vmsgtu.vi v13, v8, -5, v0.t1656; CHECK-NEXT:    vmv1r.v v0, v131657; CHECK-NEXT:    ret1658entry:1659  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(1660    <vscale x 32 x i1> %0,1661    <vscale x 32 x i8> %1,1662    i8 -4,1663    <vscale x 32 x i1> %2,1664    iXLen %3)1665 1666  ret <vscale x 32 x i1> %a1667}1668 1669define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1670; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16:1671; CHECK:       # %bb.0: # %entry1672; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1673; CHECK-NEXT:    vmsgtu.vi v0, v8, -41674; CHECK-NEXT:    ret1675entry:1676  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(1677    <vscale x 1 x i16> %0,1678    i16 -3,1679    iXLen %1)1680 1681  ret <vscale x 1 x i1> %a1682}1683 1684define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1685; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i16_i16:1686; CHECK:       # %bb.0: # %entry1687; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu1688; CHECK-NEXT:    vmv1r.v v10, v01689; CHECK-NEXT:    vmv1r.v v0, v91690; CHECK-NEXT:    vmsgtu.vi v10, v8, -3, v0.t1691; CHECK-NEXT:    vmv1r.v v0, v101692; CHECK-NEXT:    ret1693entry:1694  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(1695    <vscale x 1 x i1> %0,1696    <vscale x 1 x i16> %1,1697    i16 -2,1698    <vscale x 1 x i1> %2,1699    iXLen %3)1700 1701  ret <vscale x 1 x i1> %a1702}1703 1704define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1705; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16:1706; CHECK:       # %bb.0: # %entry1707; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1708; CHECK-NEXT:    vmsgtu.vi v0, v8, -21709; CHECK-NEXT:    ret1710entry:1711  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(1712    <vscale x 2 x i16> %0,1713    i16 -1,1714    iXLen %1)1715 1716  ret <vscale x 2 x i1> %a1717}1718 1719define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1720; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:1721; CHECK:       # %bb.0: # %entry1722; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1723; CHECK-NEXT:    vmor.mm v0, v9, v01724; CHECK-NEXT:    ret1725entry:1726  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(1727    <vscale x 2 x i1> %0,1728    <vscale x 2 x i16> %1,1729    i16 0,1730    <vscale x 2 x i1> %2,1731    iXLen %3)1732 1733  ret <vscale x 2 x i1> %a1734}1735 1736define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1737; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff:1738; CHECK:       # %bb.0: # %entry1739; CHECK-NEXT:    ret1740entry:1741  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(1742    <vscale x 2 x i1> %0,1743    <vscale x 2 x i16> %1,1744    i16 0,1745    <vscale x 2 x i1> %0,1746    iXLen %2)1747 1748  ret <vscale x 2 x i1> %a1749}1750 1751define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1752; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:1753; CHECK:       # %bb.0: # %entry1754; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1755; CHECK-NEXT:    vmset.m v01756; CHECK-NEXT:    ret1757entry:1758  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(1759    <vscale x 4 x i16> %0,1760    i16 0,1761    iXLen %1)1762 1763  ret <vscale x 4 x i1> %a1764}1765 1766define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16_1(<vscale x 4 x i16> %0, iXLen %1) nounwind {1767; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16_1:1768; CHECK:       # %bb.0: # %entry1769; CHECK-NEXT:    li a1, 991770; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1771; CHECK-NEXT:    vmsgtu.vx v0, v8, a11772; CHECK-NEXT:    ret1773entry:1774  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(1775    <vscale x 4 x i16> %0,1776    i16 100,1777    iXLen %1)1778 1779  ret <vscale x 4 x i1> %a1780}1781 1782define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1783; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:1784; CHECK:       # %bb.0: # %entry1785; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu1786; CHECK-NEXT:    vmv1r.v v10, v01787; CHECK-NEXT:    vmv1r.v v0, v91788; CHECK-NEXT:    vmsgtu.vi v10, v8, 0, v0.t1789; CHECK-NEXT:    vmv.v.v v0, v101790; CHECK-NEXT:    ret1791entry:1792  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(1793    <vscale x 4 x i1> %0,1794    <vscale x 4 x i16> %1,1795    i16 1,1796    <vscale x 4 x i1> %2,1797    iXLen %3)1798 1799  ret <vscale x 4 x i1> %a1800}1801 1802define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1803; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16:1804; CHECK:       # %bb.0: # %entry1805; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1806; CHECK-NEXT:    vmsgtu.vi v0, v8, 11807; CHECK-NEXT:    ret1808entry:1809  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(1810    <vscale x 8 x i16> %0,1811    i16 2,1812    iXLen %1)1813 1814  ret <vscale x 8 x i1> %a1815}1816 1817define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1818; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i16_i16:1819; CHECK:       # %bb.0: # %entry1820; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu1821; CHECK-NEXT:    vmv1r.v v11, v01822; CHECK-NEXT:    vmv1r.v v0, v101823; CHECK-NEXT:    vmsgtu.vi v11, v8, 2, v0.t1824; CHECK-NEXT:    vmv1r.v v0, v111825; CHECK-NEXT:    ret1826entry:1827  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(1828    <vscale x 8 x i1> %0,1829    <vscale x 8 x i16> %1,1830    i16 3,1831    <vscale x 8 x i1> %2,1832    iXLen %3)1833 1834  ret <vscale x 8 x i1> %a1835}1836 1837define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1838; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16:1839; CHECK:       # %bb.0: # %entry1840; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1841; CHECK-NEXT:    vmsgtu.vi v0, v8, 31842; CHECK-NEXT:    ret1843entry:1844  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(1845    <vscale x 16 x i16> %0,1846    i16 4,1847    iXLen %1)1848 1849  ret <vscale x 16 x i1> %a1850}1851 1852define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1853; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv16i16_i16:1854; CHECK:       # %bb.0: # %entry1855; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu1856; CHECK-NEXT:    vmv1r.v v13, v01857; CHECK-NEXT:    vmv1r.v v0, v121858; CHECK-NEXT:    vmsgtu.vi v13, v8, 4, v0.t1859; CHECK-NEXT:    vmv1r.v v0, v131860; CHECK-NEXT:    ret1861entry:1862  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(1863    <vscale x 16 x i1> %0,1864    <vscale x 16 x i16> %1,1865    i16 5,1866    <vscale x 16 x i1> %2,1867    iXLen %3)1868 1869  ret <vscale x 16 x i1> %a1870}1871 1872define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {1873; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32:1874; CHECK:       # %bb.0: # %entry1875; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1876; CHECK-NEXT:    vmsgtu.vi v0, v8, 51877; CHECK-NEXT:    ret1878entry:1879  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(1880    <vscale x 1 x i32> %0,1881    i32 6,1882    iXLen %1)1883 1884  ret <vscale x 1 x i1> %a1885}1886 1887define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1888; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i32_i32:1889; CHECK:       # %bb.0: # %entry1890; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu1891; CHECK-NEXT:    vmv1r.v v10, v01892; CHECK-NEXT:    vmv1r.v v0, v91893; CHECK-NEXT:    vmsgtu.vi v10, v8, 6, v0.t1894; CHECK-NEXT:    vmv1r.v v0, v101895; CHECK-NEXT:    ret1896entry:1897  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(1898    <vscale x 1 x i1> %0,1899    <vscale x 1 x i32> %1,1900    i32 7,1901    <vscale x 1 x i1> %2,1902    iXLen %3)1903 1904  ret <vscale x 1 x i1> %a1905}1906 1907define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {1908; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32:1909; CHECK:       # %bb.0: # %entry1910; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1911; CHECK-NEXT:    vmsgtu.vi v0, v8, 71912; CHECK-NEXT:    ret1913entry:1914  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(1915    <vscale x 2 x i32> %0,1916    i32 8,1917    iXLen %1)1918 1919  ret <vscale x 2 x i1> %a1920}1921 1922define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1923; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i32_i32:1924; CHECK:       # %bb.0: # %entry1925; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu1926; CHECK-NEXT:    vmv1r.v v10, v01927; CHECK-NEXT:    vmv1r.v v0, v91928; CHECK-NEXT:    vmsgtu.vi v10, v8, 8, v0.t1929; CHECK-NEXT:    vmv.v.v v0, v101930; CHECK-NEXT:    ret1931entry:1932  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(1933    <vscale x 2 x i1> %0,1934    <vscale x 2 x i32> %1,1935    i32 9,1936    <vscale x 2 x i1> %2,1937    iXLen %3)1938 1939  ret <vscale x 2 x i1> %a1940}1941 1942define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {1943; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32:1944; CHECK:       # %bb.0: # %entry1945; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1946; CHECK-NEXT:    vmsgtu.vi v0, v8, 91947; CHECK-NEXT:    ret1948entry:1949  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(1950    <vscale x 4 x i32> %0,1951    i32 10,1952    iXLen %1)1953 1954  ret <vscale x 4 x i1> %a1955}1956 1957define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1958; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i32_i32:1959; CHECK:       # %bb.0: # %entry1960; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu1961; CHECK-NEXT:    vmv1r.v v11, v01962; CHECK-NEXT:    vmv1r.v v0, v101963; CHECK-NEXT:    vmsgtu.vi v11, v8, 10, v0.t1964; CHECK-NEXT:    vmv1r.v v0, v111965; CHECK-NEXT:    ret1966entry:1967  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(1968    <vscale x 4 x i1> %0,1969    <vscale x 4 x i32> %1,1970    i32 11,1971    <vscale x 4 x i1> %2,1972    iXLen %3)1973 1974  ret <vscale x 4 x i1> %a1975}1976 1977define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {1978; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32:1979; CHECK:       # %bb.0: # %entry1980; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1981; CHECK-NEXT:    vmsgtu.vi v0, v8, 111982; CHECK-NEXT:    ret1983entry:1984  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(1985    <vscale x 8 x i32> %0,1986    i32 12,1987    iXLen %1)1988 1989  ret <vscale x 8 x i1> %a1990}1991 1992define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1993; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv8i32_i32:1994; CHECK:       # %bb.0: # %entry1995; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu1996; CHECK-NEXT:    vmv1r.v v13, v01997; CHECK-NEXT:    vmv1r.v v0, v121998; CHECK-NEXT:    vmsgtu.vi v13, v8, 12, v0.t1999; CHECK-NEXT:    vmv1r.v v0, v132000; CHECK-NEXT:    ret2001entry:2002  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(2003    <vscale x 8 x i1> %0,2004    <vscale x 8 x i32> %1,2005    i32 13,2006    <vscale x 8 x i1> %2,2007    iXLen %3)2008 2009  ret <vscale x 8 x i1> %a2010}2011 2012define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {2013; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64:2014; CHECK:       # %bb.0: # %entry2015; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2016; CHECK-NEXT:    vmsgtu.vi v0, v8, 132017; CHECK-NEXT:    ret2018entry:2019  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(2020    <vscale x 1 x i64> %0,2021    i64 14,2022    iXLen %1)2023 2024  ret <vscale x 1 x i1> %a2025}2026 2027define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2028; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv1i64_i64:2029; CHECK:       # %bb.0: # %entry2030; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu2031; CHECK-NEXT:    vmv1r.v v10, v02032; CHECK-NEXT:    vmv1r.v v0, v92033; CHECK-NEXT:    vmsgtu.vi v10, v8, 14, v0.t2034; CHECK-NEXT:    vmv.v.v v0, v102035; CHECK-NEXT:    ret2036entry:2037  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(2038    <vscale x 1 x i1> %0,2039    <vscale x 1 x i64> %1,2040    i64 15,2041    <vscale x 1 x i1> %2,2042    iXLen %3)2043 2044  ret <vscale x 1 x i1> %a2045}2046 2047define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {2048; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64:2049; CHECK:       # %bb.0: # %entry2050; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2051; CHECK-NEXT:    vmsgtu.vi v0, v8, 152052; CHECK-NEXT:    ret2053entry:2054  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(2055    <vscale x 2 x i64> %0,2056    i64 16,2057    iXLen %1)2058 2059  ret <vscale x 2 x i1> %a2060}2061 2062define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2063; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i64_i64:2064; CHECK:       # %bb.0: # %entry2065; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu2066; CHECK-NEXT:    vmv1r.v v11, v02067; CHECK-NEXT:    vmv1r.v v0, v102068; CHECK-NEXT:    vmsgtu.vi v11, v8, -16, v0.t2069; CHECK-NEXT:    vmv1r.v v0, v112070; CHECK-NEXT:    ret2071entry:2072  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(2073    <vscale x 2 x i1> %0,2074    <vscale x 2 x i64> %1,2075    i64 -15,2076    <vscale x 2 x i1> %2,2077    iXLen %3)2078 2079  ret <vscale x 2 x i1> %a2080}2081 2082define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2083; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64:2084; CHECK:       # %bb.0: # %entry2085; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2086; CHECK-NEXT:    vmsgtu.vi v0, v8, -152087; CHECK-NEXT:    ret2088entry:2089  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(2090    <vscale x 4 x i64> %0,2091    i64 -14,2092    iXLen %1)2093 2094  ret <vscale x 4 x i1> %a2095}2096 2097define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2098; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i64_i64:2099; CHECK:       # %bb.0: # %entry2100; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu2101; CHECK-NEXT:    vmv1r.v v13, v02102; CHECK-NEXT:    vmv1r.v v0, v122103; CHECK-NEXT:    vmsgtu.vi v13, v8, -14, v0.t2104; CHECK-NEXT:    vmv1r.v v0, v132105; CHECK-NEXT:    ret2106entry:2107  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(2108    <vscale x 4 x i1> %0,2109    <vscale x 4 x i64> %1,2110    i64 -13,2111    <vscale x 4 x i1> %2,2112    iXLen %3)2113 2114  ret <vscale x 4 x i1> %a2115}2116 2117; Test cases where the mask and maskedoff are the same value.2118define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, iXLen %3) nounwind {2119; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8:2120; CHECK:       # %bb.0: # %entry2121; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma2122; CHECK-NEXT:    vmsltu.vx v8, v8, a02123; CHECK-NEXT:    vmandn.mm v0, v0, v82124; CHECK-NEXT:    ret2125entry:2126  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(2127    <vscale x 1 x i1> %0,2128    <vscale x 1 x i8> %1,2129    i8 %2,2130    <vscale x 1 x i1> %0,2131    iXLen %3)2132 2133  ret <vscale x 1 x i1> %a2134}2135 2136define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, iXLen %3) nounwind {2137; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8:2138; CHECK:       # %bb.0: # %entry2139; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma2140; CHECK-NEXT:    vmsltu.vx v8, v8, a02141; CHECK-NEXT:    vmandn.mm v0, v0, v82142; CHECK-NEXT:    ret2143entry:2144  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(2145    <vscale x 2 x i1> %0,2146    <vscale x 2 x i8> %1,2147    i8 %2,2148    <vscale x 2 x i1> %0,2149    iXLen %3)2150 2151  ret <vscale x 2 x i1> %a2152}2153 2154define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, iXLen %3) nounwind {2155; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8:2156; CHECK:       # %bb.0: # %entry2157; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma2158; CHECK-NEXT:    vmsltu.vx v8, v8, a02159; CHECK-NEXT:    vmandn.mm v0, v0, v82160; CHECK-NEXT:    ret2161entry:2162  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(2163    <vscale x 4 x i1> %0,2164    <vscale x 4 x i8> %1,2165    i8 %2,2166    <vscale x 4 x i1> %0,2167    iXLen %3)2168 2169  ret <vscale x 4 x i1> %a2170}2171 2172define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, iXLen %3) nounwind {2173; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8:2174; CHECK:       # %bb.0: # %entry2175; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma2176; CHECK-NEXT:    vmsltu.vx v8, v8, a02177; CHECK-NEXT:    vmandn.mm v0, v0, v82178; CHECK-NEXT:    ret2179entry:2180  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(2181    <vscale x 8 x i1> %0,2182    <vscale x 8 x i8> %1,2183    i8 %2,2184    <vscale x 8 x i1> %0,2185    iXLen %3)2186 2187  ret <vscale x 8 x i1> %a2188}2189 2190define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, iXLen %3) nounwind {2191; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8:2192; CHECK:       # %bb.0: # %entry2193; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma2194; CHECK-NEXT:    vmsltu.vx v10, v8, a02195; CHECK-NEXT:    vmandn.mm v0, v0, v102196; CHECK-NEXT:    ret2197entry:2198  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(2199    <vscale x 16 x i1> %0,2200    <vscale x 16 x i8> %1,2201    i8 %2,2202    <vscale x 16 x i1> %0,2203    iXLen %3)2204 2205  ret <vscale x 16 x i1> %a2206}2207 2208define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, iXLen %3) nounwind {2209; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8:2210; CHECK:       # %bb.0: # %entry2211; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma2212; CHECK-NEXT:    vmsltu.vx v12, v8, a02213; CHECK-NEXT:    vmandn.mm v0, v0, v122214; CHECK-NEXT:    ret2215entry:2216  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(2217    <vscale x 32 x i1> %0,2218    <vscale x 32 x i8> %1,2219    i8 %2,2220    <vscale x 32 x i1> %0,2221    iXLen %3)2222 2223  ret <vscale x 32 x i1> %a2224}2225 2226define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, iXLen %3) nounwind {2227; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16:2228; CHECK:       # %bb.0: # %entry2229; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2230; CHECK-NEXT:    vmsltu.vx v8, v8, a02231; CHECK-NEXT:    vmandn.mm v0, v0, v82232; CHECK-NEXT:    ret2233entry:2234  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(2235    <vscale x 1 x i1> %0,2236    <vscale x 1 x i16> %1,2237    i16 %2,2238    <vscale x 1 x i1> %0,2239    iXLen %3)2240 2241  ret <vscale x 1 x i1> %a2242}2243 2244define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, iXLen %3) nounwind {2245; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16:2246; CHECK:       # %bb.0: # %entry2247; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2248; CHECK-NEXT:    vmsltu.vx v8, v8, a02249; CHECK-NEXT:    vmandn.mm v0, v0, v82250; CHECK-NEXT:    ret2251entry:2252  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(2253    <vscale x 2 x i1> %0,2254    <vscale x 2 x i16> %1,2255    i16 %2,2256    <vscale x 2 x i1> %0,2257    iXLen %3)2258 2259  ret <vscale x 2 x i1> %a2260}2261 2262define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, iXLen %3) nounwind {2263; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16:2264; CHECK:       # %bb.0: # %entry2265; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2266; CHECK-NEXT:    vmsltu.vx v8, v8, a02267; CHECK-NEXT:    vmandn.mm v0, v0, v82268; CHECK-NEXT:    ret2269entry:2270  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(2271    <vscale x 4 x i1> %0,2272    <vscale x 4 x i16> %1,2273    i16 %2,2274    <vscale x 4 x i1> %0,2275    iXLen %3)2276 2277  ret <vscale x 4 x i1> %a2278}2279 2280define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, iXLen %3) nounwind {2281; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16:2282; CHECK:       # %bb.0: # %entry2283; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2284; CHECK-NEXT:    vmsltu.vx v10, v8, a02285; CHECK-NEXT:    vmandn.mm v0, v0, v102286; CHECK-NEXT:    ret2287entry:2288  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(2289    <vscale x 8 x i1> %0,2290    <vscale x 8 x i16> %1,2291    i16 %2,2292    <vscale x 8 x i1> %0,2293    iXLen %3)2294 2295  ret <vscale x 8 x i1> %a2296}2297 2298define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, iXLen %3) nounwind {2299; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16:2300; CHECK:       # %bb.0: # %entry2301; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2302; CHECK-NEXT:    vmsltu.vx v12, v8, a02303; CHECK-NEXT:    vmandn.mm v0, v0, v122304; CHECK-NEXT:    ret2305entry:2306  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(2307    <vscale x 16 x i1> %0,2308    <vscale x 16 x i16> %1,2309    i16 %2,2310    <vscale x 16 x i1> %0,2311    iXLen %3)2312 2313  ret <vscale x 16 x i1> %a2314}2315 2316define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, iXLen %3) nounwind {2317; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32:2318; CHECK:       # %bb.0: # %entry2319; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2320; CHECK-NEXT:    vmsltu.vx v8, v8, a02321; CHECK-NEXT:    vmandn.mm v0, v0, v82322; CHECK-NEXT:    ret2323entry:2324  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(2325    <vscale x 1 x i1> %0,2326    <vscale x 1 x i32> %1,2327    i32 %2,2328    <vscale x 1 x i1> %0,2329    iXLen %3)2330 2331  ret <vscale x 1 x i1> %a2332}2333 2334define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, iXLen %3) nounwind {2335; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32:2336; CHECK:       # %bb.0: # %entry2337; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2338; CHECK-NEXT:    vmsltu.vx v8, v8, a02339; CHECK-NEXT:    vmandn.mm v0, v0, v82340; CHECK-NEXT:    ret2341entry:2342  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(2343    <vscale x 2 x i1> %0,2344    <vscale x 2 x i32> %1,2345    i32 %2,2346    <vscale x 2 x i1> %0,2347    iXLen %3)2348 2349  ret <vscale x 2 x i1> %a2350}2351 2352define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, iXLen %3) nounwind {2353; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32:2354; CHECK:       # %bb.0: # %entry2355; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2356; CHECK-NEXT:    vmsltu.vx v10, v8, a02357; CHECK-NEXT:    vmandn.mm v0, v0, v102358; CHECK-NEXT:    ret2359entry:2360  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(2361    <vscale x 4 x i1> %0,2362    <vscale x 4 x i32> %1,2363    i32 %2,2364    <vscale x 4 x i1> %0,2365    iXLen %3)2366 2367  ret <vscale x 4 x i1> %a2368}2369 2370define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, iXLen %3) nounwind {2371; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32:2372; CHECK:       # %bb.0: # %entry2373; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2374; CHECK-NEXT:    vmsltu.vx v12, v8, a02375; CHECK-NEXT:    vmandn.mm v0, v0, v122376; CHECK-NEXT:    ret2377entry:2378  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(2379    <vscale x 8 x i1> %0,2380    <vscale x 8 x i32> %1,2381    i32 %2,2382    <vscale x 8 x i1> %0,2383    iXLen %3)2384 2385  ret <vscale x 8 x i1> %a2386}2387 2388define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {2389; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:2390; RV32:       # %bb.0: # %entry2391; RV32-NEXT:    addi sp, sp, -162392; RV32-NEXT:    sw a0, 8(sp)2393; RV32-NEXT:    sw a1, 12(sp)2394; RV32-NEXT:    addi a0, sp, 82395; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu2396; RV32-NEXT:    vlse64.v v9, (a0), zero2397; RV32-NEXT:    vmsleu.vv v0, v9, v8, v0.t2398; RV32-NEXT:    addi sp, sp, 162399; RV32-NEXT:    ret2400;2401; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:2402; RV64:       # %bb.0: # %entry2403; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2404; RV64-NEXT:    vmsltu.vx v8, v8, a02405; RV64-NEXT:    vmandn.mm v0, v0, v82406; RV64-NEXT:    ret2407entry:2408  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(2409    <vscale x 1 x i1> %0,2410    <vscale x 1 x i64> %1,2411    i64 %2,2412    <vscale x 1 x i1> %0,2413    iXLen %3)2414 2415  ret <vscale x 1 x i1> %a2416}2417 2418define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, iXLen %3) nounwind {2419; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:2420; RV32:       # %bb.0: # %entry2421; RV32-NEXT:    addi sp, sp, -162422; RV32-NEXT:    sw a0, 8(sp)2423; RV32-NEXT:    sw a1, 12(sp)2424; RV32-NEXT:    addi a0, sp, 82425; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu2426; RV32-NEXT:    vlse64.v v12, (a0), zero2427; RV32-NEXT:    vmv1r.v v10, v02428; RV32-NEXT:    vmsleu.vv v10, v12, v8, v0.t2429; RV32-NEXT:    vmv1r.v v0, v102430; RV32-NEXT:    addi sp, sp, 162431; RV32-NEXT:    ret2432;2433; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:2434; RV64:       # %bb.0: # %entry2435; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2436; RV64-NEXT:    vmsltu.vx v10, v8, a02437; RV64-NEXT:    vmandn.mm v0, v0, v102438; RV64-NEXT:    ret2439entry:2440  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(2441    <vscale x 2 x i1> %0,2442    <vscale x 2 x i64> %1,2443    i64 %2,2444    <vscale x 2 x i1> %0,2445    iXLen %3)2446 2447  ret <vscale x 2 x i1> %a2448}2449 2450define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, iXLen %3) nounwind {2451; RV32-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:2452; RV32:       # %bb.0: # %entry2453; RV32-NEXT:    addi sp, sp, -162454; RV32-NEXT:    sw a0, 8(sp)2455; RV32-NEXT:    sw a1, 12(sp)2456; RV32-NEXT:    addi a0, sp, 82457; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu2458; RV32-NEXT:    vlse64.v v16, (a0), zero2459; RV32-NEXT:    vmv1r.v v12, v02460; RV32-NEXT:    vmsleu.vv v12, v16, v8, v0.t2461; RV32-NEXT:    vmv1r.v v0, v122462; RV32-NEXT:    addi sp, sp, 162463; RV32-NEXT:    ret2464;2465; RV64-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:2466; RV64:       # %bb.0: # %entry2467; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2468; RV64-NEXT:    vmsltu.vx v12, v8, a02469; RV64-NEXT:    vmandn.mm v0, v0, v122470; RV64-NEXT:    ret2471entry:2472  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(2473    <vscale x 4 x i1> %0,2474    <vscale x 4 x i64> %1,2475    i64 %2,2476    <vscale x 4 x i1> %0,2477    iXLen %3)2478 2479  ret <vscale x 4 x i1> %a2480}2481