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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmslt.vv v0, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 iXLen %2)18 19 ret <vscale x 1 x i1> %a20}21 22define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu26; CHECK-NEXT: vmv1r.v v11, v027; CHECK-NEXT: vmslt.vv v0, v8, v928; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t29; CHECK-NEXT: vmv1r.v v0, v1130; CHECK-NEXT: ret31entry:32 %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(33 <vscale x 1 x i8> %1,34 <vscale x 1 x i8> %2,35 iXLen %4)36 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(37 <vscale x 1 x i1> %0,38 <vscale x 1 x i8> %2,39 <vscale x 1 x i8> %3,40 <vscale x 1 x i1> %mask,41 iXLen %4)42 43 ret <vscale x 1 x i1> %a44}45 46define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma50; CHECK-NEXT: vmslt.vv v0, v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(54 <vscale x 2 x i8> %0,55 <vscale x 2 x i8> %1,56 iXLen %2)57 58 ret <vscale x 2 x i1> %a59}60 61define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, iXLen %4) nounwind {62; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu65; CHECK-NEXT: vmv1r.v v11, v066; CHECK-NEXT: vmslt.vv v0, v8, v967; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t68; CHECK-NEXT: vmv1r.v v0, v1169; CHECK-NEXT: ret70entry:71 %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(72 <vscale x 2 x i8> %1,73 <vscale x 2 x i8> %2,74 iXLen %4)75 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(76 <vscale x 2 x i1> %0,77 <vscale x 2 x i8> %2,78 <vscale x 2 x i8> %3,79 <vscale x 2 x i1> %mask,80 iXLen %4)81 82 ret <vscale x 2 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma89; CHECK-NEXT: vmslt.vv v0, v8, v990; CHECK-NEXT: ret91entry:92 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(93 <vscale x 4 x i8> %0,94 <vscale x 4 x i8> %1,95 iXLen %2)96 97 ret <vscale x 4 x i1> %a98}99 100define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu104; CHECK-NEXT: vmv1r.v v11, v0105; CHECK-NEXT: vmslt.vv v0, v8, v9106; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t107; CHECK-NEXT: vmv1r.v v0, v11108; CHECK-NEXT: ret109entry:110 %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(111 <vscale x 4 x i8> %1,112 <vscale x 4 x i8> %2,113 iXLen %4)114 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(115 <vscale x 4 x i1> %0,116 <vscale x 4 x i8> %2,117 <vscale x 4 x i8> %3,118 <vscale x 4 x i1> %mask,119 iXLen %4)120 121 ret <vscale x 4 x i1> %a122}123 124define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma128; CHECK-NEXT: vmslt.vv v0, v8, v9129; CHECK-NEXT: ret130entry:131 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(132 <vscale x 8 x i8> %0,133 <vscale x 8 x i8> %1,134 iXLen %2)135 136 ret <vscale x 8 x i1> %a137}138 139define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu143; CHECK-NEXT: vmv1r.v v11, v0144; CHECK-NEXT: vmslt.vv v0, v8, v9145; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t146; CHECK-NEXT: vmv.v.v v0, v11147; CHECK-NEXT: ret148entry:149 %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(150 <vscale x 8 x i8> %1,151 <vscale x 8 x i8> %2,152 iXLen %4)153 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(154 <vscale x 8 x i1> %0,155 <vscale x 8 x i8> %2,156 <vscale x 8 x i8> %3,157 <vscale x 8 x i1> %mask,158 iXLen %4)159 160 ret <vscale x 8 x i1> %a161}162 163define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {164; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8:165; CHECK: # %bb.0: # %entry166; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma167; CHECK-NEXT: vmslt.vv v0, v8, v10168; CHECK-NEXT: ret169entry:170 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(171 <vscale x 16 x i8> %0,172 <vscale x 16 x i8> %1,173 iXLen %2)174 175 ret <vscale x 16 x i1> %a176}177 178define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, iXLen %4) nounwind {179; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu182; CHECK-NEXT: vmv1r.v v14, v0183; CHECK-NEXT: vmslt.vv v0, v8, v10184; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t185; CHECK-NEXT: vmv1r.v v0, v14186; CHECK-NEXT: ret187entry:188 %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(189 <vscale x 16 x i8> %1,190 <vscale x 16 x i8> %2,191 iXLen %4)192 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(193 <vscale x 16 x i1> %0,194 <vscale x 16 x i8> %2,195 <vscale x 16 x i8> %3,196 <vscale x 16 x i1> %mask,197 iXLen %4)198 199 ret <vscale x 16 x i1> %a200}201 202define <vscale x 32 x i1> @intrinsic_vmslt_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma206; CHECK-NEXT: vmslt.vv v0, v8, v12207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(210 <vscale x 32 x i8> %0,211 <vscale x 32 x i8> %1,212 iXLen %2)213 214 ret <vscale x 32 x i1> %a215}216 217define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, iXLen %4) nounwind {218; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu221; CHECK-NEXT: vmv1r.v v20, v0222; CHECK-NEXT: vmslt.vv v0, v8, v12223; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t224; CHECK-NEXT: vmv1r.v v0, v20225; CHECK-NEXT: ret226entry:227 %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(228 <vscale x 32 x i8> %1,229 <vscale x 32 x i8> %2,230 iXLen %4)231 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(232 <vscale x 32 x i1> %0,233 <vscale x 32 x i8> %2,234 <vscale x 32 x i8> %3,235 <vscale x 32 x i1> %mask,236 iXLen %4)237 238 ret <vscale x 32 x i1> %a239}240 241define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {242; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma245; CHECK-NEXT: vmslt.vv v0, v8, v9246; CHECK-NEXT: ret247entry:248 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(249 <vscale x 1 x i16> %0,250 <vscale x 1 x i16> %1,251 iXLen %2)252 253 ret <vscale x 1 x i1> %a254}255 256define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, iXLen %4) nounwind {257; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:258; CHECK: # %bb.0: # %entry259; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu260; CHECK-NEXT: vmv1r.v v11, v0261; CHECK-NEXT: vmslt.vv v0, v8, v9262; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t263; CHECK-NEXT: vmv1r.v v0, v11264; CHECK-NEXT: ret265entry:266 %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(267 <vscale x 1 x i16> %1,268 <vscale x 1 x i16> %2,269 iXLen %4)270 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(271 <vscale x 1 x i1> %0,272 <vscale x 1 x i16> %2,273 <vscale x 1 x i16> %3,274 <vscale x 1 x i1> %mask,275 iXLen %4)276 277 ret <vscale x 1 x i1> %a278}279 280define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {281; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16:282; CHECK: # %bb.0: # %entry283; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma284; CHECK-NEXT: vmslt.vv v0, v8, v9285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(288 <vscale x 2 x i16> %0,289 <vscale x 2 x i16> %1,290 iXLen %2)291 292 ret <vscale x 2 x i1> %a293}294 295define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu299; CHECK-NEXT: vmv1r.v v11, v0300; CHECK-NEXT: vmslt.vv v0, v8, v9301; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t302; CHECK-NEXT: vmv1r.v v0, v11303; CHECK-NEXT: ret304entry:305 %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(306 <vscale x 2 x i16> %1,307 <vscale x 2 x i16> %2,308 iXLen %4)309 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(310 <vscale x 2 x i1> %0,311 <vscale x 2 x i16> %2,312 <vscale x 2 x i16> %3,313 <vscale x 2 x i1> %mask,314 iXLen %4)315 316 ret <vscale x 2 x i1> %a317}318 319define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {320; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16:321; CHECK: # %bb.0: # %entry322; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma323; CHECK-NEXT: vmslt.vv v0, v8, v9324; CHECK-NEXT: ret325entry:326 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(327 <vscale x 4 x i16> %0,328 <vscale x 4 x i16> %1,329 iXLen %2)330 331 ret <vscale x 4 x i1> %a332}333 334define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, iXLen %4) nounwind {335; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:336; CHECK: # %bb.0: # %entry337; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu338; CHECK-NEXT: vmv1r.v v11, v0339; CHECK-NEXT: vmslt.vv v0, v8, v9340; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t341; CHECK-NEXT: vmv.v.v v0, v11342; CHECK-NEXT: ret343entry:344 %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(345 <vscale x 4 x i16> %1,346 <vscale x 4 x i16> %2,347 iXLen %4)348 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(349 <vscale x 4 x i1> %0,350 <vscale x 4 x i16> %2,351 <vscale x 4 x i16> %3,352 <vscale x 4 x i1> %mask,353 iXLen %4)354 355 ret <vscale x 4 x i1> %a356}357 358define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {359; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma362; CHECK-NEXT: vmslt.vv v0, v8, v10363; CHECK-NEXT: ret364entry:365 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(366 <vscale x 8 x i16> %0,367 <vscale x 8 x i16> %1,368 iXLen %2)369 370 ret <vscale x 8 x i1> %a371}372 373define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, iXLen %4) nounwind {374; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:375; CHECK: # %bb.0: # %entry376; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu377; CHECK-NEXT: vmv1r.v v14, v0378; CHECK-NEXT: vmslt.vv v0, v8, v10379; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t380; CHECK-NEXT: vmv1r.v v0, v14381; CHECK-NEXT: ret382entry:383 %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(384 <vscale x 8 x i16> %1,385 <vscale x 8 x i16> %2,386 iXLen %4)387 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(388 <vscale x 8 x i1> %0,389 <vscale x 8 x i16> %2,390 <vscale x 8 x i16> %3,391 <vscale x 8 x i1> %mask,392 iXLen %4)393 394 ret <vscale x 8 x i1> %a395}396 397define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma401; CHECK-NEXT: vmslt.vv v0, v8, v12402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(405 <vscale x 16 x i16> %0,406 <vscale x 16 x i16> %1,407 iXLen %2)408 409 ret <vscale x 16 x i1> %a410}411 412define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, iXLen %4) nounwind {413; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu416; CHECK-NEXT: vmv1r.v v20, v0417; CHECK-NEXT: vmslt.vv v0, v8, v12418; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t419; CHECK-NEXT: vmv1r.v v0, v20420; CHECK-NEXT: ret421entry:422 %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(423 <vscale x 16 x i16> %1,424 <vscale x 16 x i16> %2,425 iXLen %4)426 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(427 <vscale x 16 x i1> %0,428 <vscale x 16 x i16> %2,429 <vscale x 16 x i16> %3,430 <vscale x 16 x i1> %mask,431 iXLen %4)432 433 ret <vscale x 16 x i1> %a434}435 436define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma440; CHECK-NEXT: vmslt.vv v0, v8, v9441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(444 <vscale x 1 x i32> %0,445 <vscale x 1 x i32> %1,446 iXLen %2)447 448 ret <vscale x 1 x i1> %a449}450 451define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, iXLen %4) nounwind {452; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu455; CHECK-NEXT: vmv1r.v v11, v0456; CHECK-NEXT: vmslt.vv v0, v8, v9457; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t458; CHECK-NEXT: vmv1r.v v0, v11459; CHECK-NEXT: ret460entry:461 %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(462 <vscale x 1 x i32> %1,463 <vscale x 1 x i32> %2,464 iXLen %4)465 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(466 <vscale x 1 x i1> %0,467 <vscale x 1 x i32> %2,468 <vscale x 1 x i32> %3,469 <vscale x 1 x i1> %mask,470 iXLen %4)471 472 ret <vscale x 1 x i1> %a473}474 475define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32:477; CHECK: # %bb.0: # %entry478; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma479; CHECK-NEXT: vmslt.vv v0, v8, v9480; CHECK-NEXT: ret481entry:482 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(483 <vscale x 2 x i32> %0,484 <vscale x 2 x i32> %1,485 iXLen %2)486 487 ret <vscale x 2 x i1> %a488}489 490define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, iXLen %4) nounwind {491; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:492; CHECK: # %bb.0: # %entry493; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu494; CHECK-NEXT: vmv1r.v v11, v0495; CHECK-NEXT: vmslt.vv v0, v8, v9496; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t497; CHECK-NEXT: vmv.v.v v0, v11498; CHECK-NEXT: ret499entry:500 %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(501 <vscale x 2 x i32> %1,502 <vscale x 2 x i32> %2,503 iXLen %4)504 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(505 <vscale x 2 x i1> %0,506 <vscale x 2 x i32> %2,507 <vscale x 2 x i32> %3,508 <vscale x 2 x i1> %mask,509 iXLen %4)510 511 ret <vscale x 2 x i1> %a512}513 514define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {515; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma518; CHECK-NEXT: vmslt.vv v0, v8, v10519; CHECK-NEXT: ret520entry:521 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(522 <vscale x 4 x i32> %0,523 <vscale x 4 x i32> %1,524 iXLen %2)525 526 ret <vscale x 4 x i1> %a527}528 529define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:531; CHECK: # %bb.0: # %entry532; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu533; CHECK-NEXT: vmv1r.v v14, v0534; CHECK-NEXT: vmslt.vv v0, v8, v10535; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t536; CHECK-NEXT: vmv1r.v v0, v14537; CHECK-NEXT: ret538entry:539 %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(540 <vscale x 4 x i32> %1,541 <vscale x 4 x i32> %2,542 iXLen %4)543 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(544 <vscale x 4 x i1> %0,545 <vscale x 4 x i32> %2,546 <vscale x 4 x i32> %3,547 <vscale x 4 x i1> %mask,548 iXLen %4)549 550 ret <vscale x 4 x i1> %a551}552 553define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {554; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32:555; CHECK: # %bb.0: # %entry556; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma557; CHECK-NEXT: vmslt.vv v0, v8, v12558; CHECK-NEXT: ret559entry:560 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(561 <vscale x 8 x i32> %0,562 <vscale x 8 x i32> %1,563 iXLen %2)564 565 ret <vscale x 8 x i1> %a566}567 568define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu572; CHECK-NEXT: vmv1r.v v20, v0573; CHECK-NEXT: vmslt.vv v0, v8, v12574; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t575; CHECK-NEXT: vmv1r.v v0, v20576; CHECK-NEXT: ret577entry:578 %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(579 <vscale x 8 x i32> %1,580 <vscale x 8 x i32> %2,581 iXLen %4)582 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(583 <vscale x 8 x i1> %0,584 <vscale x 8 x i32> %2,585 <vscale x 8 x i32> %3,586 <vscale x 8 x i1> %mask,587 iXLen %4)588 589 ret <vscale x 8 x i1> %a590}591 592define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {593; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i64_nxv1i64:594; CHECK: # %bb.0: # %entry595; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma596; CHECK-NEXT: vmslt.vv v0, v8, v9597; CHECK-NEXT: ret598entry:599 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(600 <vscale x 1 x i64> %0,601 <vscale x 1 x i64> %1,602 iXLen %2)603 604 ret <vscale x 1 x i1> %a605}606 607define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, iXLen %4) nounwind {608; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:609; CHECK: # %bb.0: # %entry610; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu611; CHECK-NEXT: vmv1r.v v11, v0612; CHECK-NEXT: vmslt.vv v0, v8, v9613; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t614; CHECK-NEXT: vmv.v.v v0, v11615; CHECK-NEXT: ret616entry:617 %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(618 <vscale x 1 x i64> %1,619 <vscale x 1 x i64> %2,620 iXLen %4)621 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(622 <vscale x 1 x i1> %0,623 <vscale x 1 x i64> %2,624 <vscale x 1 x i64> %3,625 <vscale x 1 x i1> %mask,626 iXLen %4)627 628 ret <vscale x 1 x i1> %a629}630 631define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {632; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i64_nxv2i64:633; CHECK: # %bb.0: # %entry634; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma635; CHECK-NEXT: vmslt.vv v0, v8, v10636; CHECK-NEXT: ret637entry:638 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(639 <vscale x 2 x i64> %0,640 <vscale x 2 x i64> %1,641 iXLen %2)642 643 ret <vscale x 2 x i1> %a644}645 646define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, iXLen %4) nounwind {647; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:648; CHECK: # %bb.0: # %entry649; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu650; CHECK-NEXT: vmv1r.v v14, v0651; CHECK-NEXT: vmslt.vv v0, v8, v10652; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t653; CHECK-NEXT: vmv1r.v v0, v14654; CHECK-NEXT: ret655entry:656 %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(657 <vscale x 2 x i64> %1,658 <vscale x 2 x i64> %2,659 iXLen %4)660 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(661 <vscale x 2 x i1> %0,662 <vscale x 2 x i64> %2,663 <vscale x 2 x i64> %3,664 <vscale x 2 x i1> %mask,665 iXLen %4)666 667 ret <vscale x 2 x i1> %a668}669 670define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i64_nxv4i64:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT: vmslt.vv v0, v8, v12675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(678 <vscale x 4 x i64> %0,679 <vscale x 4 x i64> %1,680 iXLen %2)681 682 ret <vscale x 4 x i1> %a683}684 685define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, iXLen %4) nounwind {686; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:687; CHECK: # %bb.0: # %entry688; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu689; CHECK-NEXT: vmv1r.v v20, v0690; CHECK-NEXT: vmslt.vv v0, v8, v12691; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t692; CHECK-NEXT: vmv1r.v v0, v20693; CHECK-NEXT: ret694entry:695 %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(696 <vscale x 4 x i64> %1,697 <vscale x 4 x i64> %2,698 iXLen %4)699 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(700 <vscale x 4 x i1> %0,701 <vscale x 4 x i64> %2,702 <vscale x 4 x i64> %3,703 <vscale x 4 x i1> %mask,704 iXLen %4)705 706 ret <vscale x 4 x i1> %a707}708 709define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {710; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8:711; CHECK: # %bb.0: # %entry712; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma713; CHECK-NEXT: vmslt.vx v0, v8, a0714; CHECK-NEXT: ret715entry:716 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(717 <vscale x 1 x i8> %0,718 i8 %1,719 iXLen %2)720 721 ret <vscale x 1 x i1> %a722}723 724define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {725; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:726; CHECK: # %bb.0: # %entry727; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu728; CHECK-NEXT: vmv1r.v v10, v0729; CHECK-NEXT: vmv1r.v v0, v9730; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t731; CHECK-NEXT: vmv1r.v v0, v10732; CHECK-NEXT: ret733entry:734 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(735 <vscale x 1 x i1> %0,736 <vscale x 1 x i8> %1,737 i8 %2,738 <vscale x 1 x i1> %3,739 iXLen %4)740 741 ret <vscale x 1 x i1> %a742}743 744define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {745; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8:746; CHECK: # %bb.0: # %entry747; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma748; CHECK-NEXT: vmslt.vx v0, v8, a0749; CHECK-NEXT: ret750entry:751 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(752 <vscale x 2 x i8> %0,753 i8 %1,754 iXLen %2)755 756 ret <vscale x 2 x i1> %a757}758 759define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {760; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:761; CHECK: # %bb.0: # %entry762; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu763; CHECK-NEXT: vmv1r.v v10, v0764; CHECK-NEXT: vmv1r.v v0, v9765; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t766; CHECK-NEXT: vmv1r.v v0, v10767; CHECK-NEXT: ret768entry:769 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(770 <vscale x 2 x i1> %0,771 <vscale x 2 x i8> %1,772 i8 %2,773 <vscale x 2 x i1> %3,774 iXLen %4)775 776 ret <vscale x 2 x i1> %a777}778 779define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {780; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8:781; CHECK: # %bb.0: # %entry782; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma783; CHECK-NEXT: vmslt.vx v0, v8, a0784; CHECK-NEXT: ret785entry:786 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(787 <vscale x 4 x i8> %0,788 i8 %1,789 iXLen %2)790 791 ret <vscale x 4 x i1> %a792}793 794define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {795; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:796; CHECK: # %bb.0: # %entry797; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu798; CHECK-NEXT: vmv1r.v v10, v0799; CHECK-NEXT: vmv1r.v v0, v9800; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t801; CHECK-NEXT: vmv1r.v v0, v10802; CHECK-NEXT: ret803entry:804 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(805 <vscale x 4 x i1> %0,806 <vscale x 4 x i8> %1,807 i8 %2,808 <vscale x 4 x i1> %3,809 iXLen %4)810 811 ret <vscale x 4 x i1> %a812}813 814define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {815; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8:816; CHECK: # %bb.0: # %entry817; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma818; CHECK-NEXT: vmslt.vx v0, v8, a0819; CHECK-NEXT: ret820entry:821 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(822 <vscale x 8 x i8> %0,823 i8 %1,824 iXLen %2)825 826 ret <vscale x 8 x i1> %a827}828 829define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {830; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:831; CHECK: # %bb.0: # %entry832; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu833; CHECK-NEXT: vmv1r.v v10, v0834; CHECK-NEXT: vmv1r.v v0, v9835; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t836; CHECK-NEXT: vmv.v.v v0, v10837; CHECK-NEXT: ret838entry:839 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(840 <vscale x 8 x i1> %0,841 <vscale x 8 x i8> %1,842 i8 %2,843 <vscale x 8 x i1> %3,844 iXLen %4)845 846 ret <vscale x 8 x i1> %a847}848 849define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {850; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8:851; CHECK: # %bb.0: # %entry852; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma853; CHECK-NEXT: vmslt.vx v0, v8, a0854; CHECK-NEXT: ret855entry:856 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(857 <vscale x 16 x i8> %0,858 i8 %1,859 iXLen %2)860 861 ret <vscale x 16 x i1> %a862}863 864define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {865; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:866; CHECK: # %bb.0: # %entry867; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu868; CHECK-NEXT: vmv1r.v v11, v0869; CHECK-NEXT: vmv1r.v v0, v10870; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t871; CHECK-NEXT: vmv1r.v v0, v11872; CHECK-NEXT: ret873entry:874 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(875 <vscale x 16 x i1> %0,876 <vscale x 16 x i8> %1,877 i8 %2,878 <vscale x 16 x i1> %3,879 iXLen %4)880 881 ret <vscale x 16 x i1> %a882}883 884define <vscale x 32 x i1> @intrinsic_vmslt_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {885; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8:886; CHECK: # %bb.0: # %entry887; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma888; CHECK-NEXT: vmslt.vx v0, v8, a0889; CHECK-NEXT: ret890entry:891 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(892 <vscale x 32 x i8> %0,893 i8 %1,894 iXLen %2)895 896 ret <vscale x 32 x i1> %a897}898 899define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {900; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:901; CHECK: # %bb.0: # %entry902; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu903; CHECK-NEXT: vmv1r.v v13, v0904; CHECK-NEXT: vmv1r.v v0, v12905; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t906; CHECK-NEXT: vmv1r.v v0, v13907; CHECK-NEXT: ret908entry:909 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(910 <vscale x 32 x i1> %0,911 <vscale x 32 x i8> %1,912 i8 %2,913 <vscale x 32 x i1> %3,914 iXLen %4)915 916 ret <vscale x 32 x i1> %a917}918 919define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {920; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16:921; CHECK: # %bb.0: # %entry922; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma923; CHECK-NEXT: vmslt.vx v0, v8, a0924; CHECK-NEXT: ret925entry:926 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(927 <vscale x 1 x i16> %0,928 i16 %1,929 iXLen %2)930 931 ret <vscale x 1 x i1> %a932}933 934define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {935; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:936; CHECK: # %bb.0: # %entry937; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu938; CHECK-NEXT: vmv1r.v v10, v0939; CHECK-NEXT: vmv1r.v v0, v9940; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t941; CHECK-NEXT: vmv1r.v v0, v10942; CHECK-NEXT: ret943entry:944 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(945 <vscale x 1 x i1> %0,946 <vscale x 1 x i16> %1,947 i16 %2,948 <vscale x 1 x i1> %3,949 iXLen %4)950 951 ret <vscale x 1 x i1> %a952}953 954define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {955; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16:956; CHECK: # %bb.0: # %entry957; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma958; CHECK-NEXT: vmslt.vx v0, v8, a0959; CHECK-NEXT: ret960entry:961 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(962 <vscale x 2 x i16> %0,963 i16 %1,964 iXLen %2)965 966 ret <vscale x 2 x i1> %a967}968 969define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {970; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:971; CHECK: # %bb.0: # %entry972; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu973; CHECK-NEXT: vmv1r.v v10, v0974; CHECK-NEXT: vmv1r.v v0, v9975; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t976; CHECK-NEXT: vmv1r.v v0, v10977; CHECK-NEXT: ret978entry:979 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(980 <vscale x 2 x i1> %0,981 <vscale x 2 x i16> %1,982 i16 %2,983 <vscale x 2 x i1> %3,984 iXLen %4)985 986 ret <vscale x 2 x i1> %a987}988 989define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {990; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16:991; CHECK: # %bb.0: # %entry992; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma993; CHECK-NEXT: vmslt.vx v0, v8, a0994; CHECK-NEXT: ret995entry:996 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(997 <vscale x 4 x i16> %0,998 i16 %1,999 iXLen %2)1000 1001 ret <vscale x 4 x i1> %a1002}1003 1004define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1005; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:1006; CHECK: # %bb.0: # %entry1007; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1008; CHECK-NEXT: vmv1r.v v10, v01009; CHECK-NEXT: vmv1r.v v0, v91010; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t1011; CHECK-NEXT: vmv.v.v v0, v101012; CHECK-NEXT: ret1013entry:1014 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(1015 <vscale x 4 x i1> %0,1016 <vscale x 4 x i16> %1,1017 i16 %2,1018 <vscale x 4 x i1> %3,1019 iXLen %4)1020 1021 ret <vscale x 4 x i1> %a1022}1023 1024define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1025; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16:1026; CHECK: # %bb.0: # %entry1027; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1028; CHECK-NEXT: vmslt.vx v0, v8, a01029; CHECK-NEXT: ret1030entry:1031 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(1032 <vscale x 8 x i16> %0,1033 i16 %1,1034 iXLen %2)1035 1036 ret <vscale x 8 x i1> %a1037}1038 1039define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1040; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:1041; CHECK: # %bb.0: # %entry1042; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1043; CHECK-NEXT: vmv1r.v v11, v01044; CHECK-NEXT: vmv1r.v v0, v101045; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t1046; CHECK-NEXT: vmv1r.v v0, v111047; CHECK-NEXT: ret1048entry:1049 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(1050 <vscale x 8 x i1> %0,1051 <vscale x 8 x i16> %1,1052 i16 %2,1053 <vscale x 8 x i1> %3,1054 iXLen %4)1055 1056 ret <vscale x 8 x i1> %a1057}1058 1059define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1060; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16:1061; CHECK: # %bb.0: # %entry1062; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1063; CHECK-NEXT: vmslt.vx v0, v8, a01064; CHECK-NEXT: ret1065entry:1066 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(1067 <vscale x 16 x i16> %0,1068 i16 %1,1069 iXLen %2)1070 1071 ret <vscale x 16 x i1> %a1072}1073 1074define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1075; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:1076; CHECK: # %bb.0: # %entry1077; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1078; CHECK-NEXT: vmv1r.v v13, v01079; CHECK-NEXT: vmv1r.v v0, v121080; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t1081; CHECK-NEXT: vmv1r.v v0, v131082; CHECK-NEXT: ret1083entry:1084 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(1085 <vscale x 16 x i1> %0,1086 <vscale x 16 x i16> %1,1087 i16 %2,1088 <vscale x 16 x i1> %3,1089 iXLen %4)1090 1091 ret <vscale x 16 x i1> %a1092}1093 1094define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1095; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32:1096; CHECK: # %bb.0: # %entry1097; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1098; CHECK-NEXT: vmslt.vx v0, v8, a01099; CHECK-NEXT: ret1100entry:1101 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(1102 <vscale x 1 x i32> %0,1103 i32 %1,1104 iXLen %2)1105 1106 ret <vscale x 1 x i1> %a1107}1108 1109define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1110; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:1111; CHECK: # %bb.0: # %entry1112; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1113; CHECK-NEXT: vmv1r.v v10, v01114; CHECK-NEXT: vmv1r.v v0, v91115; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t1116; CHECK-NEXT: vmv1r.v v0, v101117; CHECK-NEXT: ret1118entry:1119 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(1120 <vscale x 1 x i1> %0,1121 <vscale x 1 x i32> %1,1122 i32 %2,1123 <vscale x 1 x i1> %3,1124 iXLen %4)1125 1126 ret <vscale x 1 x i1> %a1127}1128 1129define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1130; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32:1131; CHECK: # %bb.0: # %entry1132; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1133; CHECK-NEXT: vmslt.vx v0, v8, a01134; CHECK-NEXT: ret1135entry:1136 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(1137 <vscale x 2 x i32> %0,1138 i32 %1,1139 iXLen %2)1140 1141 ret <vscale x 2 x i1> %a1142}1143 1144define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1145; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:1146; CHECK: # %bb.0: # %entry1147; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1148; CHECK-NEXT: vmv1r.v v10, v01149; CHECK-NEXT: vmv1r.v v0, v91150; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t1151; CHECK-NEXT: vmv.v.v v0, v101152; CHECK-NEXT: ret1153entry:1154 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(1155 <vscale x 2 x i1> %0,1156 <vscale x 2 x i32> %1,1157 i32 %2,1158 <vscale x 2 x i1> %3,1159 iXLen %4)1160 1161 ret <vscale x 2 x i1> %a1162}1163 1164define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1165; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32:1166; CHECK: # %bb.0: # %entry1167; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1168; CHECK-NEXT: vmslt.vx v0, v8, a01169; CHECK-NEXT: ret1170entry:1171 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(1172 <vscale x 4 x i32> %0,1173 i32 %1,1174 iXLen %2)1175 1176 ret <vscale x 4 x i1> %a1177}1178 1179define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1180; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:1181; CHECK: # %bb.0: # %entry1182; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1183; CHECK-NEXT: vmv1r.v v11, v01184; CHECK-NEXT: vmv1r.v v0, v101185; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t1186; CHECK-NEXT: vmv1r.v v0, v111187; CHECK-NEXT: ret1188entry:1189 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(1190 <vscale x 4 x i1> %0,1191 <vscale x 4 x i32> %1,1192 i32 %2,1193 <vscale x 4 x i1> %3,1194 iXLen %4)1195 1196 ret <vscale x 4 x i1> %a1197}1198 1199define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1200; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32:1201; CHECK: # %bb.0: # %entry1202; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1203; CHECK-NEXT: vmslt.vx v0, v8, a01204; CHECK-NEXT: ret1205entry:1206 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(1207 <vscale x 8 x i32> %0,1208 i32 %1,1209 iXLen %2)1210 1211 ret <vscale x 8 x i1> %a1212}1213 1214define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1215; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:1216; CHECK: # %bb.0: # %entry1217; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1218; CHECK-NEXT: vmv1r.v v13, v01219; CHECK-NEXT: vmv1r.v v0, v121220; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t1221; CHECK-NEXT: vmv1r.v v0, v131222; CHECK-NEXT: ret1223entry:1224 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(1225 <vscale x 8 x i1> %0,1226 <vscale x 8 x i32> %1,1227 i32 %2,1228 <vscale x 8 x i1> %3,1229 iXLen %4)1230 1231 ret <vscale x 8 x i1> %a1232}1233 1234define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1235; RV32-LABEL: intrinsic_vmslt_vx_nxv1i64_i64:1236; RV32: # %bb.0: # %entry1237; RV32-NEXT: addi sp, sp, -161238; RV32-NEXT: sw a0, 8(sp)1239; RV32-NEXT: sw a1, 12(sp)1240; RV32-NEXT: addi a0, sp, 81241; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1242; RV32-NEXT: vlse64.v v9, (a0), zero1243; RV32-NEXT: vmslt.vv v0, v8, v91244; RV32-NEXT: addi sp, sp, 161245; RV32-NEXT: ret1246;1247; RV64-LABEL: intrinsic_vmslt_vx_nxv1i64_i64:1248; RV64: # %bb.0: # %entry1249; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1250; RV64-NEXT: vmslt.vx v0, v8, a01251; RV64-NEXT: ret1252entry:1253 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(1254 <vscale x 1 x i64> %0,1255 i64 %1,1256 iXLen %2)1257 1258 ret <vscale x 1 x i1> %a1259}1260 1261define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1262; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:1263; RV32: # %bb.0: # %entry1264; RV32-NEXT: addi sp, sp, -161265; RV32-NEXT: sw a0, 8(sp)1266; RV32-NEXT: sw a1, 12(sp)1267; RV32-NEXT: addi a0, sp, 81268; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu1269; RV32-NEXT: vlse64.v v11, (a0), zero1270; RV32-NEXT: vmv1r.v v10, v01271; RV32-NEXT: vmv1r.v v0, v91272; RV32-NEXT: vmslt.vv v10, v8, v11, v0.t1273; RV32-NEXT: vmv.v.v v0, v101274; RV32-NEXT: addi sp, sp, 161275; RV32-NEXT: ret1276;1277; RV64-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:1278; RV64: # %bb.0: # %entry1279; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu1280; RV64-NEXT: vmv1r.v v10, v01281; RV64-NEXT: vmv1r.v v0, v91282; RV64-NEXT: vmslt.vx v10, v8, a0, v0.t1283; RV64-NEXT: vmv.v.v v0, v101284; RV64-NEXT: ret1285entry:1286 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(1287 <vscale x 1 x i1> %0,1288 <vscale x 1 x i64> %1,1289 i64 %2,1290 <vscale x 1 x i1> %3,1291 iXLen %4)1292 1293 ret <vscale x 1 x i1> %a1294}1295 1296define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1297; RV32-LABEL: intrinsic_vmslt_vx_nxv2i64_i64:1298; RV32: # %bb.0: # %entry1299; RV32-NEXT: addi sp, sp, -161300; RV32-NEXT: sw a0, 8(sp)1301; RV32-NEXT: sw a1, 12(sp)1302; RV32-NEXT: addi a0, sp, 81303; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1304; RV32-NEXT: vlse64.v v10, (a0), zero1305; RV32-NEXT: vmslt.vv v0, v8, v101306; RV32-NEXT: addi sp, sp, 161307; RV32-NEXT: ret1308;1309; RV64-LABEL: intrinsic_vmslt_vx_nxv2i64_i64:1310; RV64: # %bb.0: # %entry1311; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1312; RV64-NEXT: vmslt.vx v0, v8, a01313; RV64-NEXT: ret1314entry:1315 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(1316 <vscale x 2 x i64> %0,1317 i64 %1,1318 iXLen %2)1319 1320 ret <vscale x 2 x i1> %a1321}1322 1323define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1324; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:1325; RV32: # %bb.0: # %entry1326; RV32-NEXT: addi sp, sp, -161327; RV32-NEXT: sw a0, 8(sp)1328; RV32-NEXT: sw a1, 12(sp)1329; RV32-NEXT: addi a0, sp, 81330; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu1331; RV32-NEXT: vlse64.v v12, (a0), zero1332; RV32-NEXT: vmv1r.v v11, v01333; RV32-NEXT: vmv1r.v v0, v101334; RV32-NEXT: vmslt.vv v11, v8, v12, v0.t1335; RV32-NEXT: vmv1r.v v0, v111336; RV32-NEXT: addi sp, sp, 161337; RV32-NEXT: ret1338;1339; RV64-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:1340; RV64: # %bb.0: # %entry1341; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu1342; RV64-NEXT: vmv1r.v v11, v01343; RV64-NEXT: vmv1r.v v0, v101344; RV64-NEXT: vmslt.vx v11, v8, a0, v0.t1345; RV64-NEXT: vmv1r.v v0, v111346; RV64-NEXT: ret1347entry:1348 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(1349 <vscale x 2 x i1> %0,1350 <vscale x 2 x i64> %1,1351 i64 %2,1352 <vscale x 2 x i1> %3,1353 iXLen %4)1354 1355 ret <vscale x 2 x i1> %a1356}1357 1358define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1359; RV32-LABEL: intrinsic_vmslt_vx_nxv4i64_i64:1360; RV32: # %bb.0: # %entry1361; RV32-NEXT: addi sp, sp, -161362; RV32-NEXT: sw a0, 8(sp)1363; RV32-NEXT: sw a1, 12(sp)1364; RV32-NEXT: addi a0, sp, 81365; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1366; RV32-NEXT: vlse64.v v12, (a0), zero1367; RV32-NEXT: vmslt.vv v0, v8, v121368; RV32-NEXT: addi sp, sp, 161369; RV32-NEXT: ret1370;1371; RV64-LABEL: intrinsic_vmslt_vx_nxv4i64_i64:1372; RV64: # %bb.0: # %entry1373; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1374; RV64-NEXT: vmslt.vx v0, v8, a01375; RV64-NEXT: ret1376entry:1377 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(1378 <vscale x 4 x i64> %0,1379 i64 %1,1380 iXLen %2)1381 1382 ret <vscale x 4 x i1> %a1383}1384 1385define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1386; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:1387; RV32: # %bb.0: # %entry1388; RV32-NEXT: addi sp, sp, -161389; RV32-NEXT: sw a0, 8(sp)1390; RV32-NEXT: sw a1, 12(sp)1391; RV32-NEXT: addi a0, sp, 81392; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu1393; RV32-NEXT: vlse64.v v16, (a0), zero1394; RV32-NEXT: vmv1r.v v13, v01395; RV32-NEXT: vmv1r.v v0, v121396; RV32-NEXT: vmslt.vv v13, v8, v16, v0.t1397; RV32-NEXT: vmv1r.v v0, v131398; RV32-NEXT: addi sp, sp, 161399; RV32-NEXT: ret1400;1401; RV64-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:1402; RV64: # %bb.0: # %entry1403; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu1404; RV64-NEXT: vmv1r.v v13, v01405; RV64-NEXT: vmv1r.v v0, v121406; RV64-NEXT: vmslt.vx v13, v8, a0, v0.t1407; RV64-NEXT: vmv1r.v v0, v131408; RV64-NEXT: ret1409entry:1410 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(1411 <vscale x 4 x i1> %0,1412 <vscale x 4 x i64> %1,1413 i64 %2,1414 <vscale x 4 x i1> %3,1415 iXLen %4)1416 1417 ret <vscale x 4 x i1> %a1418}1419 1420define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1421; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8:1422; CHECK: # %bb.0: # %entry1423; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1424; CHECK-NEXT: vmsle.vi v0, v8, -161425; CHECK-NEXT: ret1426entry:1427 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(1428 <vscale x 1 x i8> %0,1429 i8 -15,1430 iXLen %1)1431 1432 ret <vscale x 1 x i1> %a1433}1434 1435define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1436; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:1437; CHECK: # %bb.0: # %entry1438; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1439; CHECK-NEXT: vmv1r.v v10, v01440; CHECK-NEXT: vmv1r.v v0, v91441; CHECK-NEXT: vmsle.vi v10, v8, -15, v0.t1442; CHECK-NEXT: vmv1r.v v0, v101443; CHECK-NEXT: ret1444entry:1445 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(1446 <vscale x 1 x i1> %0,1447 <vscale x 1 x i8> %1,1448 i8 -14,1449 <vscale x 1 x i1> %2,1450 iXLen %3)1451 1452 ret <vscale x 1 x i1> %a1453}1454 1455define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1456; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8:1457; CHECK: # %bb.0: # %entry1458; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1459; CHECK-NEXT: vmsle.vi v0, v8, -141460; CHECK-NEXT: ret1461entry:1462 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(1463 <vscale x 2 x i8> %0,1464 i8 -13,1465 iXLen %1)1466 1467 ret <vscale x 2 x i1> %a1468}1469 1470define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1471; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:1472; CHECK: # %bb.0: # %entry1473; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1474; CHECK-NEXT: vmv1r.v v10, v01475; CHECK-NEXT: vmv1r.v v0, v91476; CHECK-NEXT: vmsle.vi v10, v8, -13, v0.t1477; CHECK-NEXT: vmv1r.v v0, v101478; CHECK-NEXT: ret1479entry:1480 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(1481 <vscale x 2 x i1> %0,1482 <vscale x 2 x i8> %1,1483 i8 -12,1484 <vscale x 2 x i1> %2,1485 iXLen %3)1486 1487 ret <vscale x 2 x i1> %a1488}1489 1490define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1491; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8:1492; CHECK: # %bb.0: # %entry1493; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1494; CHECK-NEXT: vmsle.vi v0, v8, -121495; CHECK-NEXT: ret1496entry:1497 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(1498 <vscale x 4 x i8> %0,1499 i8 -11,1500 iXLen %1)1501 1502 ret <vscale x 4 x i1> %a1503}1504 1505define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1506; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:1507; CHECK: # %bb.0: # %entry1508; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1509; CHECK-NEXT: vmv1r.v v10, v01510; CHECK-NEXT: vmv1r.v v0, v91511; CHECK-NEXT: vmsle.vi v10, v8, -11, v0.t1512; CHECK-NEXT: vmv1r.v v0, v101513; CHECK-NEXT: ret1514entry:1515 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(1516 <vscale x 4 x i1> %0,1517 <vscale x 4 x i8> %1,1518 i8 -10,1519 <vscale x 4 x i1> %2,1520 iXLen %3)1521 1522 ret <vscale x 4 x i1> %a1523}1524 1525define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1526; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8:1527; CHECK: # %bb.0: # %entry1528; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1529; CHECK-NEXT: vmsle.vi v0, v8, -101530; CHECK-NEXT: ret1531entry:1532 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(1533 <vscale x 8 x i8> %0,1534 i8 -9,1535 iXLen %1)1536 1537 ret <vscale x 8 x i1> %a1538}1539 1540define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1541; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:1542; CHECK: # %bb.0: # %entry1543; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1544; CHECK-NEXT: vmv1r.v v10, v01545; CHECK-NEXT: vmv1r.v v0, v91546; CHECK-NEXT: vmsle.vi v10, v8, -9, v0.t1547; CHECK-NEXT: vmv.v.v v0, v101548; CHECK-NEXT: ret1549entry:1550 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(1551 <vscale x 8 x i1> %0,1552 <vscale x 8 x i8> %1,1553 i8 -8,1554 <vscale x 8 x i1> %2,1555 iXLen %3)1556 1557 ret <vscale x 8 x i1> %a1558}1559 1560define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1561; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8:1562; CHECK: # %bb.0: # %entry1563; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1564; CHECK-NEXT: vmsle.vi v0, v8, -81565; CHECK-NEXT: ret1566entry:1567 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(1568 <vscale x 16 x i8> %0,1569 i8 -7,1570 iXLen %1)1571 1572 ret <vscale x 16 x i1> %a1573}1574 1575define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1576; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:1577; CHECK: # %bb.0: # %entry1578; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1579; CHECK-NEXT: vmv1r.v v11, v01580; CHECK-NEXT: vmv1r.v v0, v101581; CHECK-NEXT: vmsle.vi v11, v8, -7, v0.t1582; CHECK-NEXT: vmv1r.v v0, v111583; CHECK-NEXT: ret1584entry:1585 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(1586 <vscale x 16 x i1> %0,1587 <vscale x 16 x i8> %1,1588 i8 -6,1589 <vscale x 16 x i1> %2,1590 iXLen %3)1591 1592 ret <vscale x 16 x i1> %a1593}1594 1595define <vscale x 32 x i1> @intrinsic_vmslt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1596; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8:1597; CHECK: # %bb.0: # %entry1598; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1599; CHECK-NEXT: vmsle.vi v0, v8, -61600; CHECK-NEXT: ret1601entry:1602 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(1603 <vscale x 32 x i8> %0,1604 i8 -5,1605 iXLen %1)1606 1607 ret <vscale x 32 x i1> %a1608}1609 1610define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1611; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:1612; CHECK: # %bb.0: # %entry1613; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1614; CHECK-NEXT: vmv1r.v v13, v01615; CHECK-NEXT: vmv1r.v v0, v121616; CHECK-NEXT: vmsle.vi v13, v8, -5, v0.t1617; CHECK-NEXT: vmv1r.v v0, v131618; CHECK-NEXT: ret1619entry:1620 %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(1621 <vscale x 32 x i1> %0,1622 <vscale x 32 x i8> %1,1623 i8 -4,1624 <vscale x 32 x i1> %2,1625 iXLen %3)1626 1627 ret <vscale x 32 x i1> %a1628}1629 1630define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1631; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16:1632; CHECK: # %bb.0: # %entry1633; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1634; CHECK-NEXT: vmsle.vi v0, v8, -41635; CHECK-NEXT: ret1636entry:1637 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(1638 <vscale x 1 x i16> %0,1639 i16 -3,1640 iXLen %1)1641 1642 ret <vscale x 1 x i1> %a1643}1644 1645define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1646; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:1647; CHECK: # %bb.0: # %entry1648; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1649; CHECK-NEXT: vmv1r.v v10, v01650; CHECK-NEXT: vmv1r.v v0, v91651; CHECK-NEXT: vmsle.vi v10, v8, -3, v0.t1652; CHECK-NEXT: vmv1r.v v0, v101653; CHECK-NEXT: ret1654entry:1655 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(1656 <vscale x 1 x i1> %0,1657 <vscale x 1 x i16> %1,1658 i16 -2,1659 <vscale x 1 x i1> %2,1660 iXLen %3)1661 1662 ret <vscale x 1 x i1> %a1663}1664 1665define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1666; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16:1667; CHECK: # %bb.0: # %entry1668; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1669; CHECK-NEXT: vmsle.vi v0, v8, -21670; CHECK-NEXT: ret1671entry:1672 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(1673 <vscale x 2 x i16> %0,1674 i16 -1,1675 iXLen %1)1676 1677 ret <vscale x 2 x i1> %a1678}1679 1680define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1681; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:1682; CHECK: # %bb.0: # %entry1683; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1684; CHECK-NEXT: vmv1r.v v10, v01685; CHECK-NEXT: vmv1r.v v0, v91686; CHECK-NEXT: vmslt.vx v10, v8, zero, v0.t1687; CHECK-NEXT: vmv1r.v v0, v101688; CHECK-NEXT: ret1689entry:1690 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(1691 <vscale x 2 x i1> %0,1692 <vscale x 2 x i16> %1,1693 i16 0,1694 <vscale x 2 x i1> %2,1695 iXLen %3)1696 1697 ret <vscale x 2 x i1> %a1698}1699 1700define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1701; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16:1702; CHECK: # %bb.0: # %entry1703; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1704; CHECK-NEXT: vmslt.vx v0, v8, zero1705; CHECK-NEXT: ret1706entry:1707 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(1708 <vscale x 4 x i16> %0,1709 i16 0,1710 iXLen %1)1711 1712 ret <vscale x 4 x i1> %a1713}1714 1715define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1716; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:1717; CHECK: # %bb.0: # %entry1718; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1719; CHECK-NEXT: vmv1r.v v10, v01720; CHECK-NEXT: vmv1r.v v0, v91721; CHECK-NEXT: vmsle.vi v10, v8, 0, v0.t1722; CHECK-NEXT: vmv.v.v v0, v101723; CHECK-NEXT: ret1724entry:1725 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(1726 <vscale x 4 x i1> %0,1727 <vscale x 4 x i16> %1,1728 i16 1,1729 <vscale x 4 x i1> %2,1730 iXLen %3)1731 1732 ret <vscale x 4 x i1> %a1733}1734 1735define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1736; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16:1737; CHECK: # %bb.0: # %entry1738; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1739; CHECK-NEXT: vmsle.vi v0, v8, 11740; CHECK-NEXT: ret1741entry:1742 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(1743 <vscale x 8 x i16> %0,1744 i16 2,1745 iXLen %1)1746 1747 ret <vscale x 8 x i1> %a1748}1749 1750define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1751; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:1752; CHECK: # %bb.0: # %entry1753; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1754; CHECK-NEXT: vmv1r.v v11, v01755; CHECK-NEXT: vmv1r.v v0, v101756; CHECK-NEXT: vmsle.vi v11, v8, 2, v0.t1757; CHECK-NEXT: vmv1r.v v0, v111758; CHECK-NEXT: ret1759entry:1760 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(1761 <vscale x 8 x i1> %0,1762 <vscale x 8 x i16> %1,1763 i16 3,1764 <vscale x 8 x i1> %2,1765 iXLen %3)1766 1767 ret <vscale x 8 x i1> %a1768}1769 1770define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1771; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16:1772; CHECK: # %bb.0: # %entry1773; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1774; CHECK-NEXT: vmsle.vi v0, v8, 31775; CHECK-NEXT: ret1776entry:1777 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(1778 <vscale x 16 x i16> %0,1779 i16 4,1780 iXLen %1)1781 1782 ret <vscale x 16 x i1> %a1783}1784 1785define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1786; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:1787; CHECK: # %bb.0: # %entry1788; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1789; CHECK-NEXT: vmv1r.v v13, v01790; CHECK-NEXT: vmv1r.v v0, v121791; CHECK-NEXT: vmsle.vi v13, v8, 4, v0.t1792; CHECK-NEXT: vmv1r.v v0, v131793; CHECK-NEXT: ret1794entry:1795 %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(1796 <vscale x 16 x i1> %0,1797 <vscale x 16 x i16> %1,1798 i16 5,1799 <vscale x 16 x i1> %2,1800 iXLen %3)1801 1802 ret <vscale x 16 x i1> %a1803}1804 1805define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {1806; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32:1807; CHECK: # %bb.0: # %entry1808; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1809; CHECK-NEXT: vmsle.vi v0, v8, 51810; CHECK-NEXT: ret1811entry:1812 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(1813 <vscale x 1 x i32> %0,1814 i32 6,1815 iXLen %1)1816 1817 ret <vscale x 1 x i1> %a1818}1819 1820define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1821; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:1822; CHECK: # %bb.0: # %entry1823; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1824; CHECK-NEXT: vmv1r.v v10, v01825; CHECK-NEXT: vmv1r.v v0, v91826; CHECK-NEXT: vmsle.vi v10, v8, 6, v0.t1827; CHECK-NEXT: vmv1r.v v0, v101828; CHECK-NEXT: ret1829entry:1830 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(1831 <vscale x 1 x i1> %0,1832 <vscale x 1 x i32> %1,1833 i32 7,1834 <vscale x 1 x i1> %2,1835 iXLen %3)1836 1837 ret <vscale x 1 x i1> %a1838}1839 1840define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {1841; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32:1842; CHECK: # %bb.0: # %entry1843; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1844; CHECK-NEXT: vmsle.vi v0, v8, 71845; CHECK-NEXT: ret1846entry:1847 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(1848 <vscale x 2 x i32> %0,1849 i32 8,1850 iXLen %1)1851 1852 ret <vscale x 2 x i1> %a1853}1854 1855define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1856; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:1857; CHECK: # %bb.0: # %entry1858; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1859; CHECK-NEXT: vmv1r.v v10, v01860; CHECK-NEXT: vmv1r.v v0, v91861; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t1862; CHECK-NEXT: vmv.v.v v0, v101863; CHECK-NEXT: ret1864entry:1865 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(1866 <vscale x 2 x i1> %0,1867 <vscale x 2 x i32> %1,1868 i32 9,1869 <vscale x 2 x i1> %2,1870 iXLen %3)1871 1872 ret <vscale x 2 x i1> %a1873}1874 1875define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {1876; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32:1877; CHECK: # %bb.0: # %entry1878; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1879; CHECK-NEXT: vmsle.vi v0, v8, 91880; CHECK-NEXT: ret1881entry:1882 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(1883 <vscale x 4 x i32> %0,1884 i32 10,1885 iXLen %1)1886 1887 ret <vscale x 4 x i1> %a1888}1889 1890define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1891; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:1892; CHECK: # %bb.0: # %entry1893; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1894; CHECK-NEXT: vmv1r.v v11, v01895; CHECK-NEXT: vmv1r.v v0, v101896; CHECK-NEXT: vmsle.vi v11, v8, 10, v0.t1897; CHECK-NEXT: vmv1r.v v0, v111898; CHECK-NEXT: ret1899entry:1900 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(1901 <vscale x 4 x i1> %0,1902 <vscale x 4 x i32> %1,1903 i32 11,1904 <vscale x 4 x i1> %2,1905 iXLen %3)1906 1907 ret <vscale x 4 x i1> %a1908}1909 1910define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {1911; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32:1912; CHECK: # %bb.0: # %entry1913; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1914; CHECK-NEXT: vmsle.vi v0, v8, 111915; CHECK-NEXT: ret1916entry:1917 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(1918 <vscale x 8 x i32> %0,1919 i32 12,1920 iXLen %1)1921 1922 ret <vscale x 8 x i1> %a1923}1924 1925define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1926; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:1927; CHECK: # %bb.0: # %entry1928; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1929; CHECK-NEXT: vmv1r.v v13, v01930; CHECK-NEXT: vmv1r.v v0, v121931; CHECK-NEXT: vmsle.vi v13, v8, 12, v0.t1932; CHECK-NEXT: vmv1r.v v0, v131933; CHECK-NEXT: ret1934entry:1935 %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(1936 <vscale x 8 x i1> %0,1937 <vscale x 8 x i32> %1,1938 i32 13,1939 <vscale x 8 x i1> %2,1940 iXLen %3)1941 1942 ret <vscale x 8 x i1> %a1943}1944 1945define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {1946; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64:1947; CHECK: # %bb.0: # %entry1948; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1949; CHECK-NEXT: vmsle.vi v0, v8, 81950; CHECK-NEXT: ret1951entry:1952 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(1953 <vscale x 1 x i64> %0,1954 i64 9,1955 iXLen %1)1956 1957 ret <vscale x 1 x i1> %a1958}1959 1960define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1961; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64:1962; CHECK: # %bb.0: # %entry1963; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu1964; CHECK-NEXT: vmv1r.v v10, v01965; CHECK-NEXT: vmv1r.v v0, v91966; CHECK-NEXT: vmsle.vi v10, v8, 8, v0.t1967; CHECK-NEXT: vmv.v.v v0, v101968; CHECK-NEXT: ret1969entry:1970 %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(1971 <vscale x 1 x i1> %0,1972 <vscale x 1 x i64> %1,1973 i64 9,1974 <vscale x 1 x i1> %2,1975 iXLen %3)1976 1977 ret <vscale x 1 x i1> %a1978}1979 1980define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {1981; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64:1982; CHECK: # %bb.0: # %entry1983; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1984; CHECK-NEXT: vmsle.vi v0, v8, 81985; CHECK-NEXT: ret1986entry:1987 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(1988 <vscale x 2 x i64> %0,1989 i64 9,1990 iXLen %1)1991 1992 ret <vscale x 2 x i1> %a1993}1994 1995define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1996; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64:1997; CHECK: # %bb.0: # %entry1998; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu1999; CHECK-NEXT: vmv1r.v v11, v02000; CHECK-NEXT: vmv1r.v v0, v102001; CHECK-NEXT: vmsle.vi v11, v8, 8, v0.t2002; CHECK-NEXT: vmv1r.v v0, v112003; CHECK-NEXT: ret2004entry:2005 %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(2006 <vscale x 2 x i1> %0,2007 <vscale x 2 x i64> %1,2008 i64 9,2009 <vscale x 2 x i1> %2,2010 iXLen %3)2011 2012 ret <vscale x 2 x i1> %a2013}2014 2015define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2016; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64:2017; CHECK: # %bb.0: # %entry2018; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma2019; CHECK-NEXT: vmsle.vi v0, v8, 82020; CHECK-NEXT: ret2021entry:2022 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(2023 <vscale x 4 x i64> %0,2024 i64 9,2025 iXLen %1)2026 2027 ret <vscale x 4 x i1> %a2028}2029 2030define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2031; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64:2032; CHECK: # %bb.0: # %entry2033; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu2034; CHECK-NEXT: vmv1r.v v13, v02035; CHECK-NEXT: vmv1r.v v0, v122036; CHECK-NEXT: vmsle.vi v13, v8, 8, v0.t2037; CHECK-NEXT: vmv1r.v v0, v132038; CHECK-NEXT: ret2039entry:2040 %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(2041 <vscale x 4 x i1> %0,2042 <vscale x 4 x i64> %1,2043 i64 9,2044 <vscale x 4 x i1> %2,2045 iXLen %3)2046 2047 ret <vscale x 4 x i1> %a2048}2049