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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vmsof.m v8, v012; CHECK-NEXT: vmv1r.v v0, v813; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(16 <vscale x 1 x i1> %0,17 iXLen %1)18 ret <vscale x 1 x i1> %a19}20 21define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {22; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu25; CHECK-NEXT: vmv1r.v v10, v026; CHECK-NEXT: vmv1r.v v0, v927; CHECK-NEXT: vmsof.m v10, v8, v0.t28; CHECK-NEXT: vmv1r.v v0, v1029; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(32 <vscale x 1 x i1> %0,33 <vscale x 1 x i1> %1,34 <vscale x 1 x i1> %2,35 iXLen %3)36 ret <vscale x 1 x i1> %a37}38 39define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma43; CHECK-NEXT: vmsof.m v8, v044; CHECK-NEXT: vmv1r.v v0, v845; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(48 <vscale x 2 x i1> %0,49 iXLen %1)50 ret <vscale x 2 x i1> %a51}52 53define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {54; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu57; CHECK-NEXT: vmv1r.v v10, v058; CHECK-NEXT: vmv1r.v v0, v959; CHECK-NEXT: vmsof.m v10, v8, v0.t60; CHECK-NEXT: vmv1r.v v0, v1061; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(64 <vscale x 2 x i1> %0,65 <vscale x 2 x i1> %1,66 <vscale x 2 x i1> %2,67 iXLen %3)68 ret <vscale x 2 x i1> %a69}70 71define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma75; CHECK-NEXT: vmsof.m v8, v076; CHECK-NEXT: vmv1r.v v0, v877; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(80 <vscale x 4 x i1> %0,81 iXLen %1)82 ret <vscale x 4 x i1> %a83}84 85define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {86; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu89; CHECK-NEXT: vmv1r.v v10, v090; CHECK-NEXT: vmv1r.v v0, v991; CHECK-NEXT: vmsof.m v10, v8, v0.t92; CHECK-NEXT: vmv1r.v v0, v1093; CHECK-NEXT: ret94entry:95 %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(96 <vscale x 4 x i1> %0,97 <vscale x 4 x i1> %1,98 <vscale x 4 x i1> %2,99 iXLen %3)100 ret <vscale x 4 x i1> %a101}102 103define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma107; CHECK-NEXT: vmsof.m v8, v0108; CHECK-NEXT: vmv.v.v v0, v8109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(112 <vscale x 8 x i1> %0,113 iXLen %1)114 ret <vscale x 8 x i1> %a115}116 117define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {118; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu121; CHECK-NEXT: vmv1r.v v10, v0122; CHECK-NEXT: vmv1r.v v0, v9123; CHECK-NEXT: vmsof.m v10, v8, v0.t124; CHECK-NEXT: vmv.v.v v0, v10125; CHECK-NEXT: ret126entry:127 %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(128 <vscale x 8 x i1> %0,129 <vscale x 8 x i1> %1,130 <vscale x 8 x i1> %2,131 iXLen %3)132 ret <vscale x 8 x i1> %a133}134 135define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma139; CHECK-NEXT: vmsof.m v8, v0140; CHECK-NEXT: vmv1r.v v0, v8141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(144 <vscale x 16 x i1> %0,145 iXLen %1)146 ret <vscale x 16 x i1> %a147}148 149define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {150; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:151; CHECK: # %bb.0: # %entry152; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu153; CHECK-NEXT: vmv1r.v v10, v0154; CHECK-NEXT: vmv1r.v v0, v9155; CHECK-NEXT: vmsof.m v10, v8, v0.t156; CHECK-NEXT: vmv1r.v v0, v10157; CHECK-NEXT: ret158entry:159 %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(160 <vscale x 16 x i1> %0,161 <vscale x 16 x i1> %1,162 <vscale x 16 x i1> %2,163 iXLen %3)164 ret <vscale x 16 x i1> %a165}166 167define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {168; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma171; CHECK-NEXT: vmsof.m v8, v0172; CHECK-NEXT: vmv1r.v v0, v8173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(176 <vscale x 32 x i1> %0,177 iXLen %1)178 ret <vscale x 32 x i1> %a179}180 181define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {182; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu185; CHECK-NEXT: vmv1r.v v10, v0186; CHECK-NEXT: vmv1r.v v0, v9187; CHECK-NEXT: vmsof.m v10, v8, v0.t188; CHECK-NEXT: vmv1r.v v0, v10189; CHECK-NEXT: ret190entry:191 %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(192 <vscale x 32 x i1> %0,193 <vscale x 32 x i1> %1,194 <vscale x 32 x i1> %2,195 iXLen %3)196 ret <vscale x 32 x i1> %a197}198 199define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {200; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma203; CHECK-NEXT: vmsof.m v8, v0204; CHECK-NEXT: vmv1r.v v0, v8205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(208 <vscale x 64 x i1> %0,209 iXLen %1)210 ret <vscale x 64 x i1> %a211}212 213define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {214; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu217; CHECK-NEXT: vmv1r.v v10, v0218; CHECK-NEXT: vmv1r.v v0, v9219; CHECK-NEXT: vmsof.m v10, v8, v0.t220; CHECK-NEXT: vmv1r.v v0, v10221; CHECK-NEXT: ret222entry:223 %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(224 <vscale x 64 x i1> %0,225 <vscale x 64 x i1> %1,226 <vscale x 64 x i1> %2,227 iXLen %3)228 ret <vscale x 64 x i1> %a229}230