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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32NOM3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM4 5; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32M6; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M7 8define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {9; CHECK-LABEL: vmul_vv_nxv1i8:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma12; CHECK-NEXT: vmul.vv v8, v8, v913; CHECK-NEXT: ret14 %vc = mul <vscale x 1 x i8> %va, %vb15 ret <vscale x 1 x i8> %vc16}17 18define <vscale x 1 x i8> @vmul_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {19; CHECK-LABEL: vmul_vx_nxv1i8:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma22; CHECK-NEXT: vmul.vx v8, v8, a023; CHECK-NEXT: ret24 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 025 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer26 %vc = mul <vscale x 1 x i8> %va, %splat27 ret <vscale x 1 x i8> %vc28}29 30define <vscale x 1 x i8> @vmul_vi_nxv1i8_0(<vscale x 1 x i8> %va) {31; CHECK-LABEL: vmul_vi_nxv1i8_0:32; CHECK: # %bb.0:33; CHECK-NEXT: li a0, -734; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma35; CHECK-NEXT: vmul.vx v8, v8, a036; CHECK-NEXT: ret37 %vc = mul <vscale x 1 x i8> %va, splat (i8 -7)38 ret <vscale x 1 x i8> %vc39}40 41define <vscale x 2 x i8> @vmul_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {42; CHECK-LABEL: vmul_vv_nxv2i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma45; CHECK-NEXT: vmul.vv v8, v8, v946; CHECK-NEXT: ret47 %vc = mul <vscale x 2 x i8> %va, %vb48 ret <vscale x 2 x i8> %vc49}50 51define <vscale x 2 x i8> @vmul_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {52; CHECK-LABEL: vmul_vx_nxv2i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma55; CHECK-NEXT: vmul.vx v8, v8, a056; CHECK-NEXT: ret57 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 058 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer59 %vc = mul <vscale x 2 x i8> %va, %splat60 ret <vscale x 2 x i8> %vc61}62 63define <vscale x 2 x i8> @vmul_vi_nxv2i8_0(<vscale x 2 x i8> %va) {64; CHECK-LABEL: vmul_vi_nxv2i8_0:65; CHECK: # %bb.0:66; CHECK-NEXT: li a0, -767; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma68; CHECK-NEXT: vmul.vx v8, v8, a069; CHECK-NEXT: ret70 %vc = mul <vscale x 2 x i8> %va, splat (i8 -7)71 ret <vscale x 2 x i8> %vc72}73 74define <vscale x 4 x i8> @vmul_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {75; CHECK-LABEL: vmul_vv_nxv4i8:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma78; CHECK-NEXT: vmul.vv v8, v8, v979; CHECK-NEXT: ret80 %vc = mul <vscale x 4 x i8> %va, %vb81 ret <vscale x 4 x i8> %vc82}83 84define <vscale x 4 x i8> @vmul_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {85; CHECK-LABEL: vmul_vx_nxv4i8:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma88; CHECK-NEXT: vmul.vx v8, v8, a089; CHECK-NEXT: ret90 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 091 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer92 %vc = mul <vscale x 4 x i8> %va, %splat93 ret <vscale x 4 x i8> %vc94}95 96define <vscale x 4 x i8> @vmul_vi_nxv4i8_0(<vscale x 4 x i8> %va) {97; CHECK-LABEL: vmul_vi_nxv4i8_0:98; CHECK: # %bb.0:99; CHECK-NEXT: li a0, -7100; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma101; CHECK-NEXT: vmul.vx v8, v8, a0102; CHECK-NEXT: ret103 %vc = mul <vscale x 4 x i8> %va, splat (i8 -7)104 ret <vscale x 4 x i8> %vc105}106 107define <vscale x 8 x i8> @vmul_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {108; CHECK-LABEL: vmul_vv_nxv8i8:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma111; CHECK-NEXT: vmul.vv v8, v8, v9112; CHECK-NEXT: ret113 %vc = mul <vscale x 8 x i8> %va, %vb114 ret <vscale x 8 x i8> %vc115}116 117define <vscale x 8 x i8> @vmul_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {118; CHECK-LABEL: vmul_vx_nxv8i8:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma121; CHECK-NEXT: vmul.vx v8, v8, a0122; CHECK-NEXT: ret123 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0124 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer125 %vc = mul <vscale x 8 x i8> %va, %splat126 ret <vscale x 8 x i8> %vc127}128 129define <vscale x 8 x i8> @vmul_vi_nxv8i8_0(<vscale x 8 x i8> %va) {130; CHECK-LABEL: vmul_vi_nxv8i8_0:131; CHECK: # %bb.0:132; CHECK-NEXT: li a0, -7133; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma134; CHECK-NEXT: vmul.vx v8, v8, a0135; CHECK-NEXT: ret136 %vc = mul <vscale x 8 x i8> %va, splat (i8 -7)137 ret <vscale x 8 x i8> %vc138}139 140define <vscale x 16 x i8> @vmul_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {141; CHECK-LABEL: vmul_vv_nxv16i8:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma144; CHECK-NEXT: vmul.vv v8, v8, v10145; CHECK-NEXT: ret146 %vc = mul <vscale x 16 x i8> %va, %vb147 ret <vscale x 16 x i8> %vc148}149 150define <vscale x 16 x i8> @vmul_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {151; CHECK-LABEL: vmul_vx_nxv16i8:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma154; CHECK-NEXT: vmul.vx v8, v8, a0155; CHECK-NEXT: ret156 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0157 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer158 %vc = mul <vscale x 16 x i8> %va, %splat159 ret <vscale x 16 x i8> %vc160}161 162define <vscale x 16 x i8> @vmul_vi_nxv16i8_0(<vscale x 16 x i8> %va) {163; CHECK-LABEL: vmul_vi_nxv16i8_0:164; CHECK: # %bb.0:165; CHECK-NEXT: li a0, -7166; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma167; CHECK-NEXT: vmul.vx v8, v8, a0168; CHECK-NEXT: ret169 %vc = mul <vscale x 16 x i8> %va, splat (i8 -7)170 ret <vscale x 16 x i8> %vc171}172 173define <vscale x 32 x i8> @vmul_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {174; CHECK-LABEL: vmul_vv_nxv32i8:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma177; CHECK-NEXT: vmul.vv v8, v8, v12178; CHECK-NEXT: ret179 %vc = mul <vscale x 32 x i8> %va, %vb180 ret <vscale x 32 x i8> %vc181}182 183define <vscale x 32 x i8> @vmul_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {184; CHECK-LABEL: vmul_vx_nxv32i8:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma187; CHECK-NEXT: vmul.vx v8, v8, a0188; CHECK-NEXT: ret189 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0190 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer191 %vc = mul <vscale x 32 x i8> %va, %splat192 ret <vscale x 32 x i8> %vc193}194 195define <vscale x 32 x i8> @vmul_vi_nxv32i8_0(<vscale x 32 x i8> %va) {196; CHECK-LABEL: vmul_vi_nxv32i8_0:197; CHECK: # %bb.0:198; CHECK-NEXT: li a0, -7199; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma200; CHECK-NEXT: vmul.vx v8, v8, a0201; CHECK-NEXT: ret202 %vc = mul <vscale x 32 x i8> %va, splat (i8 -7)203 ret <vscale x 32 x i8> %vc204}205 206define <vscale x 64 x i8> @vmul_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {207; CHECK-LABEL: vmul_vv_nxv64i8:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma210; CHECK-NEXT: vmul.vv v8, v8, v16211; CHECK-NEXT: ret212 %vc = mul <vscale x 64 x i8> %va, %vb213 ret <vscale x 64 x i8> %vc214}215 216define <vscale x 64 x i8> @vmul_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {217; CHECK-LABEL: vmul_vx_nxv64i8:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma220; CHECK-NEXT: vmul.vx v8, v8, a0221; CHECK-NEXT: ret222 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0223 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer224 %vc = mul <vscale x 64 x i8> %va, %splat225 ret <vscale x 64 x i8> %vc226}227 228define <vscale x 64 x i8> @vmul_vi_nxv64i8_0(<vscale x 64 x i8> %va) {229; CHECK-LABEL: vmul_vi_nxv64i8_0:230; CHECK: # %bb.0:231; CHECK-NEXT: li a0, -7232; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma233; CHECK-NEXT: vmul.vx v8, v8, a0234; CHECK-NEXT: ret235 %vc = mul <vscale x 64 x i8> %va, splat (i8 -7)236 ret <vscale x 64 x i8> %vc237}238 239define <vscale x 1 x i16> @vmul_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {240; CHECK-LABEL: vmul_vv_nxv1i16:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma243; CHECK-NEXT: vmul.vv v8, v8, v9244; CHECK-NEXT: ret245 %vc = mul <vscale x 1 x i16> %va, %vb246 ret <vscale x 1 x i16> %vc247}248 249define <vscale x 1 x i16> @vmul_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {250; CHECK-LABEL: vmul_vx_nxv1i16:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma253; CHECK-NEXT: vmul.vx v8, v8, a0254; CHECK-NEXT: ret255 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0256 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer257 %vc = mul <vscale x 1 x i16> %va, %splat258 ret <vscale x 1 x i16> %vc259}260 261define <vscale x 1 x i16> @vmul_vi_nxv1i16_0(<vscale x 1 x i16> %va) {262; CHECK-LABEL: vmul_vi_nxv1i16_0:263; CHECK: # %bb.0:264; CHECK-NEXT: li a0, -7265; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma266; CHECK-NEXT: vmul.vx v8, v8, a0267; CHECK-NEXT: ret268 %vc = mul <vscale x 1 x i16> %va, splat (i16 -7)269 ret <vscale x 1 x i16> %vc270}271 272define <vscale x 2 x i16> @vmul_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {273; CHECK-LABEL: vmul_vv_nxv2i16:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma276; CHECK-NEXT: vmul.vv v8, v8, v9277; CHECK-NEXT: ret278 %vc = mul <vscale x 2 x i16> %va, %vb279 ret <vscale x 2 x i16> %vc280}281 282define <vscale x 2 x i16> @vmul_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {283; CHECK-LABEL: vmul_vx_nxv2i16:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma286; CHECK-NEXT: vmul.vx v8, v8, a0287; CHECK-NEXT: ret288 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0289 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer290 %vc = mul <vscale x 2 x i16> %va, %splat291 ret <vscale x 2 x i16> %vc292}293 294define <vscale x 2 x i16> @vmul_vi_nxv2i16_0(<vscale x 2 x i16> %va) {295; CHECK-LABEL: vmul_vi_nxv2i16_0:296; CHECK: # %bb.0:297; CHECK-NEXT: li a0, -7298; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma299; CHECK-NEXT: vmul.vx v8, v8, a0300; CHECK-NEXT: ret301 %vc = mul <vscale x 2 x i16> %va, splat (i16 -7)302 ret <vscale x 2 x i16> %vc303}304 305define <vscale x 4 x i16> @vmul_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {306; CHECK-LABEL: vmul_vv_nxv4i16:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma309; CHECK-NEXT: vmul.vv v8, v8, v9310; CHECK-NEXT: ret311 %vc = mul <vscale x 4 x i16> %va, %vb312 ret <vscale x 4 x i16> %vc313}314 315define <vscale x 4 x i16> @vmul_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {316; CHECK-LABEL: vmul_vx_nxv4i16:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma319; CHECK-NEXT: vmul.vx v8, v8, a0320; CHECK-NEXT: ret321 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0322 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer323 %vc = mul <vscale x 4 x i16> %va, %splat324 ret <vscale x 4 x i16> %vc325}326 327define <vscale x 4 x i16> @vmul_vi_nxv4i16_0(<vscale x 4 x i16> %va) {328; CHECK-LABEL: vmul_vi_nxv4i16_0:329; CHECK: # %bb.0:330; CHECK-NEXT: li a0, -7331; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma332; CHECK-NEXT: vmul.vx v8, v8, a0333; CHECK-NEXT: ret334 %vc = mul <vscale x 4 x i16> %va, splat (i16 -7)335 ret <vscale x 4 x i16> %vc336}337 338define <vscale x 8 x i16> @vmul_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {339; CHECK-LABEL: vmul_vv_nxv8i16:340; CHECK: # %bb.0:341; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma342; CHECK-NEXT: vmul.vv v8, v8, v10343; CHECK-NEXT: ret344 %vc = mul <vscale x 8 x i16> %va, %vb345 ret <vscale x 8 x i16> %vc346}347 348define <vscale x 8 x i16> @vmul_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {349; CHECK-LABEL: vmul_vx_nxv8i16:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma352; CHECK-NEXT: vmul.vx v8, v8, a0353; CHECK-NEXT: ret354 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0355 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer356 %vc = mul <vscale x 8 x i16> %va, %splat357 ret <vscale x 8 x i16> %vc358}359 360define <vscale x 8 x i16> @vmul_vi_nxv8i16_0(<vscale x 8 x i16> %va) {361; CHECK-LABEL: vmul_vi_nxv8i16_0:362; CHECK: # %bb.0:363; CHECK-NEXT: li a0, -7364; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma365; CHECK-NEXT: vmul.vx v8, v8, a0366; CHECK-NEXT: ret367 %vc = mul <vscale x 8 x i16> %va, splat (i16 -7)368 ret <vscale x 8 x i16> %vc369}370 371define <vscale x 16 x i16> @vmul_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {372; CHECK-LABEL: vmul_vv_nxv16i16:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma375; CHECK-NEXT: vmul.vv v8, v8, v12376; CHECK-NEXT: ret377 %vc = mul <vscale x 16 x i16> %va, %vb378 ret <vscale x 16 x i16> %vc379}380 381define <vscale x 16 x i16> @vmul_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {382; CHECK-LABEL: vmul_vx_nxv16i16:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma385; CHECK-NEXT: vmul.vx v8, v8, a0386; CHECK-NEXT: ret387 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0388 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer389 %vc = mul <vscale x 16 x i16> %va, %splat390 ret <vscale x 16 x i16> %vc391}392 393define <vscale x 16 x i16> @vmul_vi_nxv16i16_0(<vscale x 16 x i16> %va) {394; CHECK-LABEL: vmul_vi_nxv16i16_0:395; CHECK: # %bb.0:396; CHECK-NEXT: li a0, -7397; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma398; CHECK-NEXT: vmul.vx v8, v8, a0399; CHECK-NEXT: ret400 %vc = mul <vscale x 16 x i16> %va, splat (i16 -7)401 ret <vscale x 16 x i16> %vc402}403 404define <vscale x 32 x i16> @vmul_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {405; CHECK-LABEL: vmul_vv_nxv32i16:406; CHECK: # %bb.0:407; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma408; CHECK-NEXT: vmul.vv v8, v8, v16409; CHECK-NEXT: ret410 %vc = mul <vscale x 32 x i16> %va, %vb411 ret <vscale x 32 x i16> %vc412}413 414define <vscale x 32 x i16> @vmul_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {415; CHECK-LABEL: vmul_vx_nxv32i16:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma418; CHECK-NEXT: vmul.vx v8, v8, a0419; CHECK-NEXT: ret420 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0421 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer422 %vc = mul <vscale x 32 x i16> %va, %splat423 ret <vscale x 32 x i16> %vc424}425 426define <vscale x 32 x i16> @vmul_vi_nxv32i16_0(<vscale x 32 x i16> %va) {427; CHECK-LABEL: vmul_vi_nxv32i16_0:428; CHECK: # %bb.0:429; CHECK-NEXT: li a0, -7430; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma431; CHECK-NEXT: vmul.vx v8, v8, a0432; CHECK-NEXT: ret433 %vc = mul <vscale x 32 x i16> %va, splat (i16 -7)434 ret <vscale x 32 x i16> %vc435}436 437define <vscale x 1 x i32> @vmul_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {438; CHECK-LABEL: vmul_vv_nxv1i32:439; CHECK: # %bb.0:440; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma441; CHECK-NEXT: vmul.vv v8, v8, v9442; CHECK-NEXT: ret443 %vc = mul <vscale x 1 x i32> %va, %vb444 ret <vscale x 1 x i32> %vc445}446 447define <vscale x 1 x i32> @vmul_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {448; CHECK-LABEL: vmul_vx_nxv1i32:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma451; CHECK-NEXT: vmul.vx v8, v8, a0452; CHECK-NEXT: ret453 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0454 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer455 %vc = mul <vscale x 1 x i32> %va, %splat456 ret <vscale x 1 x i32> %vc457}458 459define <vscale x 1 x i32> @vmul_vi_nxv1i32_0(<vscale x 1 x i32> %va) {460; CHECK-LABEL: vmul_vi_nxv1i32_0:461; CHECK: # %bb.0:462; CHECK-NEXT: li a0, -7463; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma464; CHECK-NEXT: vmul.vx v8, v8, a0465; CHECK-NEXT: ret466 %vc = mul <vscale x 1 x i32> %va, splat (i32 -7)467 ret <vscale x 1 x i32> %vc468}469 470define <vscale x 2 x i32> @vmul_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {471; CHECK-LABEL: vmul_vv_nxv2i32:472; CHECK: # %bb.0:473; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma474; CHECK-NEXT: vmul.vv v8, v8, v9475; CHECK-NEXT: ret476 %vc = mul <vscale x 2 x i32> %va, %vb477 ret <vscale x 2 x i32> %vc478}479 480define <vscale x 2 x i32> @vmul_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {481; CHECK-LABEL: vmul_vx_nxv2i32:482; CHECK: # %bb.0:483; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma484; CHECK-NEXT: vmul.vx v8, v8, a0485; CHECK-NEXT: ret486 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0487 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer488 %vc = mul <vscale x 2 x i32> %va, %splat489 ret <vscale x 2 x i32> %vc490}491 492define <vscale x 2 x i32> @vmul_vi_nxv2i32_0(<vscale x 2 x i32> %va) {493; CHECK-LABEL: vmul_vi_nxv2i32_0:494; CHECK: # %bb.0:495; CHECK-NEXT: li a0, -7496; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma497; CHECK-NEXT: vmul.vx v8, v8, a0498; CHECK-NEXT: ret499 %vc = mul <vscale x 2 x i32> %va, splat (i32 -7)500 ret <vscale x 2 x i32> %vc501}502 503define <vscale x 4 x i32> @vmul_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {504; CHECK-LABEL: vmul_vv_nxv4i32:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma507; CHECK-NEXT: vmul.vv v8, v8, v10508; CHECK-NEXT: ret509 %vc = mul <vscale x 4 x i32> %va, %vb510 ret <vscale x 4 x i32> %vc511}512 513define <vscale x 4 x i32> @vmul_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {514; CHECK-LABEL: vmul_vx_nxv4i32:515; CHECK: # %bb.0:516; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma517; CHECK-NEXT: vmul.vx v8, v8, a0518; CHECK-NEXT: ret519 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0520 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer521 %vc = mul <vscale x 4 x i32> %va, %splat522 ret <vscale x 4 x i32> %vc523}524 525define <vscale x 4 x i32> @vmul_vi_nxv4i32_0(<vscale x 4 x i32> %va) {526; CHECK-LABEL: vmul_vi_nxv4i32_0:527; CHECK: # %bb.0:528; CHECK-NEXT: li a0, -7529; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma530; CHECK-NEXT: vmul.vx v8, v8, a0531; CHECK-NEXT: ret532 %vc = mul <vscale x 4 x i32> %va, splat (i32 -7)533 ret <vscale x 4 x i32> %vc534}535 536define <vscale x 8 x i32> @vmul_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {537; CHECK-LABEL: vmul_vv_nxv8i32:538; CHECK: # %bb.0:539; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma540; CHECK-NEXT: vmul.vv v8, v8, v12541; CHECK-NEXT: ret542 %vc = mul <vscale x 8 x i32> %va, %vb543 ret <vscale x 8 x i32> %vc544}545 546define <vscale x 8 x i32> @vmul_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {547; CHECK-LABEL: vmul_vx_nxv8i32:548; CHECK: # %bb.0:549; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma550; CHECK-NEXT: vmul.vx v8, v8, a0551; CHECK-NEXT: ret552 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0553 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer554 %vc = mul <vscale x 8 x i32> %va, %splat555 ret <vscale x 8 x i32> %vc556}557 558define <vscale x 8 x i32> @vmul_vi_nxv8i32_0(<vscale x 8 x i32> %va) {559; CHECK-LABEL: vmul_vi_nxv8i32_0:560; CHECK: # %bb.0:561; CHECK-NEXT: li a0, -7562; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma563; CHECK-NEXT: vmul.vx v8, v8, a0564; CHECK-NEXT: ret565 %vc = mul <vscale x 8 x i32> %va, splat (i32 -7)566 ret <vscale x 8 x i32> %vc567}568 569define <vscale x 16 x i32> @vmul_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {570; CHECK-LABEL: vmul_vv_nxv16i32:571; CHECK: # %bb.0:572; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma573; CHECK-NEXT: vmul.vv v8, v8, v16574; CHECK-NEXT: ret575 %vc = mul <vscale x 16 x i32> %va, %vb576 ret <vscale x 16 x i32> %vc577}578 579define <vscale x 16 x i32> @vmul_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {580; CHECK-LABEL: vmul_vx_nxv16i32:581; CHECK: # %bb.0:582; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma583; CHECK-NEXT: vmul.vx v8, v8, a0584; CHECK-NEXT: ret585 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0586 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer587 %vc = mul <vscale x 16 x i32> %va, %splat588 ret <vscale x 16 x i32> %vc589}590 591define <vscale x 16 x i32> @vmul_vi_nxv16i32_0(<vscale x 16 x i32> %va) {592; CHECK-LABEL: vmul_vi_nxv16i32_0:593; CHECK: # %bb.0:594; CHECK-NEXT: li a0, -7595; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma596; CHECK-NEXT: vmul.vx v8, v8, a0597; CHECK-NEXT: ret598 %vc = mul <vscale x 16 x i32> %va, splat (i32 -7)599 ret <vscale x 16 x i32> %vc600}601 602define <vscale x 1 x i64> @vmul_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {603; CHECK-LABEL: vmul_vv_nxv1i64:604; CHECK: # %bb.0:605; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma606; CHECK-NEXT: vmul.vv v8, v8, v9607; CHECK-NEXT: ret608 %vc = mul <vscale x 1 x i64> %va, %vb609 ret <vscale x 1 x i64> %vc610}611 612define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {613; RV32-LABEL: vmul_vx_nxv1i64:614; RV32: # %bb.0:615; RV32-NEXT: addi sp, sp, -16616; RV32-NEXT: .cfi_def_cfa_offset 16617; RV32-NEXT: sw a0, 8(sp)618; RV32-NEXT: sw a1, 12(sp)619; RV32-NEXT: addi a0, sp, 8620; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma621; RV32-NEXT: vlse64.v v9, (a0), zero622; RV32-NEXT: vmul.vv v8, v8, v9623; RV32-NEXT: addi sp, sp, 16624; RV32-NEXT: .cfi_def_cfa_offset 0625; RV32-NEXT: ret626;627; RV64-LABEL: vmul_vx_nxv1i64:628; RV64: # %bb.0:629; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma630; RV64-NEXT: vmul.vx v8, v8, a0631; RV64-NEXT: ret632 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0633 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer634 %vc = mul <vscale x 1 x i64> %va, %splat635 ret <vscale x 1 x i64> %vc636}637 638define <vscale x 1 x i64> @vmul_vi_nxv1i64_0(<vscale x 1 x i64> %va) {639; CHECK-LABEL: vmul_vi_nxv1i64_0:640; CHECK: # %bb.0:641; CHECK-NEXT: li a0, -7642; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma643; CHECK-NEXT: vmul.vx v8, v8, a0644; CHECK-NEXT: ret645 %vc = mul <vscale x 1 x i64> %va, splat (i64 -7)646 ret <vscale x 1 x i64> %vc647}648 649define <vscale x 1 x i64> @vmul_vi_nxv1i64_1(<vscale x 1 x i64> %va) {650; CHECK-LABEL: vmul_vi_nxv1i64_1:651; CHECK: # %bb.0:652; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma653; CHECK-NEXT: vadd.vv v8, v8, v8654; CHECK-NEXT: ret655 %vc = mul <vscale x 1 x i64> %va, splat (i64 2)656 ret <vscale x 1 x i64> %vc657}658 659define <vscale x 1 x i64> @vmul_vi_nxv1i64_2(<vscale x 1 x i64> %va) {660; CHECK-LABEL: vmul_vi_nxv1i64_2:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma663; CHECK-NEXT: vsll.vi v8, v8, 4664; CHECK-NEXT: ret665 %vc = mul <vscale x 1 x i64> %va, splat (i64 16)666 ret <vscale x 1 x i64> %vc667}668 669define <vscale x 2 x i64> @vmul_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {670; CHECK-LABEL: vmul_vv_nxv2i64:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma673; CHECK-NEXT: vmul.vv v8, v8, v10674; CHECK-NEXT: ret675 %vc = mul <vscale x 2 x i64> %va, %vb676 ret <vscale x 2 x i64> %vc677}678 679define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {680; RV32-LABEL: vmul_vx_nxv2i64:681; RV32: # %bb.0:682; RV32-NEXT: addi sp, sp, -16683; RV32-NEXT: .cfi_def_cfa_offset 16684; RV32-NEXT: sw a0, 8(sp)685; RV32-NEXT: sw a1, 12(sp)686; RV32-NEXT: addi a0, sp, 8687; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma688; RV32-NEXT: vlse64.v v10, (a0), zero689; RV32-NEXT: vmul.vv v8, v8, v10690; RV32-NEXT: addi sp, sp, 16691; RV32-NEXT: .cfi_def_cfa_offset 0692; RV32-NEXT: ret693;694; RV64-LABEL: vmul_vx_nxv2i64:695; RV64: # %bb.0:696; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma697; RV64-NEXT: vmul.vx v8, v8, a0698; RV64-NEXT: ret699 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0700 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer701 %vc = mul <vscale x 2 x i64> %va, %splat702 ret <vscale x 2 x i64> %vc703}704 705define <vscale x 2 x i64> @vmul_vi_nxv2i64_0(<vscale x 2 x i64> %va) {706; CHECK-LABEL: vmul_vi_nxv2i64_0:707; CHECK: # %bb.0:708; CHECK-NEXT: li a0, -7709; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma710; CHECK-NEXT: vmul.vx v8, v8, a0711; CHECK-NEXT: ret712 %vc = mul <vscale x 2 x i64> %va, splat (i64 -7)713 ret <vscale x 2 x i64> %vc714}715 716define <vscale x 2 x i64> @vmul_vi_nxv2i64_1(<vscale x 2 x i64> %va) {717; CHECK-LABEL: vmul_vi_nxv2i64_1:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma720; CHECK-NEXT: vadd.vv v8, v8, v8721; CHECK-NEXT: ret722 %vc = mul <vscale x 2 x i64> %va, splat (i64 2)723 ret <vscale x 2 x i64> %vc724}725 726define <vscale x 2 x i64> @vmul_vi_nxv2i64_2(<vscale x 2 x i64> %va) {727; CHECK-LABEL: vmul_vi_nxv2i64_2:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma730; CHECK-NEXT: vsll.vi v8, v8, 4731; CHECK-NEXT: ret732 %vc = mul <vscale x 2 x i64> %va, splat (i64 16)733 ret <vscale x 2 x i64> %vc734}735 736define <vscale x 4 x i64> @vmul_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {737; CHECK-LABEL: vmul_vv_nxv4i64:738; CHECK: # %bb.0:739; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma740; CHECK-NEXT: vmul.vv v8, v8, v12741; CHECK-NEXT: ret742 %vc = mul <vscale x 4 x i64> %va, %vb743 ret <vscale x 4 x i64> %vc744}745 746define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {747; RV32-LABEL: vmul_vx_nxv4i64:748; RV32: # %bb.0:749; RV32-NEXT: addi sp, sp, -16750; RV32-NEXT: .cfi_def_cfa_offset 16751; RV32-NEXT: sw a0, 8(sp)752; RV32-NEXT: sw a1, 12(sp)753; RV32-NEXT: addi a0, sp, 8754; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma755; RV32-NEXT: vlse64.v v12, (a0), zero756; RV32-NEXT: vmul.vv v8, v8, v12757; RV32-NEXT: addi sp, sp, 16758; RV32-NEXT: .cfi_def_cfa_offset 0759; RV32-NEXT: ret760;761; RV64-LABEL: vmul_vx_nxv4i64:762; RV64: # %bb.0:763; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma764; RV64-NEXT: vmul.vx v8, v8, a0765; RV64-NEXT: ret766 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0767 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer768 %vc = mul <vscale x 4 x i64> %va, %splat769 ret <vscale x 4 x i64> %vc770}771 772define <vscale x 4 x i64> @vmul_vi_nxv4i64_0(<vscale x 4 x i64> %va) {773; CHECK-LABEL: vmul_vi_nxv4i64_0:774; CHECK: # %bb.0:775; CHECK-NEXT: li a0, -7776; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma777; CHECK-NEXT: vmul.vx v8, v8, a0778; CHECK-NEXT: ret779 %vc = mul <vscale x 4 x i64> %va, splat (i64 -7)780 ret <vscale x 4 x i64> %vc781}782 783define <vscale x 4 x i64> @vmul_vi_nxv4i64_1(<vscale x 4 x i64> %va) {784; CHECK-LABEL: vmul_vi_nxv4i64_1:785; CHECK: # %bb.0:786; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma787; CHECK-NEXT: vadd.vv v8, v8, v8788; CHECK-NEXT: ret789 %vc = mul <vscale x 4 x i64> %va, splat (i64 2)790 ret <vscale x 4 x i64> %vc791}792 793define <vscale x 4 x i64> @vmul_vi_nxv4i64_2(<vscale x 4 x i64> %va) {794; CHECK-LABEL: vmul_vi_nxv4i64_2:795; CHECK: # %bb.0:796; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma797; CHECK-NEXT: vsll.vi v8, v8, 4798; CHECK-NEXT: ret799 %vc = mul <vscale x 4 x i64> %va, splat (i64 16)800 ret <vscale x 4 x i64> %vc801}802 803define <vscale x 8 x i64> @vmul_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {804; CHECK-LABEL: vmul_vv_nxv8i64:805; CHECK: # %bb.0:806; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma807; CHECK-NEXT: vmul.vv v8, v8, v16808; CHECK-NEXT: ret809 %vc = mul <vscale x 8 x i64> %va, %vb810 ret <vscale x 8 x i64> %vc811}812 813define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {814; RV32-LABEL: vmul_vx_nxv8i64:815; RV32: # %bb.0:816; RV32-NEXT: addi sp, sp, -16817; RV32-NEXT: .cfi_def_cfa_offset 16818; RV32-NEXT: sw a0, 8(sp)819; RV32-NEXT: sw a1, 12(sp)820; RV32-NEXT: addi a0, sp, 8821; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma822; RV32-NEXT: vlse64.v v16, (a0), zero823; RV32-NEXT: vmul.vv v8, v8, v16824; RV32-NEXT: addi sp, sp, 16825; RV32-NEXT: .cfi_def_cfa_offset 0826; RV32-NEXT: ret827;828; RV64-LABEL: vmul_vx_nxv8i64:829; RV64: # %bb.0:830; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma831; RV64-NEXT: vmul.vx v8, v8, a0832; RV64-NEXT: ret833 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0834 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer835 %vc = mul <vscale x 8 x i64> %va, %splat836 ret <vscale x 8 x i64> %vc837}838 839define <vscale x 8 x i64> @vmul_vi_nxv8i64_0(<vscale x 8 x i64> %va) {840; CHECK-LABEL: vmul_vi_nxv8i64_0:841; CHECK: # %bb.0:842; CHECK-NEXT: li a0, -7843; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma844; CHECK-NEXT: vmul.vx v8, v8, a0845; CHECK-NEXT: ret846 %vc = mul <vscale x 8 x i64> %va, splat (i64 -7)847 ret <vscale x 8 x i64> %vc848}849 850define <vscale x 8 x i64> @vmul_vi_nxv8i64_1(<vscale x 8 x i64> %va) {851; CHECK-LABEL: vmul_vi_nxv8i64_1:852; CHECK: # %bb.0:853; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma854; CHECK-NEXT: vadd.vv v8, v8, v8855; CHECK-NEXT: ret856 %vc = mul <vscale x 8 x i64> %va, splat (i64 2)857 ret <vscale x 8 x i64> %vc858}859 860define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {861; CHECK-LABEL: vmul_vi_nxv8i64_2:862; CHECK: # %bb.0:863; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma864; CHECK-NEXT: vsll.vi v8, v8, 4865; CHECK-NEXT: ret866 %vc = mul <vscale x 8 x i64> %va, splat (i64 16)867 ret <vscale x 8 x i64> %vc868}869 870define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {871; RV32NOM-LABEL: vmul_xx_nxv8i64:872; RV32NOM: # %bb.0:873; RV32NOM-NEXT: addi sp, sp, -16874; RV32NOM-NEXT: sw a0, 8(sp)875; RV32NOM-NEXT: sw a1, 12(sp)876; RV32NOM-NEXT: addi a0, sp, 8877; RV32NOM-NEXT: vsetvli a1, zero, e64, m8, ta, ma878; RV32NOM-NEXT: vlse64.v v8, (a0), zero879; RV32NOM-NEXT: sw a2, 0(sp)880; RV32NOM-NEXT: sw a3, 4(sp)881; RV32NOM-NEXT: mv a0, sp882; RV32NOM-NEXT: vlse64.v v16, (a0), zero883; RV32NOM-NEXT: vmul.vv v8, v8, v16884; RV32NOM-NEXT: addi sp, sp, 16885; RV32NOM-NEXT: ret886;887; RV64NOM-LABEL: vmul_xx_nxv8i64:888; RV64NOM: # %bb.0:889; RV64NOM-NEXT: vsetvli a2, zero, e64, m8, ta, ma890; RV64NOM-NEXT: vmv.v.x v8, a0891; RV64NOM-NEXT: vmul.vx v8, v8, a1892; RV64NOM-NEXT: ret893;894; RV32M-LABEL: vmul_xx_nxv8i64:895; RV32M: # %bb.0:896; RV32M-NEXT: addi sp, sp, -16897; RV32M-NEXT: mul a4, a0, a2898; RV32M-NEXT: mul a3, a0, a3899; RV32M-NEXT: mulhu a0, a0, a2900; RV32M-NEXT: mul a1, a1, a2901; RV32M-NEXT: add a0, a0, a3902; RV32M-NEXT: add a0, a0, a1903; RV32M-NEXT: sw a4, 8(sp)904; RV32M-NEXT: sw a0, 12(sp)905; RV32M-NEXT: addi a0, sp, 8906; RV32M-NEXT: vsetvli a1, zero, e64, m8, ta, ma907; RV32M-NEXT: vlse64.v v8, (a0), zero908; RV32M-NEXT: addi sp, sp, 16909; RV32M-NEXT: ret910;911; RV64M-LABEL: vmul_xx_nxv8i64:912; RV64M: # %bb.0:913; RV64M-NEXT: mul a0, a0, a1914; RV64M-NEXT: vsetvli a1, zero, e64, m8, ta, ma915; RV64M-NEXT: vmv.v.x v8, a0916; RV64M-NEXT: ret917 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0918 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer919 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0920 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer921 %v = mul <vscale x 8 x i64> %splat1, %splat2922 ret <vscale x 8 x i64> %v923}924 925define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {926; CHECK-LABEL: vmul_vv_mask_nxv8i32:927; CHECK: # %bb.0:928; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu929; CHECK-NEXT: vmul.vv v8, v8, v12, v0.t930; CHECK-NEXT: ret931 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)932 %vc = mul <vscale x 8 x i32> %va, %vs933 ret <vscale x 8 x i32> %vc934}935 936define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {937; CHECK-LABEL: vmul_vx_mask_nxv8i32:938; CHECK: # %bb.0:939; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu940; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t941; CHECK-NEXT: ret942 %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0943 %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer944 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 1)945 %vc = mul <vscale x 8 x i32> %va, %vs946 ret <vscale x 8 x i32> %vc947}948 949define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {950; CHECK-LABEL: vmul_vi_mask_nxv8i32:951; CHECK: # %bb.0:952; CHECK-NEXT: li a0, 7953; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu954; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t955; CHECK-NEXT: ret956 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 1)957 %vc = mul <vscale x 8 x i32> %va, %vs958 ret <vscale x 8 x i32> %vc959}960