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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64d \7; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV328; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64d \9; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV6410 11define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {12; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vmul.vv v8, v8, v916; CHECK-NEXT: ret17entry:18 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(19 <vscale x 1 x i8> poison,20 <vscale x 1 x i8> %0,21 <vscale x 1 x i8> %1,22 iXLen %2)23 24 ret <vscale x 1 x i8> %a25}26 27define <vscale x 1 x i8> @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {28; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu31; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t32; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(35 <vscale x 1 x i8> %0,36 <vscale x 1 x i8> %1,37 <vscale x 1 x i8> %2,38 <vscale x 1 x i1> %3,39 iXLen %4, iXLen 1)40 41 ret <vscale x 1 x i8> %a42}43 44define <vscale x 2 x i8> @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma48; CHECK-NEXT: vmul.vv v8, v8, v949; CHECK-NEXT: ret50entry:51 %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(52 <vscale x 2 x i8> poison,53 <vscale x 2 x i8> %0,54 <vscale x 2 x i8> %1,55 iXLen %2)56 57 ret <vscale x 2 x i8> %a58}59 60define <vscale x 2 x i8> @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {61; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu64; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t65; CHECK-NEXT: ret66entry:67 %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(68 <vscale x 2 x i8> %0,69 <vscale x 2 x i8> %1,70 <vscale x 2 x i8> %2,71 <vscale x 2 x i1> %3,72 iXLen %4, iXLen 1)73 74 ret <vscale x 2 x i8> %a75}76 77define <vscale x 4 x i8> @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {78; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma81; CHECK-NEXT: vmul.vv v8, v8, v982; CHECK-NEXT: ret83entry:84 %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(85 <vscale x 4 x i8> poison,86 <vscale x 4 x i8> %0,87 <vscale x 4 x i8> %1,88 iXLen %2)89 90 ret <vscale x 4 x i8> %a91}92 93define <vscale x 4 x i8> @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {94; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu97; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t98; CHECK-NEXT: ret99entry:100 %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(101 <vscale x 4 x i8> %0,102 <vscale x 4 x i8> %1,103 <vscale x 4 x i8> %2,104 <vscale x 4 x i1> %3,105 iXLen %4, iXLen 1)106 107 ret <vscale x 4 x i8> %a108}109 110define <vscale x 8 x i8> @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {111; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma114; CHECK-NEXT: vmul.vv v8, v8, v9115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(118 <vscale x 8 x i8> poison,119 <vscale x 8 x i8> %0,120 <vscale x 8 x i8> %1,121 iXLen %2)122 123 ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu130; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(134 <vscale x 8 x i8> %0,135 <vscale x 8 x i8> %1,136 <vscale x 8 x i8> %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma147; CHECK-NEXT: vmul.vv v8, v8, v10148; CHECK-NEXT: ret149entry:150 %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(151 <vscale x 16 x i8> poison,152 <vscale x 16 x i8> %0,153 <vscale x 16 x i8> %1,154 iXLen %2)155 156 ret <vscale x 16 x i8> %a157}158 159define <vscale x 16 x i8> @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {160; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu163; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t164; CHECK-NEXT: ret165entry:166 %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(167 <vscale x 16 x i8> %0,168 <vscale x 16 x i8> %1,169 <vscale x 16 x i8> %2,170 <vscale x 16 x i1> %3,171 iXLen %4, iXLen 1)172 173 ret <vscale x 16 x i8> %a174}175 176define <vscale x 32 x i8> @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {177; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma180; CHECK-NEXT: vmul.vv v8, v8, v12181; CHECK-NEXT: ret182entry:183 %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(184 <vscale x 32 x i8> poison,185 <vscale x 32 x i8> %0,186 <vscale x 32 x i8> %1,187 iXLen %2)188 189 ret <vscale x 32 x i8> %a190}191 192define <vscale x 32 x i8> @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {193; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu196; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t197; CHECK-NEXT: ret198entry:199 %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(200 <vscale x 32 x i8> %0,201 <vscale x 32 x i8> %1,202 <vscale x 32 x i8> %2,203 <vscale x 32 x i1> %3,204 iXLen %4, iXLen 1)205 206 ret <vscale x 32 x i8> %a207}208 209define <vscale x 64 x i8> @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {210; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma213; CHECK-NEXT: vmul.vv v8, v8, v16214; CHECK-NEXT: ret215entry:216 %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(217 <vscale x 64 x i8> poison,218 <vscale x 64 x i8> %0,219 <vscale x 64 x i8> %1,220 iXLen %2)221 222 ret <vscale x 64 x i8> %a223}224 225define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {226; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:227; CHECK: # %bb.0: # %entry228; CHECK-NEXT: vl8r.v v24, (a0)229; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu230; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t231; CHECK-NEXT: ret232entry:233 %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(234 <vscale x 64 x i8> %0,235 <vscale x 64 x i8> %1,236 <vscale x 64 x i8> %2,237 <vscale x 64 x i1> %3,238 iXLen %4, iXLen 1)239 240 ret <vscale x 64 x i8> %a241}242 243define <vscale x 1 x i16> @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {244; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma247; CHECK-NEXT: vmul.vv v8, v8, v9248; CHECK-NEXT: ret249entry:250 %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(251 <vscale x 1 x i16> poison,252 <vscale x 1 x i16> %0,253 <vscale x 1 x i16> %1,254 iXLen %2)255 256 ret <vscale x 1 x i16> %a257}258 259define <vscale x 1 x i16> @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {260; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu263; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t264; CHECK-NEXT: ret265entry:266 %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(267 <vscale x 1 x i16> %0,268 <vscale x 1 x i16> %1,269 <vscale x 1 x i16> %2,270 <vscale x 1 x i1> %3,271 iXLen %4, iXLen 1)272 273 ret <vscale x 1 x i16> %a274}275 276define <vscale x 2 x i16> @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {277; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16:278; CHECK: # %bb.0: # %entry279; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma280; CHECK-NEXT: vmul.vv v8, v8, v9281; CHECK-NEXT: ret282entry:283 %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(284 <vscale x 2 x i16> poison,285 <vscale x 2 x i16> %0,286 <vscale x 2 x i16> %1,287 iXLen %2)288 289 ret <vscale x 2 x i16> %a290}291 292define <vscale x 2 x i16> @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {293; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu296; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(300 <vscale x 2 x i16> %0,301 <vscale x 2 x i16> %1,302 <vscale x 2 x i16> %2,303 <vscale x 2 x i1> %3,304 iXLen %4, iXLen 1)305 306 ret <vscale x 2 x i16> %a307}308 309define <vscale x 4 x i16> @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {310; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16:311; CHECK: # %bb.0: # %entry312; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma313; CHECK-NEXT: vmul.vv v8, v8, v9314; CHECK-NEXT: ret315entry:316 %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(317 <vscale x 4 x i16> poison,318 <vscale x 4 x i16> %0,319 <vscale x 4 x i16> %1,320 iXLen %2)321 322 ret <vscale x 4 x i16> %a323}324 325define <vscale x 4 x i16> @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {326; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16:327; CHECK: # %bb.0: # %entry328; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu329; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(333 <vscale x 4 x i16> %0,334 <vscale x 4 x i16> %1,335 <vscale x 4 x i16> %2,336 <vscale x 4 x i1> %3,337 iXLen %4, iXLen 1)338 339 ret <vscale x 4 x i16> %a340}341 342define <vscale x 8 x i16> @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {343; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16:344; CHECK: # %bb.0: # %entry345; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma346; CHECK-NEXT: vmul.vv v8, v8, v10347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(350 <vscale x 8 x i16> poison,351 <vscale x 8 x i16> %0,352 <vscale x 8 x i16> %1,353 iXLen %2)354 355 ret <vscale x 8 x i16> %a356}357 358define <vscale x 8 x i16> @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {359; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu362; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t363; CHECK-NEXT: ret364entry:365 %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(366 <vscale x 8 x i16> %0,367 <vscale x 8 x i16> %1,368 <vscale x 8 x i16> %2,369 <vscale x 8 x i1> %3,370 iXLen %4, iXLen 1)371 372 ret <vscale x 8 x i16> %a373}374 375define <vscale x 16 x i16> @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {376; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma379; CHECK-NEXT: vmul.vv v8, v8, v12380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(383 <vscale x 16 x i16> poison,384 <vscale x 16 x i16> %0,385 <vscale x 16 x i16> %1,386 iXLen %2)387 388 ret <vscale x 16 x i16> %a389}390 391define <vscale x 16 x i16> @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {392; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu395; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t396; CHECK-NEXT: ret397entry:398 %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(399 <vscale x 16 x i16> %0,400 <vscale x 16 x i16> %1,401 <vscale x 16 x i16> %2,402 <vscale x 16 x i1> %3,403 iXLen %4, iXLen 1)404 405 ret <vscale x 16 x i16> %a406}407 408define <vscale x 32 x i16> @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {409; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16:410; CHECK: # %bb.0: # %entry411; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma412; CHECK-NEXT: vmul.vv v8, v8, v16413; CHECK-NEXT: ret414entry:415 %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(416 <vscale x 32 x i16> poison,417 <vscale x 32 x i16> %0,418 <vscale x 32 x i16> %1,419 iXLen %2)420 421 ret <vscale x 32 x i16> %a422}423 424define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {425; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:426; CHECK: # %bb.0: # %entry427; CHECK-NEXT: vl8re16.v v24, (a0)428; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu429; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t430; CHECK-NEXT: ret431entry:432 %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(433 <vscale x 32 x i16> %0,434 <vscale x 32 x i16> %1,435 <vscale x 32 x i16> %2,436 <vscale x 32 x i1> %3,437 iXLen %4, iXLen 1)438 439 ret <vscale x 32 x i16> %a440}441 442define <vscale x 1 x i32> @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {443; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma446; CHECK-NEXT: vmul.vv v8, v8, v9447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(450 <vscale x 1 x i32> poison,451 <vscale x 1 x i32> %0,452 <vscale x 1 x i32> %1,453 iXLen %2)454 455 ret <vscale x 1 x i32> %a456}457 458define <vscale x 1 x i32> @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {459; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32:460; CHECK: # %bb.0: # %entry461; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu462; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t463; CHECK-NEXT: ret464entry:465 %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(466 <vscale x 1 x i32> %0,467 <vscale x 1 x i32> %1,468 <vscale x 1 x i32> %2,469 <vscale x 1 x i1> %3,470 iXLen %4, iXLen 1)471 472 ret <vscale x 1 x i32> %a473}474 475define <vscale x 2 x i32> @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32:477; CHECK: # %bb.0: # %entry478; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma479; CHECK-NEXT: vmul.vv v8, v8, v9480; CHECK-NEXT: ret481entry:482 %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(483 <vscale x 2 x i32> poison,484 <vscale x 2 x i32> %0,485 <vscale x 2 x i32> %1,486 iXLen %2)487 488 ret <vscale x 2 x i32> %a489}490 491define <vscale x 2 x i32> @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {492; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32:493; CHECK: # %bb.0: # %entry494; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu495; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t496; CHECK-NEXT: ret497entry:498 %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(499 <vscale x 2 x i32> %0,500 <vscale x 2 x i32> %1,501 <vscale x 2 x i32> %2,502 <vscale x 2 x i1> %3,503 iXLen %4, iXLen 1)504 505 ret <vscale x 2 x i32> %a506}507 508define <vscale x 4 x i32> @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {509; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32:510; CHECK: # %bb.0: # %entry511; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma512; CHECK-NEXT: vmul.vv v8, v8, v10513; CHECK-NEXT: ret514entry:515 %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(516 <vscale x 4 x i32> poison,517 <vscale x 4 x i32> %0,518 <vscale x 4 x i32> %1,519 iXLen %2)520 521 ret <vscale x 4 x i32> %a522}523 524define <vscale x 4 x i32> @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {525; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32:526; CHECK: # %bb.0: # %entry527; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu528; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t529; CHECK-NEXT: ret530entry:531 %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(532 <vscale x 4 x i32> %0,533 <vscale x 4 x i32> %1,534 <vscale x 4 x i32> %2,535 <vscale x 4 x i1> %3,536 iXLen %4, iXLen 1)537 538 ret <vscale x 4 x i32> %a539}540 541define <vscale x 8 x i32> @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {542; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32:543; CHECK: # %bb.0: # %entry544; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma545; CHECK-NEXT: vmul.vv v8, v8, v12546; CHECK-NEXT: ret547entry:548 %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(549 <vscale x 8 x i32> poison,550 <vscale x 8 x i32> %0,551 <vscale x 8 x i32> %1,552 iXLen %2)553 554 ret <vscale x 8 x i32> %a555}556 557define <vscale x 8 x i32> @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {558; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32:559; CHECK: # %bb.0: # %entry560; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu561; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t562; CHECK-NEXT: ret563entry:564 %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(565 <vscale x 8 x i32> %0,566 <vscale x 8 x i32> %1,567 <vscale x 8 x i32> %2,568 <vscale x 8 x i1> %3,569 iXLen %4, iXLen 1)570 571 ret <vscale x 8 x i32> %a572}573 574define <vscale x 16 x i32> @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {575; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32:576; CHECK: # %bb.0: # %entry577; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma578; CHECK-NEXT: vmul.vv v8, v8, v16579; CHECK-NEXT: ret580entry:581 %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(582 <vscale x 16 x i32> poison,583 <vscale x 16 x i32> %0,584 <vscale x 16 x i32> %1,585 iXLen %2)586 587 ret <vscale x 16 x i32> %a588}589 590define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {591; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:592; CHECK: # %bb.0: # %entry593; CHECK-NEXT: vl8re32.v v24, (a0)594; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu595; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t596; CHECK-NEXT: ret597entry:598 %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(599 <vscale x 16 x i32> %0,600 <vscale x 16 x i32> %1,601 <vscale x 16 x i32> %2,602 <vscale x 16 x i1> %3,603 iXLen %4, iXLen 1)604 605 ret <vscale x 16 x i32> %a606}607 608define <vscale x 1 x i64> @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {609; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma612; CHECK-NEXT: vmul.vv v8, v8, v9613; CHECK-NEXT: ret614entry:615 %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(616 <vscale x 1 x i64> poison,617 <vscale x 1 x i64> %0,618 <vscale x 1 x i64> %1,619 iXLen %2)620 621 ret <vscale x 1 x i64> %a622}623 624define <vscale x 1 x i64> @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {625; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64:626; CHECK: # %bb.0: # %entry627; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu628; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t629; CHECK-NEXT: ret630entry:631 %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(632 <vscale x 1 x i64> %0,633 <vscale x 1 x i64> %1,634 <vscale x 1 x i64> %2,635 <vscale x 1 x i1> %3,636 iXLen %4, iXLen 1)637 638 ret <vscale x 1 x i64> %a639}640 641define <vscale x 2 x i64> @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {642; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64:643; CHECK: # %bb.0: # %entry644; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma645; CHECK-NEXT: vmul.vv v8, v8, v10646; CHECK-NEXT: ret647entry:648 %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(649 <vscale x 2 x i64> poison,650 <vscale x 2 x i64> %0,651 <vscale x 2 x i64> %1,652 iXLen %2)653 654 ret <vscale x 2 x i64> %a655}656 657define <vscale x 2 x i64> @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {658; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64:659; CHECK: # %bb.0: # %entry660; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu661; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t662; CHECK-NEXT: ret663entry:664 %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(665 <vscale x 2 x i64> %0,666 <vscale x 2 x i64> %1,667 <vscale x 2 x i64> %2,668 <vscale x 2 x i1> %3,669 iXLen %4, iXLen 1)670 671 ret <vscale x 2 x i64> %a672}673 674define <vscale x 4 x i64> @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {675; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64:676; CHECK: # %bb.0: # %entry677; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma678; CHECK-NEXT: vmul.vv v8, v8, v12679; CHECK-NEXT: ret680entry:681 %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(682 <vscale x 4 x i64> poison,683 <vscale x 4 x i64> %0,684 <vscale x 4 x i64> %1,685 iXLen %2)686 687 ret <vscale x 4 x i64> %a688}689 690define <vscale x 4 x i64> @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {691; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu694; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t695; CHECK-NEXT: ret696entry:697 %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(698 <vscale x 4 x i64> %0,699 <vscale x 4 x i64> %1,700 <vscale x 4 x i64> %2,701 <vscale x 4 x i1> %3,702 iXLen %4, iXLen 1)703 704 ret <vscale x 4 x i64> %a705}706 707define <vscale x 8 x i64> @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {708; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64:709; CHECK: # %bb.0: # %entry710; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma711; CHECK-NEXT: vmul.vv v8, v8, v16712; CHECK-NEXT: ret713entry:714 %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(715 <vscale x 8 x i64> poison,716 <vscale x 8 x i64> %0,717 <vscale x 8 x i64> %1,718 iXLen %2)719 720 ret <vscale x 8 x i64> %a721}722 723define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {724; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:725; CHECK: # %bb.0: # %entry726; CHECK-NEXT: vl8re64.v v24, (a0)727; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu728; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t729; CHECK-NEXT: ret730entry:731 %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(732 <vscale x 8 x i64> %0,733 <vscale x 8 x i64> %1,734 <vscale x 8 x i64> %2,735 <vscale x 8 x i1> %3,736 iXLen %4, iXLen 1)737 738 ret <vscale x 8 x i64> %a739}740 741define <vscale x 1 x i8> @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {742; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8:743; CHECK: # %bb.0: # %entry744; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma745; CHECK-NEXT: vmul.vx v8, v8, a0746; CHECK-NEXT: ret747entry:748 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(749 <vscale x 1 x i8> poison,750 <vscale x 1 x i8> %0,751 i8 %1,752 iXLen %2)753 754 ret <vscale x 1 x i8> %a755}756 757define <vscale x 1 x i8> @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {758; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8:759; CHECK: # %bb.0: # %entry760; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu761; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t762; CHECK-NEXT: ret763entry:764 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(765 <vscale x 1 x i8> %0,766 <vscale x 1 x i8> %1,767 i8 %2,768 <vscale x 1 x i1> %3,769 iXLen %4, iXLen 1)770 771 ret <vscale x 1 x i8> %a772}773 774define <vscale x 2 x i8> @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {775; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8:776; CHECK: # %bb.0: # %entry777; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma778; CHECK-NEXT: vmul.vx v8, v8, a0779; CHECK-NEXT: ret780entry:781 %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(782 <vscale x 2 x i8> poison,783 <vscale x 2 x i8> %0,784 i8 %1,785 iXLen %2)786 787 ret <vscale x 2 x i8> %a788}789 790define <vscale x 2 x i8> @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {791; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8:792; CHECK: # %bb.0: # %entry793; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu794; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t795; CHECK-NEXT: ret796entry:797 %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(798 <vscale x 2 x i8> %0,799 <vscale x 2 x i8> %1,800 i8 %2,801 <vscale x 2 x i1> %3,802 iXLen %4, iXLen 1)803 804 ret <vscale x 2 x i8> %a805}806 807define <vscale x 4 x i8> @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {808; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8:809; CHECK: # %bb.0: # %entry810; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma811; CHECK-NEXT: vmul.vx v8, v8, a0812; CHECK-NEXT: ret813entry:814 %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(815 <vscale x 4 x i8> poison,816 <vscale x 4 x i8> %0,817 i8 %1,818 iXLen %2)819 820 ret <vscale x 4 x i8> %a821}822 823define <vscale x 4 x i8> @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {824; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8:825; CHECK: # %bb.0: # %entry826; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu827; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t828; CHECK-NEXT: ret829entry:830 %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(831 <vscale x 4 x i8> %0,832 <vscale x 4 x i8> %1,833 i8 %2,834 <vscale x 4 x i1> %3,835 iXLen %4, iXLen 1)836 837 ret <vscale x 4 x i8> %a838}839 840define <vscale x 8 x i8> @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {841; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8:842; CHECK: # %bb.0: # %entry843; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma844; CHECK-NEXT: vmul.vx v8, v8, a0845; CHECK-NEXT: ret846entry:847 %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(848 <vscale x 8 x i8> poison,849 <vscale x 8 x i8> %0,850 i8 %1,851 iXLen %2)852 853 ret <vscale x 8 x i8> %a854}855 856define <vscale x 8 x i8> @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {857; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8:858; CHECK: # %bb.0: # %entry859; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu860; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t861; CHECK-NEXT: ret862entry:863 %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(864 <vscale x 8 x i8> %0,865 <vscale x 8 x i8> %1,866 i8 %2,867 <vscale x 8 x i1> %3,868 iXLen %4, iXLen 1)869 870 ret <vscale x 8 x i8> %a871}872 873define <vscale x 16 x i8> @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {874; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8:875; CHECK: # %bb.0: # %entry876; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma877; CHECK-NEXT: vmul.vx v8, v8, a0878; CHECK-NEXT: ret879entry:880 %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(881 <vscale x 16 x i8> poison,882 <vscale x 16 x i8> %0,883 i8 %1,884 iXLen %2)885 886 ret <vscale x 16 x i8> %a887}888 889define <vscale x 16 x i8> @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {890; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8:891; CHECK: # %bb.0: # %entry892; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu893; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t894; CHECK-NEXT: ret895entry:896 %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(897 <vscale x 16 x i8> %0,898 <vscale x 16 x i8> %1,899 i8 %2,900 <vscale x 16 x i1> %3,901 iXLen %4, iXLen 1)902 903 ret <vscale x 16 x i8> %a904}905 906define <vscale x 32 x i8> @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {907; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8:908; CHECK: # %bb.0: # %entry909; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma910; CHECK-NEXT: vmul.vx v8, v8, a0911; CHECK-NEXT: ret912entry:913 %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(914 <vscale x 32 x i8> poison,915 <vscale x 32 x i8> %0,916 i8 %1,917 iXLen %2)918 919 ret <vscale x 32 x i8> %a920}921 922define <vscale x 32 x i8> @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {923; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8:924; CHECK: # %bb.0: # %entry925; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu926; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t927; CHECK-NEXT: ret928entry:929 %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(930 <vscale x 32 x i8> %0,931 <vscale x 32 x i8> %1,932 i8 %2,933 <vscale x 32 x i1> %3,934 iXLen %4, iXLen 1)935 936 ret <vscale x 32 x i8> %a937}938 939define <vscale x 64 x i8> @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {940; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8:941; CHECK: # %bb.0: # %entry942; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma943; CHECK-NEXT: vmul.vx v8, v8, a0944; CHECK-NEXT: ret945entry:946 %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(947 <vscale x 64 x i8> poison,948 <vscale x 64 x i8> %0,949 i8 %1,950 iXLen %2)951 952 ret <vscale x 64 x i8> %a953}954 955define <vscale x 64 x i8> @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {956; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8:957; CHECK: # %bb.0: # %entry958; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu959; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t960; CHECK-NEXT: ret961entry:962 %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(963 <vscale x 64 x i8> %0,964 <vscale x 64 x i8> %1,965 i8 %2,966 <vscale x 64 x i1> %3,967 iXLen %4, iXLen 1)968 969 ret <vscale x 64 x i8> %a970}971 972define <vscale x 1 x i16> @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {973; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16:974; CHECK: # %bb.0: # %entry975; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma976; CHECK-NEXT: vmul.vx v8, v8, a0977; CHECK-NEXT: ret978entry:979 %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(980 <vscale x 1 x i16> poison,981 <vscale x 1 x i16> %0,982 i16 %1,983 iXLen %2)984 985 ret <vscale x 1 x i16> %a986}987 988define <vscale x 1 x i16> @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {989; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16:990; CHECK: # %bb.0: # %entry991; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu992; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t993; CHECK-NEXT: ret994entry:995 %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(996 <vscale x 1 x i16> %0,997 <vscale x 1 x i16> %1,998 i16 %2,999 <vscale x 1 x i1> %3,1000 iXLen %4, iXLen 1)1001 1002 ret <vscale x 1 x i16> %a1003}1004 1005define <vscale x 2 x i16> @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1006; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16:1007; CHECK: # %bb.0: # %entry1008; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1009; CHECK-NEXT: vmul.vx v8, v8, a01010; CHECK-NEXT: ret1011entry:1012 %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(1013 <vscale x 2 x i16> poison,1014 <vscale x 2 x i16> %0,1015 i16 %1,1016 iXLen %2)1017 1018 ret <vscale x 2 x i16> %a1019}1020 1021define <vscale x 2 x i16> @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1022; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16:1023; CHECK: # %bb.0: # %entry1024; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1025; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t1026; CHECK-NEXT: ret1027entry:1028 %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(1029 <vscale x 2 x i16> %0,1030 <vscale x 2 x i16> %1,1031 i16 %2,1032 <vscale x 2 x i1> %3,1033 iXLen %4, iXLen 1)1034 1035 ret <vscale x 2 x i16> %a1036}1037 1038define <vscale x 4 x i16> @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1039; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16:1040; CHECK: # %bb.0: # %entry1041; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1042; CHECK-NEXT: vmul.vx v8, v8, a01043; CHECK-NEXT: ret1044entry:1045 %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(1046 <vscale x 4 x i16> poison,1047 <vscale x 4 x i16> %0,1048 i16 %1,1049 iXLen %2)1050 1051 ret <vscale x 4 x i16> %a1052}1053 1054define <vscale x 4 x i16> @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1055; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16:1056; CHECK: # %bb.0: # %entry1057; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1058; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t1059; CHECK-NEXT: ret1060entry:1061 %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(1062 <vscale x 4 x i16> %0,1063 <vscale x 4 x i16> %1,1064 i16 %2,1065 <vscale x 4 x i1> %3,1066 iXLen %4, iXLen 1)1067 1068 ret <vscale x 4 x i16> %a1069}1070 1071define <vscale x 8 x i16> @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1072; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16:1073; CHECK: # %bb.0: # %entry1074; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1075; CHECK-NEXT: vmul.vx v8, v8, a01076; CHECK-NEXT: ret1077entry:1078 %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(1079 <vscale x 8 x i16> poison,1080 <vscale x 8 x i16> %0,1081 i16 %1,1082 iXLen %2)1083 1084 ret <vscale x 8 x i16> %a1085}1086 1087define <vscale x 8 x i16> @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1088; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16:1089; CHECK: # %bb.0: # %entry1090; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1091; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t1092; CHECK-NEXT: ret1093entry:1094 %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(1095 <vscale x 8 x i16> %0,1096 <vscale x 8 x i16> %1,1097 i16 %2,1098 <vscale x 8 x i1> %3,1099 iXLen %4, iXLen 1)1100 1101 ret <vscale x 8 x i16> %a1102}1103 1104define <vscale x 16 x i16> @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1105; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16:1106; CHECK: # %bb.0: # %entry1107; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1108; CHECK-NEXT: vmul.vx v8, v8, a01109; CHECK-NEXT: ret1110entry:1111 %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(1112 <vscale x 16 x i16> poison,1113 <vscale x 16 x i16> %0,1114 i16 %1,1115 iXLen %2)1116 1117 ret <vscale x 16 x i16> %a1118}1119 1120define <vscale x 16 x i16> @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1121; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16:1122; CHECK: # %bb.0: # %entry1123; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1124; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t1125; CHECK-NEXT: ret1126entry:1127 %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(1128 <vscale x 16 x i16> %0,1129 <vscale x 16 x i16> %1,1130 i16 %2,1131 <vscale x 16 x i1> %3,1132 iXLen %4, iXLen 1)1133 1134 ret <vscale x 16 x i16> %a1135}1136 1137define <vscale x 32 x i16> @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1138; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16:1139; CHECK: # %bb.0: # %entry1140; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1141; CHECK-NEXT: vmul.vx v8, v8, a01142; CHECK-NEXT: ret1143entry:1144 %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(1145 <vscale x 32 x i16> poison,1146 <vscale x 32 x i16> %0,1147 i16 %1,1148 iXLen %2)1149 1150 ret <vscale x 32 x i16> %a1151}1152 1153define <vscale x 32 x i16> @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1154; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16:1155; CHECK: # %bb.0: # %entry1156; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1157; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t1158; CHECK-NEXT: ret1159entry:1160 %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(1161 <vscale x 32 x i16> %0,1162 <vscale x 32 x i16> %1,1163 i16 %2,1164 <vscale x 32 x i1> %3,1165 iXLen %4, iXLen 1)1166 1167 ret <vscale x 32 x i16> %a1168}1169 1170define <vscale x 1 x i32> @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1171; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32:1172; CHECK: # %bb.0: # %entry1173; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1174; CHECK-NEXT: vmul.vx v8, v8, a01175; CHECK-NEXT: ret1176entry:1177 %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(1178 <vscale x 1 x i32> poison,1179 <vscale x 1 x i32> %0,1180 i32 %1,1181 iXLen %2)1182 1183 ret <vscale x 1 x i32> %a1184}1185 1186define <vscale x 1 x i32> @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1187; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32:1188; CHECK: # %bb.0: # %entry1189; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1190; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t1191; CHECK-NEXT: ret1192entry:1193 %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(1194 <vscale x 1 x i32> %0,1195 <vscale x 1 x i32> %1,1196 i32 %2,1197 <vscale x 1 x i1> %3,1198 iXLen %4, iXLen 1)1199 1200 ret <vscale x 1 x i32> %a1201}1202 1203define <vscale x 2 x i32> @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1204; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32:1205; CHECK: # %bb.0: # %entry1206; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1207; CHECK-NEXT: vmul.vx v8, v8, a01208; CHECK-NEXT: ret1209entry:1210 %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(1211 <vscale x 2 x i32> poison,1212 <vscale x 2 x i32> %0,1213 i32 %1,1214 iXLen %2)1215 1216 ret <vscale x 2 x i32> %a1217}1218 1219define <vscale x 2 x i32> @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1220; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32:1221; CHECK: # %bb.0: # %entry1222; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1223; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t1224; CHECK-NEXT: ret1225entry:1226 %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(1227 <vscale x 2 x i32> %0,1228 <vscale x 2 x i32> %1,1229 i32 %2,1230 <vscale x 2 x i1> %3,1231 iXLen %4, iXLen 1)1232 1233 ret <vscale x 2 x i32> %a1234}1235 1236define <vscale x 4 x i32> @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1237; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32:1238; CHECK: # %bb.0: # %entry1239; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1240; CHECK-NEXT: vmul.vx v8, v8, a01241; CHECK-NEXT: ret1242entry:1243 %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(1244 <vscale x 4 x i32> poison,1245 <vscale x 4 x i32> %0,1246 i32 %1,1247 iXLen %2)1248 1249 ret <vscale x 4 x i32> %a1250}1251 1252define <vscale x 4 x i32> @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1253; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32:1254; CHECK: # %bb.0: # %entry1255; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1256; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t1257; CHECK-NEXT: ret1258entry:1259 %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(1260 <vscale x 4 x i32> %0,1261 <vscale x 4 x i32> %1,1262 i32 %2,1263 <vscale x 4 x i1> %3,1264 iXLen %4, iXLen 1)1265 1266 ret <vscale x 4 x i32> %a1267}1268 1269define <vscale x 8 x i32> @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1270; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32:1271; CHECK: # %bb.0: # %entry1272; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1273; CHECK-NEXT: vmul.vx v8, v8, a01274; CHECK-NEXT: ret1275entry:1276 %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(1277 <vscale x 8 x i32> poison,1278 <vscale x 8 x i32> %0,1279 i32 %1,1280 iXLen %2)1281 1282 ret <vscale x 8 x i32> %a1283}1284 1285define <vscale x 8 x i32> @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1286; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32:1287; CHECK: # %bb.0: # %entry1288; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1289; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t1290; CHECK-NEXT: ret1291entry:1292 %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(1293 <vscale x 8 x i32> %0,1294 <vscale x 8 x i32> %1,1295 i32 %2,1296 <vscale x 8 x i1> %3,1297 iXLen %4, iXLen 1)1298 1299 ret <vscale x 8 x i32> %a1300}1301 1302define <vscale x 16 x i32> @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1303; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32:1304; CHECK: # %bb.0: # %entry1305; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1306; CHECK-NEXT: vmul.vx v8, v8, a01307; CHECK-NEXT: ret1308entry:1309 %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(1310 <vscale x 16 x i32> poison,1311 <vscale x 16 x i32> %0,1312 i32 %1,1313 iXLen %2)1314 1315 ret <vscale x 16 x i32> %a1316}1317 1318define <vscale x 16 x i32> @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1319; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32:1320; CHECK: # %bb.0: # %entry1321; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu1322; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t1323; CHECK-NEXT: ret1324entry:1325 %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(1326 <vscale x 16 x i32> %0,1327 <vscale x 16 x i32> %1,1328 i32 %2,1329 <vscale x 16 x i1> %3,1330 iXLen %4, iXLen 1)1331 1332 ret <vscale x 16 x i32> %a1333}1334 1335define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1336; RV32-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:1337; RV32: # %bb.0: # %entry1338; RV32-NEXT: addi sp, sp, -161339; RV32-NEXT: sw a0, 8(sp)1340; RV32-NEXT: sw a1, 12(sp)1341; RV32-NEXT: addi a0, sp, 81342; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1343; RV32-NEXT: vlse64.v v9, (a0), zero1344; RV32-NEXT: vmul.vv v8, v8, v91345; RV32-NEXT: addi sp, sp, 161346; RV32-NEXT: ret1347;1348; RV64-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:1349; RV64: # %bb.0: # %entry1350; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1351; RV64-NEXT: vmul.vx v8, v8, a01352; RV64-NEXT: ret1353entry:1354 %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(1355 <vscale x 1 x i64> poison,1356 <vscale x 1 x i64> %0,1357 i64 %1,1358 iXLen %2)1359 1360 ret <vscale x 1 x i64> %a1361}1362 1363define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1364; RV32-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:1365; RV32: # %bb.0: # %entry1366; RV32-NEXT: addi sp, sp, -161367; RV32-NEXT: sw a0, 8(sp)1368; RV32-NEXT: sw a1, 12(sp)1369; RV32-NEXT: addi a0, sp, 81370; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu1371; RV32-NEXT: vlse64.v v10, (a0), zero1372; RV32-NEXT: vmul.vv v8, v9, v10, v0.t1373; RV32-NEXT: addi sp, sp, 161374; RV32-NEXT: ret1375;1376; RV64-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:1377; RV64: # %bb.0: # %entry1378; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu1379; RV64-NEXT: vmul.vx v8, v9, a0, v0.t1380; RV64-NEXT: ret1381entry:1382 %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(1383 <vscale x 1 x i64> %0,1384 <vscale x 1 x i64> %1,1385 i64 %2,1386 <vscale x 1 x i1> %3,1387 iXLen %4, iXLen 1)1388 1389 ret <vscale x 1 x i64> %a1390}1391 1392define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1393; RV32-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:1394; RV32: # %bb.0: # %entry1395; RV32-NEXT: addi sp, sp, -161396; RV32-NEXT: sw a0, 8(sp)1397; RV32-NEXT: sw a1, 12(sp)1398; RV32-NEXT: addi a0, sp, 81399; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1400; RV32-NEXT: vlse64.v v10, (a0), zero1401; RV32-NEXT: vmul.vv v8, v8, v101402; RV32-NEXT: addi sp, sp, 161403; RV32-NEXT: ret1404;1405; RV64-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:1406; RV64: # %bb.0: # %entry1407; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1408; RV64-NEXT: vmul.vx v8, v8, a01409; RV64-NEXT: ret1410entry:1411 %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(1412 <vscale x 2 x i64> poison,1413 <vscale x 2 x i64> %0,1414 i64 %1,1415 iXLen %2)1416 1417 ret <vscale x 2 x i64> %a1418}1419 1420define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1421; RV32-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:1422; RV32: # %bb.0: # %entry1423; RV32-NEXT: addi sp, sp, -161424; RV32-NEXT: sw a0, 8(sp)1425; RV32-NEXT: sw a1, 12(sp)1426; RV32-NEXT: addi a0, sp, 81427; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu1428; RV32-NEXT: vlse64.v v12, (a0), zero1429; RV32-NEXT: vmul.vv v8, v10, v12, v0.t1430; RV32-NEXT: addi sp, sp, 161431; RV32-NEXT: ret1432;1433; RV64-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:1434; RV64: # %bb.0: # %entry1435; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu1436; RV64-NEXT: vmul.vx v8, v10, a0, v0.t1437; RV64-NEXT: ret1438entry:1439 %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(1440 <vscale x 2 x i64> %0,1441 <vscale x 2 x i64> %1,1442 i64 %2,1443 <vscale x 2 x i1> %3,1444 iXLen %4, iXLen 1)1445 1446 ret <vscale x 2 x i64> %a1447}1448 1449define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1450; RV32-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:1451; RV32: # %bb.0: # %entry1452; RV32-NEXT: addi sp, sp, -161453; RV32-NEXT: sw a0, 8(sp)1454; RV32-NEXT: sw a1, 12(sp)1455; RV32-NEXT: addi a0, sp, 81456; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1457; RV32-NEXT: vlse64.v v12, (a0), zero1458; RV32-NEXT: vmul.vv v8, v8, v121459; RV32-NEXT: addi sp, sp, 161460; RV32-NEXT: ret1461;1462; RV64-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:1463; RV64: # %bb.0: # %entry1464; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1465; RV64-NEXT: vmul.vx v8, v8, a01466; RV64-NEXT: ret1467entry:1468 %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(1469 <vscale x 4 x i64> poison,1470 <vscale x 4 x i64> %0,1471 i64 %1,1472 iXLen %2)1473 1474 ret <vscale x 4 x i64> %a1475}1476 1477define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1478; RV32-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:1479; RV32: # %bb.0: # %entry1480; RV32-NEXT: addi sp, sp, -161481; RV32-NEXT: sw a0, 8(sp)1482; RV32-NEXT: sw a1, 12(sp)1483; RV32-NEXT: addi a0, sp, 81484; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu1485; RV32-NEXT: vlse64.v v16, (a0), zero1486; RV32-NEXT: vmul.vv v8, v12, v16, v0.t1487; RV32-NEXT: addi sp, sp, 161488; RV32-NEXT: ret1489;1490; RV64-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:1491; RV64: # %bb.0: # %entry1492; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu1493; RV64-NEXT: vmul.vx v8, v12, a0, v0.t1494; RV64-NEXT: ret1495entry:1496 %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(1497 <vscale x 4 x i64> %0,1498 <vscale x 4 x i64> %1,1499 i64 %2,1500 <vscale x 4 x i1> %3,1501 iXLen %4, iXLen 1)1502 1503 ret <vscale x 4 x i64> %a1504}1505 1506define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1507; RV32-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:1508; RV32: # %bb.0: # %entry1509; RV32-NEXT: addi sp, sp, -161510; RV32-NEXT: sw a0, 8(sp)1511; RV32-NEXT: sw a1, 12(sp)1512; RV32-NEXT: addi a0, sp, 81513; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1514; RV32-NEXT: vlse64.v v16, (a0), zero1515; RV32-NEXT: vmul.vv v8, v8, v161516; RV32-NEXT: addi sp, sp, 161517; RV32-NEXT: ret1518;1519; RV64-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:1520; RV64: # %bb.0: # %entry1521; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1522; RV64-NEXT: vmul.vx v8, v8, a01523; RV64-NEXT: ret1524entry:1525 %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(1526 <vscale x 8 x i64> poison,1527 <vscale x 8 x i64> %0,1528 i64 %1,1529 iXLen %2)1530 1531 ret <vscale x 8 x i64> %a1532}1533 1534define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1535; RV32-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:1536; RV32: # %bb.0: # %entry1537; RV32-NEXT: addi sp, sp, -161538; RV32-NEXT: sw a0, 8(sp)1539; RV32-NEXT: sw a1, 12(sp)1540; RV32-NEXT: addi a0, sp, 81541; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu1542; RV32-NEXT: vlse64.v v24, (a0), zero1543; RV32-NEXT: vmul.vv v8, v16, v24, v0.t1544; RV32-NEXT: addi sp, sp, 161545; RV32-NEXT: ret1546;1547; RV64-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:1548; RV64: # %bb.0: # %entry1549; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu1550; RV64-NEXT: vmul.vx v8, v16, a0, v0.t1551; RV64-NEXT: ret1552entry:1553 %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(1554 <vscale x 8 x i64> %0,1555 <vscale x 8 x i64> %1,1556 i64 %2,1557 <vscale x 8 x i1> %3,1558 iXLen %4, iXLen 1)1559 1560 ret <vscale x 8 x i64> %a1561}1562