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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5; Test that the prepareSREMEqFold optimization doesn't crash on scalable6; vector types.7define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {8; CHECK-LABEL: srem_eq_fold_nxv4i8:9; CHECK: # %bb.0:10; CHECK-NEXT: li a0, 4211; CHECK-NEXT: li a1, -8512; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma13; CHECK-NEXT: vmv.v.x v9, a014; CHECK-NEXT: vmacc.vx v9, a1, v815; CHECK-NEXT: vsll.vi v8, v9, 716; CHECK-NEXT: vsrl.vi v9, v9, 117; CHECK-NEXT: vor.vv v8, v9, v818; CHECK-NEXT: vmsleu.vx v0, v8, a019; CHECK-NEXT: ret20 %rem = srem <vscale x 4 x i8> %va, splat (i8 6)21 22 %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer23 ret <vscale x 4 x i1> %cc24}25 26define <vscale x 1 x i32> @vmulh_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {27; CHECK-LABEL: vmulh_vv_nxv1i32:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma30; CHECK-NEXT: vmulh.vv v8, v9, v831; CHECK-NEXT: ret32 %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>33 %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>34 %ve = mul <vscale x 1 x i64> %vc, %vd35 %vf = lshr <vscale x 1 x i64> %ve, splat (i64 32)36 %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>37 ret <vscale x 1 x i32> %vg38}39 40define <vscale x 1 x i32> @vmulh_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {41; CHECK-LABEL: vmulh_vx_nxv1i32:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma44; CHECK-NEXT: vmulh.vx v8, v8, a045; CHECK-NEXT: ret46 %head1 = insertelement <vscale x 1 x i32> poison, i32 %x, i32 047 %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer48 %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>49 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>50 %vd = mul <vscale x 1 x i64> %vb, %vc51 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)52 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>53 ret <vscale x 1 x i32> %vf54}55 56define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {57; CHECK-LABEL: vmulh_vi_nxv1i32_0:58; CHECK: # %bb.0:59; CHECK-NEXT: li a0, -760; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma61; CHECK-NEXT: vmulh.vx v8, v8, a062; CHECK-NEXT: ret63 %vb = sext <vscale x 1 x i32> splat (i32 -7) to <vscale x 1 x i64>64 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>65 %vd = mul <vscale x 1 x i64> %vb, %vc66 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)67 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>68 ret <vscale x 1 x i32> %vf69}70 71define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {72; CHECK-LABEL: vmulh_vi_nxv1i32_1:73; CHECK: # %bb.0:74; CHECK-NEXT: li a0, 1675; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma76; CHECK-NEXT: vmulh.vx v8, v8, a077; CHECK-NEXT: ret78 %vb = sext <vscale x 1 x i32> splat (i32 16) to <vscale x 1 x i64>79 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>80 %vd = mul <vscale x 1 x i64> %vb, %vc81 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)82 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>83 ret <vscale x 1 x i32> %vf84}85 86define <vscale x 2 x i32> @vmulh_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {87; CHECK-LABEL: vmulh_vv_nxv2i32:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma90; CHECK-NEXT: vmulh.vv v8, v9, v891; CHECK-NEXT: ret92 %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>93 %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>94 %ve = mul <vscale x 2 x i64> %vc, %vd95 %vf = lshr <vscale x 2 x i64> %ve, splat (i64 32)96 %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>97 ret <vscale x 2 x i32> %vg98}99 100define <vscale x 2 x i32> @vmulh_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {101; CHECK-LABEL: vmulh_vx_nxv2i32:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma104; CHECK-NEXT: vmulh.vx v8, v8, a0105; CHECK-NEXT: ret106 %head1 = insertelement <vscale x 2 x i32> poison, i32 %x, i32 0107 %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer108 %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>109 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>110 %vd = mul <vscale x 2 x i64> %vb, %vc111 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)112 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>113 ret <vscale x 2 x i32> %vf114}115 116define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {117; CHECK-LABEL: vmulh_vi_nxv2i32_0:118; CHECK: # %bb.0:119; CHECK-NEXT: li a0, -7120; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma121; CHECK-NEXT: vmulh.vx v8, v8, a0122; CHECK-NEXT: ret123 %vb = sext <vscale x 2 x i32> splat (i32 -7) to <vscale x 2 x i64>124 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>125 %vd = mul <vscale x 2 x i64> %vb, %vc126 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)127 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>128 ret <vscale x 2 x i32> %vf129}130 131define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {132; CHECK-LABEL: vmulh_vi_nxv2i32_1:133; CHECK: # %bb.0:134; CHECK-NEXT: li a0, 16135; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma136; CHECK-NEXT: vmulh.vx v8, v8, a0137; CHECK-NEXT: ret138 %vb = sext <vscale x 2 x i32> splat (i32 16) to <vscale x 2 x i64>139 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>140 %vd = mul <vscale x 2 x i64> %vb, %vc141 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)142 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>143 ret <vscale x 2 x i32> %vf144}145 146define <vscale x 4 x i32> @vmulh_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {147; CHECK-LABEL: vmulh_vv_nxv4i32:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma150; CHECK-NEXT: vmulh.vv v8, v10, v8151; CHECK-NEXT: ret152 %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>153 %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>154 %ve = mul <vscale x 4 x i64> %vc, %vd155 %vf = lshr <vscale x 4 x i64> %ve, splat (i64 32)156 %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>157 ret <vscale x 4 x i32> %vg158}159 160define <vscale x 4 x i32> @vmulh_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {161; CHECK-LABEL: vmulh_vx_nxv4i32:162; CHECK: # %bb.0:163; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma164; CHECK-NEXT: vmulh.vx v8, v8, a0165; CHECK-NEXT: ret166 %head1 = insertelement <vscale x 4 x i32> poison, i32 %x, i32 0167 %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer168 %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>169 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>170 %vd = mul <vscale x 4 x i64> %vb, %vc171 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)172 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>173 ret <vscale x 4 x i32> %vf174}175 176define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {177; CHECK-LABEL: vmulh_vi_nxv4i32_0:178; CHECK: # %bb.0:179; CHECK-NEXT: li a0, -7180; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma181; CHECK-NEXT: vmulh.vx v8, v8, a0182; CHECK-NEXT: ret183 %vb = sext <vscale x 4 x i32> splat (i32 -7) to <vscale x 4 x i64>184 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>185 %vd = mul <vscale x 4 x i64> %vb, %vc186 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)187 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>188 ret <vscale x 4 x i32> %vf189}190 191define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {192; CHECK-LABEL: vmulh_vi_nxv4i32_1:193; CHECK: # %bb.0:194; CHECK-NEXT: li a0, 16195; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma196; CHECK-NEXT: vmulh.vx v8, v8, a0197; CHECK-NEXT: ret198 %vb = sext <vscale x 4 x i32> splat (i32 16) to <vscale x 4 x i64>199 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>200 %vd = mul <vscale x 4 x i64> %vb, %vc201 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)202 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>203 ret <vscale x 4 x i32> %vf204}205 206define <vscale x 8 x i32> @vmulh_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {207; CHECK-LABEL: vmulh_vv_nxv8i32:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma210; CHECK-NEXT: vmulh.vv v8, v12, v8211; CHECK-NEXT: ret212 %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>213 %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>214 %ve = mul <vscale x 8 x i64> %vc, %vd215 %vf = lshr <vscale x 8 x i64> %ve, splat (i64 32)216 %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>217 ret <vscale x 8 x i32> %vg218}219 220define <vscale x 8 x i32> @vmulh_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {221; CHECK-LABEL: vmulh_vx_nxv8i32:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma224; CHECK-NEXT: vmulh.vx v8, v8, a0225; CHECK-NEXT: ret226 %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0227 %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer228 %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>229 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>230 %vd = mul <vscale x 8 x i64> %vb, %vc231 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)232 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>233 ret <vscale x 8 x i32> %vf234}235 236define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {237; CHECK-LABEL: vmulh_vi_nxv8i32_0:238; CHECK: # %bb.0:239; CHECK-NEXT: li a0, -7240; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma241; CHECK-NEXT: vmulh.vx v8, v8, a0242; CHECK-NEXT: ret243 %vb = sext <vscale x 8 x i32> splat (i32 -7) to <vscale x 8 x i64>244 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>245 %vd = mul <vscale x 8 x i64> %vb, %vc246 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)247 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>248 ret <vscale x 8 x i32> %vf249}250 251define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {252; CHECK-LABEL: vmulh_vi_nxv8i32_1:253; CHECK: # %bb.0:254; CHECK-NEXT: li a0, 16255; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma256; CHECK-NEXT: vmulh.vx v8, v8, a0257; CHECK-NEXT: ret258 %vb = sext <vscale x 8 x i32> splat (i32 16) to <vscale x 8 x i64>259 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>260 %vd = mul <vscale x 8 x i64> %vb, %vc261 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)262 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>263 ret <vscale x 8 x i32> %vf264}265