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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 \7; RUN: -mattr=+zve64d 2>&1 | FileCheck %s --check-prefixes=ZVE64D8; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 \9; RUN: -mattr=+zve64d 2>&1 | FileCheck %s --check-prefixes=ZVE64D10 11; ZVE64D: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vmulh12 13define <vscale x 1 x i8> @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {14; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma17; CHECK-NEXT: vmulh.vv v8, v8, v918; CHECK-NEXT: ret19entry:20 %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8(21 <vscale x 1 x i8> poison,22 <vscale x 1 x i8> %0,23 <vscale x 1 x i8> %1,24 iXLen %2)25 26 ret <vscale x 1 x i8> %a27}28 29define <vscale x 1 x i8> @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {30; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu33; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t34; CHECK-NEXT: ret35entry:36 %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8(37 <vscale x 1 x i8> %0,38 <vscale x 1 x i8> %1,39 <vscale x 1 x i8> %2,40 <vscale x 1 x i1> %3,41 iXLen %4, iXLen 1)42 43 ret <vscale x 1 x i8> %a44}45 46define <vscale x 2 x i8> @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma50; CHECK-NEXT: vmulh.vv v8, v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8(54 <vscale x 2 x i8> poison,55 <vscale x 2 x i8> %0,56 <vscale x 2 x i8> %1,57 iXLen %2)58 59 ret <vscale x 2 x i8> %a60}61 62define <vscale x 2 x i8> @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu66; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t67; CHECK-NEXT: ret68entry:69 %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8(70 <vscale x 2 x i8> %0,71 <vscale x 2 x i8> %1,72 <vscale x 2 x i8> %2,73 <vscale x 2 x i1> %3,74 iXLen %4, iXLen 1)75 76 ret <vscale x 2 x i8> %a77}78 79define <vscale x 4 x i8> @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {80; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma83; CHECK-NEXT: vmulh.vv v8, v8, v984; CHECK-NEXT: ret85entry:86 %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8(87 <vscale x 4 x i8> poison,88 <vscale x 4 x i8> %0,89 <vscale x 4 x i8> %1,90 iXLen %2)91 92 ret <vscale x 4 x i8> %a93}94 95define <vscale x 4 x i8> @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {96; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu99; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t100; CHECK-NEXT: ret101entry:102 %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8(103 <vscale x 4 x i8> %0,104 <vscale x 4 x i8> %1,105 <vscale x 4 x i8> %2,106 <vscale x 4 x i1> %3,107 iXLen %4, iXLen 1)108 109 ret <vscale x 4 x i8> %a110}111 112define <vscale x 8 x i8> @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {113; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma116; CHECK-NEXT: vmulh.vv v8, v8, v9117; CHECK-NEXT: ret118entry:119 %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8(120 <vscale x 8 x i8> poison,121 <vscale x 8 x i8> %0,122 <vscale x 8 x i8> %1,123 iXLen %2)124 125 ret <vscale x 8 x i8> %a126}127 128define <vscale x 8 x i8> @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {129; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu132; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t133; CHECK-NEXT: ret134entry:135 %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8(136 <vscale x 8 x i8> %0,137 <vscale x 8 x i8> %1,138 <vscale x 8 x i8> %2,139 <vscale x 8 x i1> %3,140 iXLen %4, iXLen 1)141 142 ret <vscale x 8 x i8> %a143}144 145define <vscale x 16 x i8> @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {146; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8:147; CHECK: # %bb.0: # %entry148; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma149; CHECK-NEXT: vmulh.vv v8, v8, v10150; CHECK-NEXT: ret151entry:152 %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8(153 <vscale x 16 x i8> poison,154 <vscale x 16 x i8> %0,155 <vscale x 16 x i8> %1,156 iXLen %2)157 158 ret <vscale x 16 x i8> %a159}160 161define <vscale x 16 x i8> @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {162; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu165; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t166; CHECK-NEXT: ret167entry:168 %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8(169 <vscale x 16 x i8> %0,170 <vscale x 16 x i8> %1,171 <vscale x 16 x i8> %2,172 <vscale x 16 x i1> %3,173 iXLen %4, iXLen 1)174 175 ret <vscale x 16 x i8> %a176}177 178define <vscale x 32 x i8> @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {179; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma182; CHECK-NEXT: vmulh.vv v8, v8, v12183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8(186 <vscale x 32 x i8> poison,187 <vscale x 32 x i8> %0,188 <vscale x 32 x i8> %1,189 iXLen %2)190 191 ret <vscale x 32 x i8> %a192}193 194define <vscale x 32 x i8> @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu198; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8(202 <vscale x 32 x i8> %0,203 <vscale x 32 x i8> %1,204 <vscale x 32 x i8> %2,205 <vscale x 32 x i1> %3,206 iXLen %4, iXLen 1)207 208 ret <vscale x 32 x i8> %a209}210 211define <vscale x 64 x i8> @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma215; CHECK-NEXT: vmulh.vv v8, v8, v16216; CHECK-NEXT: ret217entry:218 %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.nxv64i8(219 <vscale x 64 x i8> poison,220 <vscale x 64 x i8> %0,221 <vscale x 64 x i8> %1,222 iXLen %2)223 224 ret <vscale x 64 x i8> %a225}226 227define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {228; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: vl8r.v v24, (a0)231; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu232; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(236 <vscale x 64 x i8> %0,237 <vscale x 64 x i8> %1,238 <vscale x 64 x i8> %2,239 <vscale x 64 x i1> %3,240 iXLen %4, iXLen 1)241 242 ret <vscale x 64 x i8> %a243}244 245define <vscale x 1 x i16> @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma249; CHECK-NEXT: vmulh.vv v8, v8, v9250; CHECK-NEXT: ret251entry:252 %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16(253 <vscale x 1 x i16> poison,254 <vscale x 1 x i16> %0,255 <vscale x 1 x i16> %1,256 iXLen %2)257 258 ret <vscale x 1 x i16> %a259}260 261define <vscale x 1 x i16> @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {262; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16:263; CHECK: # %bb.0: # %entry264; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu265; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t266; CHECK-NEXT: ret267entry:268 %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16(269 <vscale x 1 x i16> %0,270 <vscale x 1 x i16> %1,271 <vscale x 1 x i16> %2,272 <vscale x 1 x i1> %3,273 iXLen %4, iXLen 1)274 275 ret <vscale x 1 x i16> %a276}277 278define <vscale x 2 x i16> @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {279; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16:280; CHECK: # %bb.0: # %entry281; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma282; CHECK-NEXT: vmulh.vv v8, v8, v9283; CHECK-NEXT: ret284entry:285 %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16(286 <vscale x 2 x i16> poison,287 <vscale x 2 x i16> %0,288 <vscale x 2 x i16> %1,289 iXLen %2)290 291 ret <vscale x 2 x i16> %a292}293 294define <vscale x 2 x i16> @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {295; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16:296; CHECK: # %bb.0: # %entry297; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu298; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t299; CHECK-NEXT: ret300entry:301 %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16(302 <vscale x 2 x i16> %0,303 <vscale x 2 x i16> %1,304 <vscale x 2 x i16> %2,305 <vscale x 2 x i1> %3,306 iXLen %4, iXLen 1)307 308 ret <vscale x 2 x i16> %a309}310 311define <vscale x 4 x i16> @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {312; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma315; CHECK-NEXT: vmulh.vv v8, v8, v9316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.nxv4i16(319 <vscale x 4 x i16> poison,320 <vscale x 4 x i16> %0,321 <vscale x 4 x i16> %1,322 iXLen %2)323 324 ret <vscale x 4 x i16> %a325}326 327define <vscale x 4 x i16> @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {328; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu331; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t332; CHECK-NEXT: ret333entry:334 %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16(335 <vscale x 4 x i16> %0,336 <vscale x 4 x i16> %1,337 <vscale x 4 x i16> %2,338 <vscale x 4 x i1> %3,339 iXLen %4, iXLen 1)340 341 ret <vscale x 4 x i16> %a342}343 344define <vscale x 8 x i16> @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {345; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma348; CHECK-NEXT: vmulh.vv v8, v8, v10349; CHECK-NEXT: ret350entry:351 %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.nxv8i16(352 <vscale x 8 x i16> poison,353 <vscale x 8 x i16> %0,354 <vscale x 8 x i16> %1,355 iXLen %2)356 357 ret <vscale x 8 x i16> %a358}359 360define <vscale x 8 x i16> @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {361; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16:362; CHECK: # %bb.0: # %entry363; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu364; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16(368 <vscale x 8 x i16> %0,369 <vscale x 8 x i16> %1,370 <vscale x 8 x i16> %2,371 <vscale x 8 x i1> %3,372 iXLen %4, iXLen 1)373 374 ret <vscale x 8 x i16> %a375}376 377define <vscale x 16 x i16> @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {378; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma381; CHECK-NEXT: vmulh.vv v8, v8, v12382; CHECK-NEXT: ret383entry:384 %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.nxv16i16(385 <vscale x 16 x i16> poison,386 <vscale x 16 x i16> %0,387 <vscale x 16 x i16> %1,388 iXLen %2)389 390 ret <vscale x 16 x i16> %a391}392 393define <vscale x 16 x i16> @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {394; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16:395; CHECK: # %bb.0: # %entry396; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu397; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t398; CHECK-NEXT: ret399entry:400 %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16(401 <vscale x 16 x i16> %0,402 <vscale x 16 x i16> %1,403 <vscale x 16 x i16> %2,404 <vscale x 16 x i1> %3,405 iXLen %4, iXLen 1)406 407 ret <vscale x 16 x i16> %a408}409 410define <vscale x 32 x i16> @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {411; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma414; CHECK-NEXT: vmulh.vv v8, v8, v16415; CHECK-NEXT: ret416entry:417 %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.nxv32i16(418 <vscale x 32 x i16> poison,419 <vscale x 32 x i16> %0,420 <vscale x 32 x i16> %1,421 iXLen %2)422 423 ret <vscale x 32 x i16> %a424}425 426define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {427; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: vl8re16.v v24, (a0)430; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu431; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t432; CHECK-NEXT: ret433entry:434 %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(435 <vscale x 32 x i16> %0,436 <vscale x 32 x i16> %1,437 <vscale x 32 x i16> %2,438 <vscale x 32 x i1> %3,439 iXLen %4, iXLen 1)440 441 ret <vscale x 32 x i16> %a442}443 444define <vscale x 1 x i32> @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {445; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32:446; CHECK: # %bb.0: # %entry447; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma448; CHECK-NEXT: vmulh.vv v8, v8, v9449; CHECK-NEXT: ret450entry:451 %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32(452 <vscale x 1 x i32> poison,453 <vscale x 1 x i32> %0,454 <vscale x 1 x i32> %1,455 iXLen %2)456 457 ret <vscale x 1 x i32> %a458}459 460define <vscale x 1 x i32> @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {461; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32:462; CHECK: # %bb.0: # %entry463; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu464; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t465; CHECK-NEXT: ret466entry:467 %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32(468 <vscale x 1 x i32> %0,469 <vscale x 1 x i32> %1,470 <vscale x 1 x i32> %2,471 <vscale x 1 x i1> %3,472 iXLen %4, iXLen 1)473 474 ret <vscale x 1 x i32> %a475}476 477define <vscale x 2 x i32> @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {478; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32:479; CHECK: # %bb.0: # %entry480; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma481; CHECK-NEXT: vmulh.vv v8, v8, v9482; CHECK-NEXT: ret483entry:484 %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32(485 <vscale x 2 x i32> poison,486 <vscale x 2 x i32> %0,487 <vscale x 2 x i32> %1,488 iXLen %2)489 490 ret <vscale x 2 x i32> %a491}492 493define <vscale x 2 x i32> @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {494; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32:495; CHECK: # %bb.0: # %entry496; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu497; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t498; CHECK-NEXT: ret499entry:500 %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32(501 <vscale x 2 x i32> %0,502 <vscale x 2 x i32> %1,503 <vscale x 2 x i32> %2,504 <vscale x 2 x i1> %3,505 iXLen %4, iXLen 1)506 507 ret <vscale x 2 x i32> %a508}509 510define <vscale x 4 x i32> @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {511; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32:512; CHECK: # %bb.0: # %entry513; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma514; CHECK-NEXT: vmulh.vv v8, v8, v10515; CHECK-NEXT: ret516entry:517 %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(518 <vscale x 4 x i32> poison,519 <vscale x 4 x i32> %0,520 <vscale x 4 x i32> %1,521 iXLen %2)522 523 ret <vscale x 4 x i32> %a524}525 526define <vscale x 4 x i32> @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {527; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32:528; CHECK: # %bb.0: # %entry529; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu530; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t531; CHECK-NEXT: ret532entry:533 %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32(534 <vscale x 4 x i32> %0,535 <vscale x 4 x i32> %1,536 <vscale x 4 x i32> %2,537 <vscale x 4 x i1> %3,538 iXLen %4, iXLen 1)539 540 ret <vscale x 4 x i32> %a541}542 543define <vscale x 8 x i32> @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {544; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma547; CHECK-NEXT: vmulh.vv v8, v8, v12548; CHECK-NEXT: ret549entry:550 %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.nxv8i32(551 <vscale x 8 x i32> poison,552 <vscale x 8 x i32> %0,553 <vscale x 8 x i32> %1,554 iXLen %2)555 556 ret <vscale x 8 x i32> %a557}558 559define <vscale x 8 x i32> @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {560; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32:561; CHECK: # %bb.0: # %entry562; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu563; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t564; CHECK-NEXT: ret565entry:566 %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32(567 <vscale x 8 x i32> %0,568 <vscale x 8 x i32> %1,569 <vscale x 8 x i32> %2,570 <vscale x 8 x i1> %3,571 iXLen %4, iXLen 1)572 573 ret <vscale x 8 x i32> %a574}575 576define <vscale x 16 x i32> @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {577; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32:578; CHECK: # %bb.0: # %entry579; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma580; CHECK-NEXT: vmulh.vv v8, v8, v16581; CHECK-NEXT: ret582entry:583 %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.nxv16i32(584 <vscale x 16 x i32> poison,585 <vscale x 16 x i32> %0,586 <vscale x 16 x i32> %1,587 iXLen %2)588 589 ret <vscale x 16 x i32> %a590}591 592define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {593; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32:594; CHECK: # %bb.0: # %entry595; CHECK-NEXT: vl8re32.v v24, (a0)596; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu597; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t598; CHECK-NEXT: ret599entry:600 %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(601 <vscale x 16 x i32> %0,602 <vscale x 16 x i32> %1,603 <vscale x 16 x i32> %2,604 <vscale x 16 x i1> %3,605 iXLen %4, iXLen 1)606 607 ret <vscale x 16 x i32> %a608}609 610define <vscale x 1 x i64> @intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {611; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64:612; CHECK: # %bb.0: # %entry613; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma614; CHECK-NEXT: vmulh.vv v8, v8, v9615; CHECK-NEXT: ret616entry:617 %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64(618 <vscale x 1 x i64> poison,619 <vscale x 1 x i64> %0,620 <vscale x 1 x i64> %1,621 iXLen %2)622 623 ret <vscale x 1 x i64> %a624}625 626define <vscale x 1 x i64> @intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {627; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64:628; CHECK: # %bb.0: # %entry629; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu630; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t631; CHECK-NEXT: ret632entry:633 %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64(634 <vscale x 1 x i64> %0,635 <vscale x 1 x i64> %1,636 <vscale x 1 x i64> %2,637 <vscale x 1 x i1> %3,638 iXLen %4, iXLen 1)639 640 ret <vscale x 1 x i64> %a641}642 643define <vscale x 2 x i64> @intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {644; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64:645; CHECK: # %bb.0: # %entry646; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma647; CHECK-NEXT: vmulh.vv v8, v8, v10648; CHECK-NEXT: ret649entry:650 %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64(651 <vscale x 2 x i64> poison,652 <vscale x 2 x i64> %0,653 <vscale x 2 x i64> %1,654 iXLen %2)655 656 ret <vscale x 2 x i64> %a657}658 659define <vscale x 2 x i64> @intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {660; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64:661; CHECK: # %bb.0: # %entry662; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu663; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t664; CHECK-NEXT: ret665entry:666 %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.nxv2i64(667 <vscale x 2 x i64> %0,668 <vscale x 2 x i64> %1,669 <vscale x 2 x i64> %2,670 <vscale x 2 x i1> %3,671 iXLen %4, iXLen 1)672 673 ret <vscale x 2 x i64> %a674}675 676define <vscale x 4 x i64> @intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {677; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64:678; CHECK: # %bb.0: # %entry679; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma680; CHECK-NEXT: vmulh.vv v8, v8, v12681; CHECK-NEXT: ret682entry:683 %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64(684 <vscale x 4 x i64> poison,685 <vscale x 4 x i64> %0,686 <vscale x 4 x i64> %1,687 iXLen %2)688 689 ret <vscale x 4 x i64> %a690}691 692define <vscale x 4 x i64> @intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {693; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64:694; CHECK: # %bb.0: # %entry695; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu696; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t697; CHECK-NEXT: ret698entry:699 %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.nxv4i64(700 <vscale x 4 x i64> %0,701 <vscale x 4 x i64> %1,702 <vscale x 4 x i64> %2,703 <vscale x 4 x i1> %3,704 iXLen %4, iXLen 1)705 706 ret <vscale x 4 x i64> %a707}708 709define <vscale x 8 x i64> @intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {710; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64:711; CHECK: # %bb.0: # %entry712; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma713; CHECK-NEXT: vmulh.vv v8, v8, v16714; CHECK-NEXT: ret715entry:716 %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64(717 <vscale x 8 x i64> poison,718 <vscale x 8 x i64> %0,719 <vscale x 8 x i64> %1,720 iXLen %2)721 722 ret <vscale x 8 x i64> %a723}724 725define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {726; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64:727; CHECK: # %bb.0: # %entry728; CHECK-NEXT: vl8re64.v v24, (a0)729; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu730; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t731; CHECK-NEXT: ret732entry:733 %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(734 <vscale x 8 x i64> %0,735 <vscale x 8 x i64> %1,736 <vscale x 8 x i64> %2,737 <vscale x 8 x i1> %3,738 iXLen %4, iXLen 1)739 740 ret <vscale x 8 x i64> %a741}742 743define <vscale x 1 x i8> @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {744; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8:745; CHECK: # %bb.0: # %entry746; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma747; CHECK-NEXT: vmulh.vx v8, v8, a0748; CHECK-NEXT: ret749entry:750 %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8(751 <vscale x 1 x i8> poison,752 <vscale x 1 x i8> %0,753 i8 %1,754 iXLen %2)755 756 ret <vscale x 1 x i8> %a757}758 759define <vscale x 1 x i8> @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {760; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8:761; CHECK: # %bb.0: # %entry762; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu763; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t764; CHECK-NEXT: ret765entry:766 %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8(767 <vscale x 1 x i8> %0,768 <vscale x 1 x i8> %1,769 i8 %2,770 <vscale x 1 x i1> %3,771 iXLen %4, iXLen 1)772 773 ret <vscale x 1 x i8> %a774}775 776define <vscale x 2 x i8> @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {777; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8:778; CHECK: # %bb.0: # %entry779; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma780; CHECK-NEXT: vmulh.vx v8, v8, a0781; CHECK-NEXT: ret782entry:783 %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8(784 <vscale x 2 x i8> poison,785 <vscale x 2 x i8> %0,786 i8 %1,787 iXLen %2)788 789 ret <vscale x 2 x i8> %a790}791 792define <vscale x 2 x i8> @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {793; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8:794; CHECK: # %bb.0: # %entry795; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu796; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t797; CHECK-NEXT: ret798entry:799 %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.i8(800 <vscale x 2 x i8> %0,801 <vscale x 2 x i8> %1,802 i8 %2,803 <vscale x 2 x i1> %3,804 iXLen %4, iXLen 1)805 806 ret <vscale x 2 x i8> %a807}808 809define <vscale x 4 x i8> @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {810; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8:811; CHECK: # %bb.0: # %entry812; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma813; CHECK-NEXT: vmulh.vx v8, v8, a0814; CHECK-NEXT: ret815entry:816 %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8(817 <vscale x 4 x i8> poison,818 <vscale x 4 x i8> %0,819 i8 %1,820 iXLen %2)821 822 ret <vscale x 4 x i8> %a823}824 825define <vscale x 4 x i8> @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {826; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8:827; CHECK: # %bb.0: # %entry828; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu829; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t830; CHECK-NEXT: ret831entry:832 %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.i8(833 <vscale x 4 x i8> %0,834 <vscale x 4 x i8> %1,835 i8 %2,836 <vscale x 4 x i1> %3,837 iXLen %4, iXLen 1)838 839 ret <vscale x 4 x i8> %a840}841 842define <vscale x 8 x i8> @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {843; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8:844; CHECK: # %bb.0: # %entry845; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma846; CHECK-NEXT: vmulh.vx v8, v8, a0847; CHECK-NEXT: ret848entry:849 %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8(850 <vscale x 8 x i8> poison,851 <vscale x 8 x i8> %0,852 i8 %1,853 iXLen %2)854 855 ret <vscale x 8 x i8> %a856}857 858define <vscale x 8 x i8> @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {859; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8:860; CHECK: # %bb.0: # %entry861; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu862; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t863; CHECK-NEXT: ret864entry:865 %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.i8(866 <vscale x 8 x i8> %0,867 <vscale x 8 x i8> %1,868 i8 %2,869 <vscale x 8 x i1> %3,870 iXLen %4, iXLen 1)871 872 ret <vscale x 8 x i8> %a873}874 875define <vscale x 16 x i8> @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {876; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8:877; CHECK: # %bb.0: # %entry878; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma879; CHECK-NEXT: vmulh.vx v8, v8, a0880; CHECK-NEXT: ret881entry:882 %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8(883 <vscale x 16 x i8> poison,884 <vscale x 16 x i8> %0,885 i8 %1,886 iXLen %2)887 888 ret <vscale x 16 x i8> %a889}890 891define <vscale x 16 x i8> @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {892; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8:893; CHECK: # %bb.0: # %entry894; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu895; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t896; CHECK-NEXT: ret897entry:898 %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.i8(899 <vscale x 16 x i8> %0,900 <vscale x 16 x i8> %1,901 i8 %2,902 <vscale x 16 x i1> %3,903 iXLen %4, iXLen 1)904 905 ret <vscale x 16 x i8> %a906}907 908define <vscale x 32 x i8> @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {909; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8:910; CHECK: # %bb.0: # %entry911; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma912; CHECK-NEXT: vmulh.vx v8, v8, a0913; CHECK-NEXT: ret914entry:915 %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8(916 <vscale x 32 x i8> poison,917 <vscale x 32 x i8> %0,918 i8 %1,919 iXLen %2)920 921 ret <vscale x 32 x i8> %a922}923 924define <vscale x 32 x i8> @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {925; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8:926; CHECK: # %bb.0: # %entry927; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu928; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t929; CHECK-NEXT: ret930entry:931 %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.i8(932 <vscale x 32 x i8> %0,933 <vscale x 32 x i8> %1,934 i8 %2,935 <vscale x 32 x i1> %3,936 iXLen %4, iXLen 1)937 938 ret <vscale x 32 x i8> %a939}940 941define <vscale x 64 x i8> @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {942; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8:943; CHECK: # %bb.0: # %entry944; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma945; CHECK-NEXT: vmulh.vx v8, v8, a0946; CHECK-NEXT: ret947entry:948 %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.i8(949 <vscale x 64 x i8> poison,950 <vscale x 64 x i8> %0,951 i8 %1,952 iXLen %2)953 954 ret <vscale x 64 x i8> %a955}956 957define <vscale x 64 x i8> @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {958; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8:959; CHECK: # %bb.0: # %entry960; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu961; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t962; CHECK-NEXT: ret963entry:964 %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.i8(965 <vscale x 64 x i8> %0,966 <vscale x 64 x i8> %1,967 i8 %2,968 <vscale x 64 x i1> %3,969 iXLen %4, iXLen 1)970 971 ret <vscale x 64 x i8> %a972}973 974define <vscale x 1 x i16> @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {975; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16:976; CHECK: # %bb.0: # %entry977; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma978; CHECK-NEXT: vmulh.vx v8, v8, a0979; CHECK-NEXT: ret980entry:981 %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16(982 <vscale x 1 x i16> poison,983 <vscale x 1 x i16> %0,984 i16 %1,985 iXLen %2)986 987 ret <vscale x 1 x i16> %a988}989 990define <vscale x 1 x i16> @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {991; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16:992; CHECK: # %bb.0: # %entry993; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu994; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t995; CHECK-NEXT: ret996entry:997 %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16(998 <vscale x 1 x i16> %0,999 <vscale x 1 x i16> %1,1000 i16 %2,1001 <vscale x 1 x i1> %3,1002 iXLen %4, iXLen 1)1003 1004 ret <vscale x 1 x i16> %a1005}1006 1007define <vscale x 2 x i16> @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1008; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16:1009; CHECK: # %bb.0: # %entry1010; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1011; CHECK-NEXT: vmulh.vx v8, v8, a01012; CHECK-NEXT: ret1013entry:1014 %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.i16(1015 <vscale x 2 x i16> poison,1016 <vscale x 2 x i16> %0,1017 i16 %1,1018 iXLen %2)1019 1020 ret <vscale x 2 x i16> %a1021}1022 1023define <vscale x 2 x i16> @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1024; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16:1025; CHECK: # %bb.0: # %entry1026; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1027; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t1028; CHECK-NEXT: ret1029entry:1030 %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.i16(1031 <vscale x 2 x i16> %0,1032 <vscale x 2 x i16> %1,1033 i16 %2,1034 <vscale x 2 x i1> %3,1035 iXLen %4, iXLen 1)1036 1037 ret <vscale x 2 x i16> %a1038}1039 1040define <vscale x 4 x i16> @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1041; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16:1042; CHECK: # %bb.0: # %entry1043; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1044; CHECK-NEXT: vmulh.vx v8, v8, a01045; CHECK-NEXT: ret1046entry:1047 %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.i16(1048 <vscale x 4 x i16> poison,1049 <vscale x 4 x i16> %0,1050 i16 %1,1051 iXLen %2)1052 1053 ret <vscale x 4 x i16> %a1054}1055 1056define <vscale x 4 x i16> @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1057; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16:1058; CHECK: # %bb.0: # %entry1059; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1060; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t1061; CHECK-NEXT: ret1062entry:1063 %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.i16(1064 <vscale x 4 x i16> %0,1065 <vscale x 4 x i16> %1,1066 i16 %2,1067 <vscale x 4 x i1> %3,1068 iXLen %4, iXLen 1)1069 1070 ret <vscale x 4 x i16> %a1071}1072 1073define <vscale x 8 x i16> @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1074; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16:1075; CHECK: # %bb.0: # %entry1076; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1077; CHECK-NEXT: vmulh.vx v8, v8, a01078; CHECK-NEXT: ret1079entry:1080 %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.i16(1081 <vscale x 8 x i16> poison,1082 <vscale x 8 x i16> %0,1083 i16 %1,1084 iXLen %2)1085 1086 ret <vscale x 8 x i16> %a1087}1088 1089define <vscale x 8 x i16> @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1090; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16:1091; CHECK: # %bb.0: # %entry1092; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1093; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t1094; CHECK-NEXT: ret1095entry:1096 %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.i16(1097 <vscale x 8 x i16> %0,1098 <vscale x 8 x i16> %1,1099 i16 %2,1100 <vscale x 8 x i1> %3,1101 iXLen %4, iXLen 1)1102 1103 ret <vscale x 8 x i16> %a1104}1105 1106define <vscale x 16 x i16> @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1107; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16:1108; CHECK: # %bb.0: # %entry1109; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1110; CHECK-NEXT: vmulh.vx v8, v8, a01111; CHECK-NEXT: ret1112entry:1113 %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.i16(1114 <vscale x 16 x i16> poison,1115 <vscale x 16 x i16> %0,1116 i16 %1,1117 iXLen %2)1118 1119 ret <vscale x 16 x i16> %a1120}1121 1122define <vscale x 16 x i16> @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1123; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16:1124; CHECK: # %bb.0: # %entry1125; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1126; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t1127; CHECK-NEXT: ret1128entry:1129 %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.i16(1130 <vscale x 16 x i16> %0,1131 <vscale x 16 x i16> %1,1132 i16 %2,1133 <vscale x 16 x i1> %3,1134 iXLen %4, iXLen 1)1135 1136 ret <vscale x 16 x i16> %a1137}1138 1139define <vscale x 32 x i16> @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1140; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16:1141; CHECK: # %bb.0: # %entry1142; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1143; CHECK-NEXT: vmulh.vx v8, v8, a01144; CHECK-NEXT: ret1145entry:1146 %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.i16(1147 <vscale x 32 x i16> poison,1148 <vscale x 32 x i16> %0,1149 i16 %1,1150 iXLen %2)1151 1152 ret <vscale x 32 x i16> %a1153}1154 1155define <vscale x 32 x i16> @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1156; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16:1157; CHECK: # %bb.0: # %entry1158; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1159; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t1160; CHECK-NEXT: ret1161entry:1162 %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.i16(1163 <vscale x 32 x i16> %0,1164 <vscale x 32 x i16> %1,1165 i16 %2,1166 <vscale x 32 x i1> %3,1167 iXLen %4, iXLen 1)1168 1169 ret <vscale x 32 x i16> %a1170}1171 1172define <vscale x 1 x i32> @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1173; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32:1174; CHECK: # %bb.0: # %entry1175; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1176; CHECK-NEXT: vmulh.vx v8, v8, a01177; CHECK-NEXT: ret1178entry:1179 %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32(1180 <vscale x 1 x i32> poison,1181 <vscale x 1 x i32> %0,1182 i32 %1,1183 iXLen %2)1184 1185 ret <vscale x 1 x i32> %a1186}1187 1188define <vscale x 1 x i32> @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1189; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32:1190; CHECK: # %bb.0: # %entry1191; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1192; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t1193; CHECK-NEXT: ret1194entry:1195 %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32(1196 <vscale x 1 x i32> %0,1197 <vscale x 1 x i32> %1,1198 i32 %2,1199 <vscale x 1 x i1> %3,1200 iXLen %4, iXLen 1)1201 1202 ret <vscale x 1 x i32> %a1203}1204 1205define <vscale x 2 x i32> @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1206; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32:1207; CHECK: # %bb.0: # %entry1208; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1209; CHECK-NEXT: vmulh.vx v8, v8, a01210; CHECK-NEXT: ret1211entry:1212 %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.i32(1213 <vscale x 2 x i32> poison,1214 <vscale x 2 x i32> %0,1215 i32 %1,1216 iXLen %2)1217 1218 ret <vscale x 2 x i32> %a1219}1220 1221define <vscale x 2 x i32> @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1222; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32:1223; CHECK: # %bb.0: # %entry1224; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1225; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t1226; CHECK-NEXT: ret1227entry:1228 %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.i32(1229 <vscale x 2 x i32> %0,1230 <vscale x 2 x i32> %1,1231 i32 %2,1232 <vscale x 2 x i1> %3,1233 iXLen %4, iXLen 1)1234 1235 ret <vscale x 2 x i32> %a1236}1237 1238define <vscale x 4 x i32> @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1239; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32:1240; CHECK: # %bb.0: # %entry1241; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1242; CHECK-NEXT: vmulh.vx v8, v8, a01243; CHECK-NEXT: ret1244entry:1245 %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.i32(1246 <vscale x 4 x i32> poison,1247 <vscale x 4 x i32> %0,1248 i32 %1,1249 iXLen %2)1250 1251 ret <vscale x 4 x i32> %a1252}1253 1254define <vscale x 4 x i32> @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1255; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32:1256; CHECK: # %bb.0: # %entry1257; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1258; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t1259; CHECK-NEXT: ret1260entry:1261 %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.i32(1262 <vscale x 4 x i32> %0,1263 <vscale x 4 x i32> %1,1264 i32 %2,1265 <vscale x 4 x i1> %3,1266 iXLen %4, iXLen 1)1267 1268 ret <vscale x 4 x i32> %a1269}1270 1271define <vscale x 8 x i32> @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1272; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32:1273; CHECK: # %bb.0: # %entry1274; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1275; CHECK-NEXT: vmulh.vx v8, v8, a01276; CHECK-NEXT: ret1277entry:1278 %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.i32(1279 <vscale x 8 x i32> poison,1280 <vscale x 8 x i32> %0,1281 i32 %1,1282 iXLen %2)1283 1284 ret <vscale x 8 x i32> %a1285}1286 1287define <vscale x 8 x i32> @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1288; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32:1289; CHECK: # %bb.0: # %entry1290; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1291; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t1292; CHECK-NEXT: ret1293entry:1294 %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.i32(1295 <vscale x 8 x i32> %0,1296 <vscale x 8 x i32> %1,1297 i32 %2,1298 <vscale x 8 x i1> %3,1299 iXLen %4, iXLen 1)1300 1301 ret <vscale x 8 x i32> %a1302}1303 1304define <vscale x 16 x i32> @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1305; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32:1306; CHECK: # %bb.0: # %entry1307; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1308; CHECK-NEXT: vmulh.vx v8, v8, a01309; CHECK-NEXT: ret1310entry:1311 %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.i32(1312 <vscale x 16 x i32> poison,1313 <vscale x 16 x i32> %0,1314 i32 %1,1315 iXLen %2)1316 1317 ret <vscale x 16 x i32> %a1318}1319 1320define <vscale x 16 x i32> @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1321; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32:1322; CHECK: # %bb.0: # %entry1323; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu1324; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t1325; CHECK-NEXT: ret1326entry:1327 %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.i32(1328 <vscale x 16 x i32> %0,1329 <vscale x 16 x i32> %1,1330 i32 %2,1331 <vscale x 16 x i1> %3,1332 iXLen %4, iXLen 1)1333 1334 ret <vscale x 16 x i32> %a1335}1336 1337define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1338; RV32-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:1339; RV32: # %bb.0: # %entry1340; RV32-NEXT: addi sp, sp, -161341; RV32-NEXT: sw a0, 8(sp)1342; RV32-NEXT: sw a1, 12(sp)1343; RV32-NEXT: addi a0, sp, 81344; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1345; RV32-NEXT: vlse64.v v9, (a0), zero1346; RV32-NEXT: vmulh.vv v8, v8, v91347; RV32-NEXT: addi sp, sp, 161348; RV32-NEXT: ret1349;1350; RV64-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:1351; RV64: # %bb.0: # %entry1352; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1353; RV64-NEXT: vmulh.vx v8, v8, a01354; RV64-NEXT: ret1355entry:1356 %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(1357 <vscale x 1 x i64> poison,1358 <vscale x 1 x i64> %0,1359 i64 %1,1360 iXLen %2)1361 1362 ret <vscale x 1 x i64> %a1363}1364 1365define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1366; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:1367; RV32: # %bb.0: # %entry1368; RV32-NEXT: addi sp, sp, -161369; RV32-NEXT: sw a0, 8(sp)1370; RV32-NEXT: sw a1, 12(sp)1371; RV32-NEXT: addi a0, sp, 81372; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu1373; RV32-NEXT: vlse64.v v10, (a0), zero1374; RV32-NEXT: vmulh.vv v8, v9, v10, v0.t1375; RV32-NEXT: addi sp, sp, 161376; RV32-NEXT: ret1377;1378; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:1379; RV64: # %bb.0: # %entry1380; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu1381; RV64-NEXT: vmulh.vx v8, v9, a0, v0.t1382; RV64-NEXT: ret1383entry:1384 %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(1385 <vscale x 1 x i64> %0,1386 <vscale x 1 x i64> %1,1387 i64 %2,1388 <vscale x 1 x i1> %3,1389 iXLen %4, iXLen 1)1390 1391 ret <vscale x 1 x i64> %a1392}1393 1394define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1395; RV32-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:1396; RV32: # %bb.0: # %entry1397; RV32-NEXT: addi sp, sp, -161398; RV32-NEXT: sw a0, 8(sp)1399; RV32-NEXT: sw a1, 12(sp)1400; RV32-NEXT: addi a0, sp, 81401; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1402; RV32-NEXT: vlse64.v v10, (a0), zero1403; RV32-NEXT: vmulh.vv v8, v8, v101404; RV32-NEXT: addi sp, sp, 161405; RV32-NEXT: ret1406;1407; RV64-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:1408; RV64: # %bb.0: # %entry1409; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1410; RV64-NEXT: vmulh.vx v8, v8, a01411; RV64-NEXT: ret1412entry:1413 %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(1414 <vscale x 2 x i64> poison,1415 <vscale x 2 x i64> %0,1416 i64 %1,1417 iXLen %2)1418 1419 ret <vscale x 2 x i64> %a1420}1421 1422define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1423; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:1424; RV32: # %bb.0: # %entry1425; RV32-NEXT: addi sp, sp, -161426; RV32-NEXT: sw a0, 8(sp)1427; RV32-NEXT: sw a1, 12(sp)1428; RV32-NEXT: addi a0, sp, 81429; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu1430; RV32-NEXT: vlse64.v v12, (a0), zero1431; RV32-NEXT: vmulh.vv v8, v10, v12, v0.t1432; RV32-NEXT: addi sp, sp, 161433; RV32-NEXT: ret1434;1435; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:1436; RV64: # %bb.0: # %entry1437; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu1438; RV64-NEXT: vmulh.vx v8, v10, a0, v0.t1439; RV64-NEXT: ret1440entry:1441 %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(1442 <vscale x 2 x i64> %0,1443 <vscale x 2 x i64> %1,1444 i64 %2,1445 <vscale x 2 x i1> %3,1446 iXLen %4, iXLen 1)1447 1448 ret <vscale x 2 x i64> %a1449}1450 1451define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1452; RV32-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:1453; RV32: # %bb.0: # %entry1454; RV32-NEXT: addi sp, sp, -161455; RV32-NEXT: sw a0, 8(sp)1456; RV32-NEXT: sw a1, 12(sp)1457; RV32-NEXT: addi a0, sp, 81458; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1459; RV32-NEXT: vlse64.v v12, (a0), zero1460; RV32-NEXT: vmulh.vv v8, v8, v121461; RV32-NEXT: addi sp, sp, 161462; RV32-NEXT: ret1463;1464; RV64-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:1465; RV64: # %bb.0: # %entry1466; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1467; RV64-NEXT: vmulh.vx v8, v8, a01468; RV64-NEXT: ret1469entry:1470 %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(1471 <vscale x 4 x i64> poison,1472 <vscale x 4 x i64> %0,1473 i64 %1,1474 iXLen %2)1475 1476 ret <vscale x 4 x i64> %a1477}1478 1479define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1480; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:1481; RV32: # %bb.0: # %entry1482; RV32-NEXT: addi sp, sp, -161483; RV32-NEXT: sw a0, 8(sp)1484; RV32-NEXT: sw a1, 12(sp)1485; RV32-NEXT: addi a0, sp, 81486; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu1487; RV32-NEXT: vlse64.v v16, (a0), zero1488; RV32-NEXT: vmulh.vv v8, v12, v16, v0.t1489; RV32-NEXT: addi sp, sp, 161490; RV32-NEXT: ret1491;1492; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:1493; RV64: # %bb.0: # %entry1494; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu1495; RV64-NEXT: vmulh.vx v8, v12, a0, v0.t1496; RV64-NEXT: ret1497entry:1498 %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(1499 <vscale x 4 x i64> %0,1500 <vscale x 4 x i64> %1,1501 i64 %2,1502 <vscale x 4 x i1> %3,1503 iXLen %4, iXLen 1)1504 1505 ret <vscale x 4 x i64> %a1506}1507 1508define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1509; RV32-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:1510; RV32: # %bb.0: # %entry1511; RV32-NEXT: addi sp, sp, -161512; RV32-NEXT: sw a0, 8(sp)1513; RV32-NEXT: sw a1, 12(sp)1514; RV32-NEXT: addi a0, sp, 81515; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1516; RV32-NEXT: vlse64.v v16, (a0), zero1517; RV32-NEXT: vmulh.vv v8, v8, v161518; RV32-NEXT: addi sp, sp, 161519; RV32-NEXT: ret1520;1521; RV64-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:1522; RV64: # %bb.0: # %entry1523; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1524; RV64-NEXT: vmulh.vx v8, v8, a01525; RV64-NEXT: ret1526entry:1527 %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(1528 <vscale x 8 x i64> poison,1529 <vscale x 8 x i64> %0,1530 i64 %1,1531 iXLen %2)1532 1533 ret <vscale x 8 x i64> %a1534}1535 1536define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1537; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:1538; RV32: # %bb.0: # %entry1539; RV32-NEXT: addi sp, sp, -161540; RV32-NEXT: sw a0, 8(sp)1541; RV32-NEXT: sw a1, 12(sp)1542; RV32-NEXT: addi a0, sp, 81543; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu1544; RV32-NEXT: vlse64.v v24, (a0), zero1545; RV32-NEXT: vmulh.vv v8, v16, v24, v0.t1546; RV32-NEXT: addi sp, sp, 161547; RV32-NEXT: ret1548;1549; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:1550; RV64: # %bb.0: # %entry1551; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu1552; RV64-NEXT: vmulh.vx v8, v16, a0, v0.t1553; RV64-NEXT: ret1554entry:1555 %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(1556 <vscale x 8 x i64> %0,1557 <vscale x 8 x i64> %1,1558 i64 %2,1559 <vscale x 8 x i1> %3,1560 iXLen %4, iXLen 1)1561 1562 ret <vscale x 8 x i64> %a1563}1564