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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {6; CHECK-LABEL: vmulhu_vv_nxv1i32:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma9; CHECK-NEXT: vmulhu.vv v8, v9, v810; CHECK-NEXT: ret11 %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>12 %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>13 %ve = mul <vscale x 1 x i64> %vc, %vd14 %vf = lshr <vscale x 1 x i64> %ve, splat (i64 32)15 %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>16 ret <vscale x 1 x i32> %vg17}18 19define <vscale x 1 x i32> @vmulhu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {20; CHECK-LABEL: vmulhu_vx_nxv1i32:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma23; CHECK-NEXT: vmulhu.vx v8, v8, a024; CHECK-NEXT: ret25 %head1 = insertelement <vscale x 1 x i32> poison, i32 %x, i32 026 %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer27 %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>28 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>29 %vd = mul <vscale x 1 x i64> %vb, %vc30 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)31 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>32 ret <vscale x 1 x i32> %vf33}34 35define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {36; CHECK-LABEL: vmulhu_vi_nxv1i32_0:37; CHECK: # %bb.0:38; CHECK-NEXT: li a0, -739; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma40; CHECK-NEXT: vmulhu.vx v8, v8, a041; CHECK-NEXT: ret42 %vb = zext <vscale x 1 x i32> splat (i32 -7) to <vscale x 1 x i64>43 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>44 %vd = mul <vscale x 1 x i64> %vb, %vc45 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)46 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>47 ret <vscale x 1 x i32> %vf48}49 50define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {51; RV32-LABEL: vmulhu_vi_nxv1i32_1:52; RV32: # %bb.0:53; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma54; RV32-NEXT: vsrl.vi v8, v8, 2855; RV32-NEXT: ret56;57; RV64-LABEL: vmulhu_vi_nxv1i32_1:58; RV64: # %bb.0:59; RV64-NEXT: li a0, 1660; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma61; RV64-NEXT: vmulhu.vx v8, v8, a062; RV64-NEXT: ret63 %vb = zext <vscale x 1 x i32> splat (i32 16) to <vscale x 1 x i64>64 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>65 %vd = mul <vscale x 1 x i64> %vb, %vc66 %ve = lshr <vscale x 1 x i64> %vd, splat (i64 32)67 %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>68 ret <vscale x 1 x i32> %vf69}70 71define <vscale x 2 x i32> @vmulhu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {72; CHECK-LABEL: vmulhu_vv_nxv2i32:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma75; CHECK-NEXT: vmulhu.vv v8, v9, v876; CHECK-NEXT: ret77 %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>78 %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>79 %ve = mul <vscale x 2 x i64> %vc, %vd80 %vf = lshr <vscale x 2 x i64> %ve, splat (i64 32)81 %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>82 ret <vscale x 2 x i32> %vg83}84 85define <vscale x 2 x i32> @vmulhu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {86; CHECK-LABEL: vmulhu_vx_nxv2i32:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma89; CHECK-NEXT: vmulhu.vx v8, v8, a090; CHECK-NEXT: ret91 %head1 = insertelement <vscale x 2 x i32> poison, i32 %x, i32 092 %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer93 %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>94 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>95 %vd = mul <vscale x 2 x i64> %vb, %vc96 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)97 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>98 ret <vscale x 2 x i32> %vf99}100 101define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {102; CHECK-LABEL: vmulhu_vi_nxv2i32_0:103; CHECK: # %bb.0:104; CHECK-NEXT: li a0, -7105; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma106; CHECK-NEXT: vmulhu.vx v8, v8, a0107; CHECK-NEXT: ret108 %vb = zext <vscale x 2 x i32> splat (i32 -7) to <vscale x 2 x i64>109 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>110 %vd = mul <vscale x 2 x i64> %vb, %vc111 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)112 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>113 ret <vscale x 2 x i32> %vf114}115 116define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {117; RV32-LABEL: vmulhu_vi_nxv2i32_1:118; RV32: # %bb.0:119; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma120; RV32-NEXT: vsrl.vi v8, v8, 28121; RV32-NEXT: ret122;123; RV64-LABEL: vmulhu_vi_nxv2i32_1:124; RV64: # %bb.0:125; RV64-NEXT: li a0, 16126; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma127; RV64-NEXT: vmulhu.vx v8, v8, a0128; RV64-NEXT: ret129 %vb = zext <vscale x 2 x i32> splat (i32 16) to <vscale x 2 x i64>130 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>131 %vd = mul <vscale x 2 x i64> %vb, %vc132 %ve = lshr <vscale x 2 x i64> %vd, splat (i64 32)133 %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>134 ret <vscale x 2 x i32> %vf135}136 137define <vscale x 4 x i32> @vmulhu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {138; CHECK-LABEL: vmulhu_vv_nxv4i32:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma141; CHECK-NEXT: vmulhu.vv v8, v10, v8142; CHECK-NEXT: ret143 %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>144 %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>145 %ve = mul <vscale x 4 x i64> %vc, %vd146 %vf = lshr <vscale x 4 x i64> %ve, splat (i64 32)147 %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>148 ret <vscale x 4 x i32> %vg149}150 151define <vscale x 4 x i32> @vmulhu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {152; CHECK-LABEL: vmulhu_vx_nxv4i32:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma155; CHECK-NEXT: vmulhu.vx v8, v8, a0156; CHECK-NEXT: ret157 %head1 = insertelement <vscale x 4 x i32> poison, i32 %x, i32 0158 %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer159 %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>160 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>161 %vd = mul <vscale x 4 x i64> %vb, %vc162 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)163 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>164 ret <vscale x 4 x i32> %vf165}166 167define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {168; CHECK-LABEL: vmulhu_vi_nxv4i32_0:169; CHECK: # %bb.0:170; CHECK-NEXT: li a0, -7171; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma172; CHECK-NEXT: vmulhu.vx v8, v8, a0173; CHECK-NEXT: ret174 %vb = zext <vscale x 4 x i32> splat (i32 -7) to <vscale x 4 x i64>175 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>176 %vd = mul <vscale x 4 x i64> %vb, %vc177 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)178 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>179 ret <vscale x 4 x i32> %vf180}181 182define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {183; RV32-LABEL: vmulhu_vi_nxv4i32_1:184; RV32: # %bb.0:185; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma186; RV32-NEXT: vsrl.vi v8, v8, 28187; RV32-NEXT: ret188;189; RV64-LABEL: vmulhu_vi_nxv4i32_1:190; RV64: # %bb.0:191; RV64-NEXT: li a0, 16192; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma193; RV64-NEXT: vmulhu.vx v8, v8, a0194; RV64-NEXT: ret195 %vb = zext <vscale x 4 x i32> splat (i32 16) to <vscale x 4 x i64>196 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>197 %vd = mul <vscale x 4 x i64> %vb, %vc198 %ve = lshr <vscale x 4 x i64> %vd, splat (i64 32)199 %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>200 ret <vscale x 4 x i32> %vf201}202 203define <vscale x 8 x i32> @vmulhu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {204; CHECK-LABEL: vmulhu_vv_nxv8i32:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma207; CHECK-NEXT: vmulhu.vv v8, v12, v8208; CHECK-NEXT: ret209 %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>210 %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>211 %ve = mul <vscale x 8 x i64> %vc, %vd212 %vf = lshr <vscale x 8 x i64> %ve, splat (i64 32)213 %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>214 ret <vscale x 8 x i32> %vg215}216 217define <vscale x 8 x i32> @vmulhu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {218; CHECK-LABEL: vmulhu_vx_nxv8i32:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma221; CHECK-NEXT: vmulhu.vx v8, v8, a0222; CHECK-NEXT: ret223 %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0224 %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer225 %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>226 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>227 %vd = mul <vscale x 8 x i64> %vb, %vc228 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)229 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>230 ret <vscale x 8 x i32> %vf231}232 233define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {234; CHECK-LABEL: vmulhu_vi_nxv8i32_0:235; CHECK: # %bb.0:236; CHECK-NEXT: li a0, -7237; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma238; CHECK-NEXT: vmulhu.vx v8, v8, a0239; CHECK-NEXT: ret240 %vb = zext <vscale x 8 x i32> splat (i32 -7) to <vscale x 8 x i64>241 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>242 %vd = mul <vscale x 8 x i64> %vb, %vc243 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)244 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>245 ret <vscale x 8 x i32> %vf246}247 248define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {249; RV32-LABEL: vmulhu_vi_nxv8i32_1:250; RV32: # %bb.0:251; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma252; RV32-NEXT: vsrl.vi v8, v8, 28253; RV32-NEXT: ret254;255; RV64-LABEL: vmulhu_vi_nxv8i32_1:256; RV64: # %bb.0:257; RV64-NEXT: li a0, 16258; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma259; RV64-NEXT: vmulhu.vx v8, v8, a0260; RV64-NEXT: ret261 %vb = zext <vscale x 8 x i32> splat (i32 16) to <vscale x 8 x i64>262 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>263 %vd = mul <vscale x 8 x i64> %vb, %vc264 %ve = lshr <vscale x 8 x i64> %vd, splat (i64 32)265 %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>266 ret <vscale x 8 x i32> %vf267}268