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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vmv.s.x_x_nxv1i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma11; CHECK-NEXT: vmv.s.x v8, a012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2)15 ret <vscale x 1 x i8> %a16}17 18define <vscale x 2 x i8> @intrinsic_vmv.s.x_x_nxv2i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {19; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma22; CHECK-NEXT: vmv.s.x v8, a023; CHECK-NEXT: ret24entry:25 %a = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2)26 ret <vscale x 2 x i8> %a27}28 29define <vscale x 4 x i8> @intrinsic_vmv.s.x_x_nxv4i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {30; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma33; CHECK-NEXT: vmv.s.x v8, a034; CHECK-NEXT: ret35entry:36 %a = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2)37 ret <vscale x 4 x i8> %a38}39 40define <vscale x 8 x i8> @intrinsic_vmv.s.x_x_nxv8i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma44; CHECK-NEXT: vmv.s.x v8, a045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2)48 ret <vscale x 8 x i8> %a49}50 51define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {52; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma55; CHECK-NEXT: vmv.s.x v8, a056; CHECK-NEXT: ret57entry:58 %a = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2)59 ret <vscale x 16 x i8> %a60}61 62define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {63; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma66; CHECK-NEXT: vmv.s.x v8, a067; CHECK-NEXT: ret68entry:69 %a = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2)70 ret <vscale x 32 x i8> %a71}72 73define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma77; CHECK-NEXT: vmv.s.x v8, a078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2)81 ret <vscale x 64 x i8> %a82}83 84define <vscale x 1 x i16> @intrinsic_vmv.s.x_x_nxv1i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {85; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma88; CHECK-NEXT: vmv.s.x v8, a089; CHECK-NEXT: ret90entry:91 %a = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2)92 ret <vscale x 1 x i16> %a93}94 95define <vscale x 2 x i16> @intrinsic_vmv.s.x_x_nxv2i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {96; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma99; CHECK-NEXT: vmv.s.x v8, a0100; CHECK-NEXT: ret101entry:102 %a = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2)103 ret <vscale x 2 x i16> %a104}105 106define <vscale x 4 x i16> @intrinsic_vmv.s.x_x_nxv4i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma110; CHECK-NEXT: vmv.s.x v8, a0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2)114 ret <vscale x 4 x i16> %a115}116 117define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {118; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma121; CHECK-NEXT: vmv.s.x v8, a0122; CHECK-NEXT: ret123entry:124 %a = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2)125 ret <vscale x 8 x i16> %a126}127 128define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {129; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma132; CHECK-NEXT: vmv.s.x v8, a0133; CHECK-NEXT: ret134entry:135 %a = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2)136 ret <vscale x 16 x i16> %a137}138 139define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma143; CHECK-NEXT: vmv.s.x v8, a0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2)147 ret <vscale x 32 x i16> %a148}149 150define <vscale x 1 x i32> @intrinsic_vmv.s.x_x_nxv1i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {151; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma154; CHECK-NEXT: vmv.s.x v8, a0155; CHECK-NEXT: ret156entry:157 %a = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2)158 ret <vscale x 1 x i32> %a159}160 161define <vscale x 2 x i32> @intrinsic_vmv.s.x_x_nxv2i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma165; CHECK-NEXT: vmv.s.x v8, a0166; CHECK-NEXT: ret167entry:168 %a = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2)169 ret <vscale x 2 x i32> %a170}171 172define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma176; CHECK-NEXT: vmv.s.x v8, a0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2)180 ret <vscale x 4 x i32> %a181}182 183define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {184; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma187; CHECK-NEXT: vmv.s.x v8, a0188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2)191 ret <vscale x 8 x i32> %a192}193 194define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {195; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma198; CHECK-NEXT: vmv.s.x v8, a0199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2)202 ret <vscale x 16 x i32> %a203}204 205define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {206; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64:207; RV32: # %bb.0: # %entry208; RV32-NEXT: addi sp, sp, -16209; RV32-NEXT: sw a0, 8(sp)210; RV32-NEXT: sw a1, 12(sp)211; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu212; RV32-NEXT: vid.v v9213; RV32-NEXT: vmseq.vi v0, v9, 0214; RV32-NEXT: addi a0, sp, 8215; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t216; RV32-NEXT: addi sp, sp, 16217; RV32-NEXT: ret218;219; RV64-LABEL: intrinsic_vmv.s.x_x_nxv1i64:220; RV64: # %bb.0: # %entry221; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma222; RV64-NEXT: vmv.s.x v8, a0223; RV64-NEXT: ret224entry:225 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2)226 ret <vscale x 1 x i64> %a227}228 229define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {230; RV32-LABEL: intrinsic_vmv.s.x_x_nxv2i64:231; RV32: # %bb.0: # %entry232; RV32-NEXT: addi sp, sp, -16233; RV32-NEXT: sw a0, 8(sp)234; RV32-NEXT: sw a1, 12(sp)235; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu236; RV32-NEXT: vid.v v10237; RV32-NEXT: vmseq.vi v0, v10, 0238; RV32-NEXT: addi a0, sp, 8239; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t240; RV32-NEXT: addi sp, sp, 16241; RV32-NEXT: ret242;243; RV64-LABEL: intrinsic_vmv.s.x_x_nxv2i64:244; RV64: # %bb.0: # %entry245; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma246; RV64-NEXT: vmv.s.x v8, a0247; RV64-NEXT: ret248entry:249 %a = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2)250 ret <vscale x 2 x i64> %a251}252 253define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {254; RV32-LABEL: intrinsic_vmv.s.x_x_nxv4i64:255; RV32: # %bb.0: # %entry256; RV32-NEXT: addi sp, sp, -16257; RV32-NEXT: sw a0, 8(sp)258; RV32-NEXT: sw a1, 12(sp)259; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu260; RV32-NEXT: vid.v v12261; RV32-NEXT: vmseq.vi v0, v12, 0262; RV32-NEXT: addi a0, sp, 8263; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t264; RV32-NEXT: addi sp, sp, 16265; RV32-NEXT: ret266;267; RV64-LABEL: intrinsic_vmv.s.x_x_nxv4i64:268; RV64: # %bb.0: # %entry269; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma270; RV64-NEXT: vmv.s.x v8, a0271; RV64-NEXT: ret272entry:273 %a = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2)274 ret <vscale x 4 x i64> %a275}276 277define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {278; RV32-LABEL: intrinsic_vmv.s.x_x_nxv8i64:279; RV32: # %bb.0: # %entry280; RV32-NEXT: addi sp, sp, -16281; RV32-NEXT: sw a0, 8(sp)282; RV32-NEXT: sw a1, 12(sp)283; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu284; RV32-NEXT: vid.v v16285; RV32-NEXT: vmseq.vi v0, v16, 0286; RV32-NEXT: addi a0, sp, 8287; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t288; RV32-NEXT: addi sp, sp, 16289; RV32-NEXT: ret290;291; RV64-LABEL: intrinsic_vmv.s.x_x_nxv8i64:292; RV64: # %bb.0: # %entry293; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma294; RV64-NEXT: vmv.s.x v8, a0295; RV64-NEXT: ret296entry:297 %a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2)298 ret <vscale x 8 x i64> %a299}300 301; We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x302define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64_bug(<vscale x 1 x i64> %0, ptr %1) nounwind {303; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:304; RV32: # %bb.0: # %entry305; RV32-NEXT: addi sp, sp, -16306; RV32-NEXT: lw a1, 0(a0)307; RV32-NEXT: lw a0, 4(a0)308; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu309; RV32-NEXT: vid.v v9310; RV32-NEXT: vmseq.vi v0, v9, 0311; RV32-NEXT: sw a1, 8(sp)312; RV32-NEXT: sw a0, 12(sp)313; RV32-NEXT: addi a0, sp, 8314; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t315; RV32-NEXT: addi sp, sp, 16316; RV32-NEXT: ret317;318; RV64-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:319; RV64: # %bb.0: # %entry320; RV64-NEXT: ld a0, 0(a0)321; RV64-NEXT: vsetivli zero, 1, e64, m1, tu, ma322; RV64-NEXT: vmv.s.x v8, a0323; RV64-NEXT: ret324entry:325 %a = load i64, ptr %1, align 8326 %b = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %a, iXLen 1)327 ret <vscale x 1 x i64> %b328}329