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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma11; CHECK-NEXT: vmv.v.v v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 iXLen %2)18 19 ret <vscale x 1 x i8> %a20}21 22define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {23; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma26; CHECK-NEXT: vmv.v.v v8, v927; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(30 <vscale x 2 x i8> %0,31 <vscale x 2 x i8> %1,32 iXLen %2)33 34 ret <vscale x 2 x i8> %a35}36 37define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {38; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma41; CHECK-NEXT: vmv.v.v v8, v942; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(45 <vscale x 4 x i8> %0,46 <vscale x 4 x i8> %1,47 iXLen %2)48 49 ret <vscale x 4 x i8> %a50}51 52define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {53; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma56; CHECK-NEXT: vmv.v.v v8, v957; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(60 <vscale x 8 x i8> %0,61 <vscale x 8 x i8> %1,62 iXLen %2)63 64 ret <vscale x 8 x i8> %a65}66 67define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {68; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma71; CHECK-NEXT: vmv.v.v v8, v1072; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(75 <vscale x 16 x i8> %0,76 <vscale x 16 x i8> %1,77 iXLen %2)78 79 ret <vscale x 16 x i8> %a80}81 82define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {83; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma86; CHECK-NEXT: vmv.v.v v8, v1287; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(90 <vscale x 32 x i8> %0,91 <vscale x 32 x i8> %1,92 iXLen %2)93 94 ret <vscale x 32 x i8> %a95}96 97define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {98; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma101; CHECK-NEXT: vmv.v.v v8, v16102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(105 <vscale x 64 x i8> %0,106 <vscale x 64 x i8> %1,107 iXLen %2)108 109 ret <vscale x 64 x i8> %a110}111 112define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {113; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma116; CHECK-NEXT: vmv.v.v v8, v9117; CHECK-NEXT: ret118entry:119 %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(120 <vscale x 1 x i16> %0,121 <vscale x 1 x i16> %1,122 iXLen %2)123 124 ret <vscale x 1 x i16> %a125}126 127define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {128; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma131; CHECK-NEXT: vmv.v.v v8, v9132; CHECK-NEXT: ret133entry:134 %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(135 <vscale x 2 x i16> %0,136 <vscale x 2 x i16> %1,137 iXLen %2)138 139 ret <vscale x 2 x i16> %a140}141 142define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {143; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma146; CHECK-NEXT: vmv.v.v v8, v9147; CHECK-NEXT: ret148entry:149 %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(150 <vscale x 4 x i16> %0,151 <vscale x 4 x i16> %1,152 iXLen %2)153 154 ret <vscale x 4 x i16> %a155}156 157define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {158; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma161; CHECK-NEXT: vmv.v.v v8, v10162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(165 <vscale x 8 x i16> %0,166 <vscale x 8 x i16> %1,167 iXLen %2)168 169 ret <vscale x 8 x i16> %a170}171 172define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma176; CHECK-NEXT: vmv.v.v v8, v12177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(180 <vscale x 16 x i16> %0,181 <vscale x 16 x i16> %1,182 iXLen %2)183 184 ret <vscale x 16 x i16> %a185}186 187define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {188; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma191; CHECK-NEXT: vmv.v.v v8, v16192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(195 <vscale x 32 x i16> %0,196 <vscale x 32 x i16> %1,197 iXLen %2)198 199 ret <vscale x 32 x i16> %a200}201 202define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma206; CHECK-NEXT: vmv.v.v v8, v9207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(210 <vscale x 1 x i32> %0,211 <vscale x 1 x i32> %1,212 iXLen %2)213 214 ret <vscale x 1 x i32> %a215}216 217define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {218; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma221; CHECK-NEXT: vmv.v.v v8, v9222; CHECK-NEXT: ret223entry:224 %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(225 <vscale x 2 x i32> %0,226 <vscale x 2 x i32> %1,227 iXLen %2)228 229 ret <vscale x 2 x i32> %a230}231 232define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {233; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32:234; CHECK: # %bb.0: # %entry235; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma236; CHECK-NEXT: vmv.v.v v8, v10237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(240 <vscale x 4 x i32> %0,241 <vscale x 4 x i32> %1,242 iXLen %2)243 244 ret <vscale x 4 x i32> %a245}246 247define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {248; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma251; CHECK-NEXT: vmv.v.v v8, v12252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(255 <vscale x 8 x i32> %0,256 <vscale x 8 x i32> %1,257 iXLen %2)258 259 ret <vscale x 8 x i32> %a260}261 262define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {263; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma266; CHECK-NEXT: vmv.v.v v8, v16267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(270 <vscale x 16 x i32> %0,271 <vscale x 16 x i32> %1,272 iXLen %2)273 274 ret <vscale x 16 x i32> %a275}276 277define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {278; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma281; CHECK-NEXT: vmv.v.v v8, v9282; CHECK-NEXT: ret283entry:284 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(285 <vscale x 1 x i64> %0,286 <vscale x 1 x i64> %1,287 iXLen %2)288 289 ret <vscale x 1 x i64> %a290}291 292define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {293; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma296; CHECK-NEXT: vmv.v.v v8, v10297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(300 <vscale x 2 x i64> %0,301 <vscale x 2 x i64> %1,302 iXLen %2)303 304 ret <vscale x 2 x i64> %a305}306 307define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {308; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64:309; CHECK: # %bb.0: # %entry310; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma311; CHECK-NEXT: vmv.v.v v8, v12312; CHECK-NEXT: ret313entry:314 %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(315 <vscale x 4 x i64> %0,316 <vscale x 4 x i64> %1,317 iXLen %2)318 319 ret <vscale x 4 x i64> %a320}321 322define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {323; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma326; CHECK-NEXT: vmv.v.v v8, v16327; CHECK-NEXT: ret328entry:329 %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(330 <vscale x 8 x i64> %0,331 <vscale x 8 x i64> %1,332 iXLen %2)333 334 ret <vscale x 8 x i64> %a335}336 337define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma341; CHECK-NEXT: vmv.v.v v8, v9342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(345 <vscale x 1 x half> %0,346 <vscale x 1 x half> %1,347 iXLen %2)348 349 ret <vscale x 1 x half> %a350}351 352define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {353; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16:354; CHECK: # %bb.0: # %entry355; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma356; CHECK-NEXT: vmv.v.v v8, v9357; CHECK-NEXT: ret358entry:359 %a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(360 <vscale x 2 x half> %0,361 <vscale x 2 x half> %1,362 iXLen %2)363 364 ret <vscale x 2 x half> %a365}366 367define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {368; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16:369; CHECK: # %bb.0: # %entry370; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma371; CHECK-NEXT: vmv.v.v v8, v9372; CHECK-NEXT: ret373entry:374 %a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(375 <vscale x 4 x half> %0,376 <vscale x 4 x half> %1,377 iXLen %2)378 379 ret <vscale x 4 x half> %a380}381 382define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {383; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16:384; CHECK: # %bb.0: # %entry385; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma386; CHECK-NEXT: vmv.v.v v8, v10387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(390 <vscale x 8 x half> %0,391 <vscale x 8 x half> %1,392 iXLen %2)393 394 ret <vscale x 8 x half> %a395}396 397define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma401; CHECK-NEXT: vmv.v.v v8, v12402; CHECK-NEXT: ret403entry:404 %a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(405 <vscale x 16 x half> %0,406 <vscale x 16 x half> %1,407 iXLen %2)408 409 ret <vscale x 16 x half> %a410}411 412define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2) nounwind {413; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma416; CHECK-NEXT: vmv.v.v v8, v16417; CHECK-NEXT: ret418entry:419 %a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(420 <vscale x 32 x half> %0,421 <vscale x 32 x half> %1,422 iXLen %2)423 424 ret <vscale x 32 x half> %a425}426 427define <vscale x 1 x bfloat> @intrinsic_vmv.v.v_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {428; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1bf16_nxv1bf16:429; CHECK: # %bb.0: # %entry430; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma431; CHECK-NEXT: vmv.v.v v8, v9432; CHECK-NEXT: ret433entry:434 %a = call <vscale x 1 x bfloat> @llvm.riscv.vmv.v.v.nxv1bf16(435 <vscale x 1 x bfloat> %0,436 <vscale x 1 x bfloat> %1,437 iXLen %2)438 439 ret <vscale x 1 x bfloat> %a440}441 442define <vscale x 2 x bfloat> @intrinsic_vmv.v.v_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {443; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2bf16_nxv2bf16:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma446; CHECK-NEXT: vmv.v.v v8, v9447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 2 x bfloat> @llvm.riscv.vmv.v.v.nxv2bf16(450 <vscale x 2 x bfloat> %0,451 <vscale x 2 x bfloat> %1,452 iXLen %2)453 454 ret <vscale x 2 x bfloat> %a455}456 457define <vscale x 4 x bfloat> @intrinsic_vmv.v.v_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {458; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4bf16_nxv4bf16:459; CHECK: # %bb.0: # %entry460; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma461; CHECK-NEXT: vmv.v.v v8, v9462; CHECK-NEXT: ret463entry:464 %a = call <vscale x 4 x bfloat> @llvm.riscv.vmv.v.v.nxv4bf16(465 <vscale x 4 x bfloat> %0,466 <vscale x 4 x bfloat> %1,467 iXLen %2)468 469 ret <vscale x 4 x bfloat> %a470}471 472define <vscale x 8 x bfloat> @intrinsic_vmv.v.v_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {473; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8bf16_nxv8bf16:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma476; CHECK-NEXT: vmv.v.v v8, v10477; CHECK-NEXT: ret478entry:479 %a = call <vscale x 8 x bfloat> @llvm.riscv.vmv.v.v.nxv8bf16(480 <vscale x 8 x bfloat> %0,481 <vscale x 8 x bfloat> %1,482 iXLen %2)483 484 ret <vscale x 8 x bfloat> %a485}486 487define <vscale x 16 x bfloat> @intrinsic_vmv.v.v_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {488; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16bf16_nxv16bf16:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma491; CHECK-NEXT: vmv.v.v v8, v12492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 16 x bfloat> @llvm.riscv.vmv.v.v.nxv16bf16(495 <vscale x 16 x bfloat> %0,496 <vscale x 16 x bfloat> %1,497 iXLen %2)498 499 ret <vscale x 16 x bfloat> %a500}501 502define <vscale x 32 x bfloat> @intrinsic_vmv.v.v_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2) nounwind {503; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32bf16_nxv32bf16:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma506; CHECK-NEXT: vmv.v.v v8, v16507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 32 x bfloat> @llvm.riscv.vmv.v.v.nxv32bf16(510 <vscale x 32 x bfloat> %0,511 <vscale x 32 x bfloat> %1,512 iXLen %2)513 514 ret <vscale x 32 x bfloat> %a515}516 517define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {518; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:519; CHECK: # %bb.0: # %entry520; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma521; CHECK-NEXT: vmv.v.v v8, v9522; CHECK-NEXT: ret523entry:524 %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(525 <vscale x 1 x float> %0,526 <vscale x 1 x float> %1,527 iXLen %2)528 529 ret <vscale x 1 x float> %a530}531 532define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {533; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32:534; CHECK: # %bb.0: # %entry535; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma536; CHECK-NEXT: vmv.v.v v8, v9537; CHECK-NEXT: ret538entry:539 %a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(540 <vscale x 2 x float> %0,541 <vscale x 2 x float> %1,542 iXLen %2)543 544 ret <vscale x 2 x float> %a545}546 547define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {548; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32:549; CHECK: # %bb.0: # %entry550; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma551; CHECK-NEXT: vmv.v.v v8, v10552; CHECK-NEXT: ret553entry:554 %a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(555 <vscale x 4 x float> %0,556 <vscale x 4 x float> %1,557 iXLen %2)558 559 ret <vscale x 4 x float> %a560}561 562define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {563; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32:564; CHECK: # %bb.0: # %entry565; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma566; CHECK-NEXT: vmv.v.v v8, v12567; CHECK-NEXT: ret568entry:569 %a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(570 <vscale x 8 x float> %0,571 <vscale x 8 x float> %1,572 iXLen %2)573 574 ret <vscale x 8 x float> %a575}576 577define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2) nounwind {578; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32:579; CHECK: # %bb.0: # %entry580; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma581; CHECK-NEXT: vmv.v.v v8, v16582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(585 <vscale x 16 x float> %0,586 <vscale x 16 x float> %1,587 iXLen %2)588 589 ret <vscale x 16 x float> %a590}591 592define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {593; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64:594; CHECK: # %bb.0: # %entry595; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma596; CHECK-NEXT: vmv.v.v v8, v9597; CHECK-NEXT: ret598entry:599 %a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(600 <vscale x 1 x double> %0,601 <vscale x 1 x double> %1,602 iXLen %2)603 604 ret <vscale x 1 x double> %a605}606 607define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {608; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64:609; CHECK: # %bb.0: # %entry610; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma611; CHECK-NEXT: vmv.v.v v8, v10612; CHECK-NEXT: ret613entry:614 %a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(615 <vscale x 2 x double> %0,616 <vscale x 2 x double> %1,617 iXLen %2)618 619 ret <vscale x 2 x double> %a620}621 622define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {623; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64:624; CHECK: # %bb.0: # %entry625; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma626; CHECK-NEXT: vmv.v.v v8, v12627; CHECK-NEXT: ret628entry:629 %a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(630 <vscale x 4 x double> %0,631 <vscale x 4 x double> %1,632 iXLen %2)633 634 ret <vscale x 4 x double> %a635}636 637define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64:639; CHECK: # %bb.0: # %entry640; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma641; CHECK-NEXT: vmv.v.v v8, v16642; CHECK-NEXT: ret643entry:644 %a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(645 <vscale x 8 x double> %0,646 <vscale x 8 x double> %1,647 iXLen %2)648 649 ret <vscale x 8 x double> %a650}651