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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vmv.v.x v8, a012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(15 <vscale x 1 x i8> poison,16 i8 %0,17 iXLen %1)18 19 ret <vscale x 1 x i8> %a20}21 22define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, iXLen %1) nounwind {23; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma26; CHECK-NEXT: vmv.v.x v8, a027; CHECK-NEXT: ret28entry:29 %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(30 <vscale x 2 x i8> poison,31 i8 %0,32 iXLen %1)33 34 ret <vscale x 2 x i8> %a35}36 37define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, iXLen %1) nounwind {38; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma41; CHECK-NEXT: vmv.v.x v8, a042; CHECK-NEXT: ret43entry:44 %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(45 <vscale x 4 x i8> poison,46 i8 %0,47 iXLen %1)48 49 ret <vscale x 4 x i8> %a50}51 52define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, iXLen %1) nounwind {53; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma56; CHECK-NEXT: vmv.v.x v8, a057; CHECK-NEXT: ret58entry:59 %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(60 <vscale x 8 x i8> poison,61 i8 %0,62 iXLen %1)63 64 ret <vscale x 8 x i8> %a65}66 67define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, iXLen %1) nounwind {68; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma71; CHECK-NEXT: vmv.v.x v8, a072; CHECK-NEXT: ret73entry:74 %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(75 <vscale x 16 x i8> poison,76 i8 %0,77 iXLen %1)78 79 ret <vscale x 16 x i8> %a80}81 82define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, iXLen %1) nounwind {83; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma86; CHECK-NEXT: vmv.v.x v8, a087; CHECK-NEXT: ret88entry:89 %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(90 <vscale x 32 x i8> poison,91 i8 %0,92 iXLen %1)93 94 ret <vscale x 32 x i8> %a95}96 97define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, iXLen %1) nounwind {98; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma101; CHECK-NEXT: vmv.v.x v8, a0102; CHECK-NEXT: ret103entry:104 %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(105 <vscale x 64 x i8> poison,106 i8 %0,107 iXLen %1)108 109 ret <vscale x 64 x i8> %a110}111 112define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, iXLen %1) nounwind {113; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma116; CHECK-NEXT: vmv.v.x v8, a0117; CHECK-NEXT: ret118entry:119 %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(120 <vscale x 1 x i16> poison,121 i16 %0,122 iXLen %1)123 124 ret <vscale x 1 x i16> %a125}126 127define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, iXLen %1) nounwind {128; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma131; CHECK-NEXT: vmv.v.x v8, a0132; CHECK-NEXT: ret133entry:134 %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(135 <vscale x 2 x i16> poison,136 i16 %0,137 iXLen %1)138 139 ret <vscale x 2 x i16> %a140}141 142define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, iXLen %1) nounwind {143; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma146; CHECK-NEXT: vmv.v.x v8, a0147; CHECK-NEXT: ret148entry:149 %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(150 <vscale x 4 x i16> poison,151 i16 %0,152 iXLen %1)153 154 ret <vscale x 4 x i16> %a155}156 157define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, iXLen %1) nounwind {158; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma161; CHECK-NEXT: vmv.v.x v8, a0162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(165 <vscale x 8 x i16> poison,166 i16 %0,167 iXLen %1)168 169 ret <vscale x 8 x i16> %a170}171 172define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, iXLen %1) nounwind {173; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma176; CHECK-NEXT: vmv.v.x v8, a0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(180 <vscale x 16 x i16> poison,181 i16 %0,182 iXLen %1)183 184 ret <vscale x 16 x i16> %a185}186 187define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, iXLen %1) nounwind {188; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma191; CHECK-NEXT: vmv.v.x v8, a0192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(195 <vscale x 32 x i16> poison,196 i16 %0,197 iXLen %1)198 199 ret <vscale x 32 x i16> %a200}201 202define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, iXLen %1) nounwind {203; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma206; CHECK-NEXT: vmv.v.x v8, a0207; CHECK-NEXT: ret208entry:209 %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(210 <vscale x 1 x i32> poison,211 i32 %0,212 iXLen %1)213 214 ret <vscale x 1 x i32> %a215}216 217define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, iXLen %1) nounwind {218; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma221; CHECK-NEXT: vmv.v.x v8, a0222; CHECK-NEXT: ret223entry:224 %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(225 <vscale x 2 x i32> poison,226 i32 %0,227 iXLen %1)228 229 ret <vscale x 2 x i32> %a230}231 232define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, iXLen %1) nounwind {233; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32:234; CHECK: # %bb.0: # %entry235; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma236; CHECK-NEXT: vmv.v.x v8, a0237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(240 <vscale x 4 x i32> poison,241 i32 %0,242 iXLen %1)243 244 ret <vscale x 4 x i32> %a245}246 247define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, iXLen %1) nounwind {248; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma251; CHECK-NEXT: vmv.v.x v8, a0252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(255 <vscale x 8 x i32> poison,256 i32 %0,257 iXLen %1)258 259 ret <vscale x 8 x i32> %a260}261 262define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, iXLen %1) nounwind {263; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma266; CHECK-NEXT: vmv.v.x v8, a0267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(270 <vscale x 16 x i32> poison,271 i32 %0,272 iXLen %1)273 274 ret <vscale x 16 x i32> %a275}276 277define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, iXLen %1) nounwind {278; RV32-LABEL: intrinsic_vmv.v.x_x_nxv1i64:279; RV32: # %bb.0: # %entry280; RV32-NEXT: addi sp, sp, -16281; RV32-NEXT: sw a0, 8(sp)282; RV32-NEXT: sw a1, 12(sp)283; RV32-NEXT: addi a0, sp, 8284; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma285; RV32-NEXT: vlse64.v v8, (a0), zero286; RV32-NEXT: addi sp, sp, 16287; RV32-NEXT: ret288;289; RV64-LABEL: intrinsic_vmv.v.x_x_nxv1i64:290; RV64: # %bb.0: # %entry291; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma292; RV64-NEXT: vmv.v.x v8, a0293; RV64-NEXT: ret294entry:295 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(296 <vscale x 1 x i64> poison,297 i64 %0,298 iXLen %1)299 300 ret <vscale x 1 x i64> %a301}302 303define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, iXLen %1) nounwind {304; RV32-LABEL: intrinsic_vmv.v.x_x_nxv2i64:305; RV32: # %bb.0: # %entry306; RV32-NEXT: addi sp, sp, -16307; RV32-NEXT: sw a0, 8(sp)308; RV32-NEXT: sw a1, 12(sp)309; RV32-NEXT: addi a0, sp, 8310; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma311; RV32-NEXT: vlse64.v v8, (a0), zero312; RV32-NEXT: addi sp, sp, 16313; RV32-NEXT: ret314;315; RV64-LABEL: intrinsic_vmv.v.x_x_nxv2i64:316; RV64: # %bb.0: # %entry317; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma318; RV64-NEXT: vmv.v.x v8, a0319; RV64-NEXT: ret320entry:321 %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(322 <vscale x 2 x i64> poison,323 i64 %0,324 iXLen %1)325 326 ret <vscale x 2 x i64> %a327}328 329define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, iXLen %1) nounwind {330; RV32-LABEL: intrinsic_vmv.v.x_x_nxv4i64:331; RV32: # %bb.0: # %entry332; RV32-NEXT: addi sp, sp, -16333; RV32-NEXT: sw a0, 8(sp)334; RV32-NEXT: sw a1, 12(sp)335; RV32-NEXT: addi a0, sp, 8336; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma337; RV32-NEXT: vlse64.v v8, (a0), zero338; RV32-NEXT: addi sp, sp, 16339; RV32-NEXT: ret340;341; RV64-LABEL: intrinsic_vmv.v.x_x_nxv4i64:342; RV64: # %bb.0: # %entry343; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma344; RV64-NEXT: vmv.v.x v8, a0345; RV64-NEXT: ret346entry:347 %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(348 <vscale x 4 x i64> poison,349 i64 %0,350 iXLen %1)351 352 ret <vscale x 4 x i64> %a353}354 355define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, iXLen %1) nounwind {356; RV32-LABEL: intrinsic_vmv.v.x_x_nxv8i64:357; RV32: # %bb.0: # %entry358; RV32-NEXT: addi sp, sp, -16359; RV32-NEXT: sw a0, 8(sp)360; RV32-NEXT: sw a1, 12(sp)361; RV32-NEXT: addi a0, sp, 8362; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma363; RV32-NEXT: vlse64.v v8, (a0), zero364; RV32-NEXT: addi sp, sp, 16365; RV32-NEXT: ret366;367; RV64-LABEL: intrinsic_vmv.v.x_x_nxv8i64:368; RV64: # %bb.0: # %entry369; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma370; RV64-NEXT: vmv.v.x v8, a0371; RV64-NEXT: ret372entry:373 %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(374 <vscale x 8 x i64> poison,375 i64 %0,376 iXLen %1)377 378 ret <vscale x 8 x i64> %a379}380 381define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(iXLen %0) nounwind {382; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma385; CHECK-NEXT: vmv.v.i v8, 9386; CHECK-NEXT: ret387entry:388 %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(389 <vscale x 1 x i8> poison,390 i8 9,391 iXLen %0)392 393 ret <vscale x 1 x i8> %a394}395 396define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(iXLen %0) nounwind {397; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8:398; CHECK: # %bb.0: # %entry399; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma400; CHECK-NEXT: vmv.v.i v8, 9401; CHECK-NEXT: ret402entry:403 %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(404 <vscale x 2 x i8> poison,405 i8 9,406 iXLen %0)407 408 ret <vscale x 2 x i8> %a409}410 411define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(iXLen %0) nounwind {412; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8:413; CHECK: # %bb.0: # %entry414; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma415; CHECK-NEXT: vmv.v.i v8, 9416; CHECK-NEXT: ret417entry:418 %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(419 <vscale x 4 x i8> poison,420 i8 9,421 iXLen %0)422 423 ret <vscale x 4 x i8> %a424}425 426define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(iXLen %0) nounwind {427; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma430; CHECK-NEXT: vmv.v.i v8, 9431; CHECK-NEXT: ret432entry:433 %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(434 <vscale x 8 x i8> poison,435 i8 9,436 iXLen %0)437 438 ret <vscale x 8 x i8> %a439}440 441define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(iXLen %0) nounwind {442; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8:443; CHECK: # %bb.0: # %entry444; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma445; CHECK-NEXT: vmv.v.i v8, 9446; CHECK-NEXT: ret447entry:448 %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(449 <vscale x 16 x i8> poison,450 i8 9,451 iXLen %0)452 453 ret <vscale x 16 x i8> %a454}455 456define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(iXLen %0) nounwind {457; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma460; CHECK-NEXT: vmv.v.i v8, 9461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(464 <vscale x 32 x i8> poison,465 i8 9,466 iXLen %0)467 468 ret <vscale x 32 x i8> %a469}470 471define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(iXLen %0) nounwind {472; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma475; CHECK-NEXT: vmv.v.i v8, 9476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(479 <vscale x 64 x i8> poison,480 i8 9,481 iXLen %0)482 483 ret <vscale x 64 x i8> %a484}485 486define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(iXLen %0) nounwind {487; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16:488; CHECK: # %bb.0: # %entry489; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma490; CHECK-NEXT: vmv.v.i v8, 9491; CHECK-NEXT: ret492entry:493 %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(494 <vscale x 1 x i16> poison,495 i16 9,496 iXLen %0)497 498 ret <vscale x 1 x i16> %a499}500 501define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(iXLen %0) nounwind {502; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16:503; CHECK: # %bb.0: # %entry504; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma505; CHECK-NEXT: vmv.v.i v8, 9506; CHECK-NEXT: ret507entry:508 %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(509 <vscale x 2 x i16> poison,510 i16 9,511 iXLen %0)512 513 ret <vscale x 2 x i16> %a514}515 516define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(iXLen %0) nounwind {517; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16:518; CHECK: # %bb.0: # %entry519; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma520; CHECK-NEXT: vmv.v.i v8, 9521; CHECK-NEXT: ret522entry:523 %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(524 <vscale x 4 x i16> poison,525 i16 9,526 iXLen %0)527 528 ret <vscale x 4 x i16> %a529}530 531define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(iXLen %0) nounwind {532; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16:533; CHECK: # %bb.0: # %entry534; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma535; CHECK-NEXT: vmv.v.i v8, 9536; CHECK-NEXT: ret537entry:538 %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(539 <vscale x 8 x i16> poison,540 i16 9,541 iXLen %0)542 543 ret <vscale x 8 x i16> %a544}545 546define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(iXLen %0) nounwind {547; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16:548; CHECK: # %bb.0: # %entry549; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma550; CHECK-NEXT: vmv.v.i v8, 9551; CHECK-NEXT: ret552entry:553 %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(554 <vscale x 16 x i16> poison,555 i16 9,556 iXLen %0)557 558 ret <vscale x 16 x i16> %a559}560 561define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(iXLen %0) nounwind {562; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16:563; CHECK: # %bb.0: # %entry564; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma565; CHECK-NEXT: vmv.v.i v8, 9566; CHECK-NEXT: ret567entry:568 %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(569 <vscale x 32 x i16> poison,570 i16 9,571 iXLen %0)572 573 ret <vscale x 32 x i16> %a574}575 576define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(iXLen %0) nounwind {577; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32:578; CHECK: # %bb.0: # %entry579; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma580; CHECK-NEXT: vmv.v.i v8, 9581; CHECK-NEXT: ret582entry:583 %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(584 <vscale x 1 x i32> poison,585 i32 9,586 iXLen %0)587 588 ret <vscale x 1 x i32> %a589}590 591define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(iXLen %0) nounwind {592; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32:593; CHECK: # %bb.0: # %entry594; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma595; CHECK-NEXT: vmv.v.i v8, 9596; CHECK-NEXT: ret597entry:598 %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(599 <vscale x 2 x i32> poison,600 i32 9,601 iXLen %0)602 603 ret <vscale x 2 x i32> %a604}605 606define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(iXLen %0) nounwind {607; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32:608; CHECK: # %bb.0: # %entry609; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma610; CHECK-NEXT: vmv.v.i v8, 9611; CHECK-NEXT: ret612entry:613 %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(614 <vscale x 4 x i32> poison,615 i32 9,616 iXLen %0)617 618 ret <vscale x 4 x i32> %a619}620 621define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(iXLen %0) nounwind {622; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32:623; CHECK: # %bb.0: # %entry624; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma625; CHECK-NEXT: vmv.v.i v8, 9626; CHECK-NEXT: ret627entry:628 %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(629 <vscale x 8 x i32> poison,630 i32 9,631 iXLen %0)632 633 ret <vscale x 8 x i32> %a634}635 636define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(iXLen %0) nounwind {637; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32:638; CHECK: # %bb.0: # %entry639; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma640; CHECK-NEXT: vmv.v.i v8, 9641; CHECK-NEXT: ret642entry:643 %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(644 <vscale x 16 x i32> poison,645 i32 9,646 iXLen %0)647 648 ret <vscale x 16 x i32> %a649}650 651define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(iXLen %0) nounwind {652; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64:653; CHECK: # %bb.0: # %entry654; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma655; CHECK-NEXT: vmv.v.i v8, 9656; CHECK-NEXT: ret657entry:658 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(659 <vscale x 1 x i64> poison,660 i64 9,661 iXLen %0)662 663 ret <vscale x 1 x i64> %a664}665 666define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(iXLen %0) nounwind {667; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64:668; CHECK: # %bb.0: # %entry669; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma670; CHECK-NEXT: vmv.v.i v8, 9671; CHECK-NEXT: ret672entry:673 %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(674 <vscale x 2 x i64> poison,675 i64 9,676 iXLen %0)677 678 ret <vscale x 2 x i64> %a679}680 681define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(iXLen %0) nounwind {682; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64:683; CHECK: # %bb.0: # %entry684; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma685; CHECK-NEXT: vmv.v.i v8, 9686; CHECK-NEXT: ret687entry:688 %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(689 <vscale x 4 x i64> poison,690 i64 9,691 iXLen %0)692 693 ret <vscale x 4 x i64> %a694}695 696define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(iXLen %0) nounwind {697; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64:698; CHECK: # %bb.0: # %entry699; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma700; CHECK-NEXT: vmv.v.i v8, 9701; CHECK-NEXT: ret702entry:703 %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(704 <vscale x 8 x i64> poison,705 i64 9,706 iXLen %0)707 708 ret <vscale x 8 x i64> %a709}710