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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define signext i8 @intrinsic_vmv.x.s_s_nxv1i8(<vscale x 1 x i8> %0) nounwind {8; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma11; CHECK-NEXT: vmv.x.s a0, v812; CHECK-NEXT: ret13entry:14 %a = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> %0)15 ret i8 %a16}17 18define signext i8 @intrinsic_vmv.x.s_s_nxv2i8(<vscale x 2 x i8> %0) nounwind {19; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i8:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma22; CHECK-NEXT: vmv.x.s a0, v823; CHECK-NEXT: ret24entry:25 %a = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> %0)26 ret i8 %a27}28 29define signext i8 @intrinsic_vmv.x.s_s_nxv4i8(<vscale x 4 x i8> %0) nounwind {30; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i8:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma33; CHECK-NEXT: vmv.x.s a0, v834; CHECK-NEXT: ret35entry:36 %a = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> %0)37 ret i8 %a38}39 40define signext i8 @intrinsic_vmv.x.s_s_nxv8i8(<vscale x 8 x i8> %0) nounwind {41; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma44; CHECK-NEXT: vmv.x.s a0, v845; CHECK-NEXT: ret46entry:47 %a = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> %0)48 ret i8 %a49}50 51define signext i8 @intrinsic_vmv.x.s_s_nxv16i8(<vscale x 16 x i8> %0) nounwind {52; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i8:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma55; CHECK-NEXT: vmv.x.s a0, v856; CHECK-NEXT: ret57entry:58 %a = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> %0)59 ret i8 %a60}61 62define signext i8 @intrinsic_vmv.x.s_s_nxv32i8(<vscale x 32 x i8> %0) nounwind {63; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i8:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma66; CHECK-NEXT: vmv.x.s a0, v867; CHECK-NEXT: ret68entry:69 %a = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> %0)70 ret i8 %a71}72 73define signext i8 @intrinsic_vmv.x.s_s_nxv64i8(<vscale x 64 x i8> %0) nounwind {74; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv64i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma77; CHECK-NEXT: vmv.x.s a0, v878; CHECK-NEXT: ret79entry:80 %a = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> %0)81 ret i8 %a82}83 84define signext i16 @intrinsic_vmv.x.s_s_nxv1i16(<vscale x 1 x i16> %0) nounwind {85; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i16:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma88; CHECK-NEXT: vmv.x.s a0, v889; CHECK-NEXT: ret90entry:91 %a = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> %0)92 ret i16 %a93}94 95define signext i16 @intrinsic_vmv.x.s_s_nxv2i16(<vscale x 2 x i16> %0) nounwind {96; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i16:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma99; CHECK-NEXT: vmv.x.s a0, v8100; CHECK-NEXT: ret101entry:102 %a = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> %0)103 ret i16 %a104}105 106define signext i16 @intrinsic_vmv.x.s_s_nxv4i16(<vscale x 4 x i16> %0) nounwind {107; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma110; CHECK-NEXT: vmv.x.s a0, v8111; CHECK-NEXT: ret112entry:113 %a = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> %0)114 ret i16 %a115}116 117define signext i16 @intrinsic_vmv.x.s_s_nxv8i16(<vscale x 8 x i16> %0) nounwind {118; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i16:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma121; CHECK-NEXT: vmv.x.s a0, v8122; CHECK-NEXT: ret123entry:124 %a = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> %0)125 ret i16 %a126}127 128define signext i16 @intrinsic_vmv.x.s_s_nxv16i16(<vscale x 16 x i16> %0) nounwind {129; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i16:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma132; CHECK-NEXT: vmv.x.s a0, v8133; CHECK-NEXT: ret134entry:135 %a = call i16 @llvm.riscv.vmv.x.s.nxv16i16( <vscale x 16 x i16> %0)136 ret i16 %a137}138 139define signext i16 @intrinsic_vmv.x.s_s_nxv32i16(<vscale x 32 x i16> %0) nounwind {140; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i16:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma143; CHECK-NEXT: vmv.x.s a0, v8144; CHECK-NEXT: ret145entry:146 %a = call i16 @llvm.riscv.vmv.x.s.nxv32i16( <vscale x 32 x i16> %0)147 ret i16 %a148}149 150define signext i32 @intrinsic_vmv.x.s_s_nxv1i32(<vscale x 1 x i32> %0) nounwind {151; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i32:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma154; CHECK-NEXT: vmv.x.s a0, v8155; CHECK-NEXT: ret156entry:157 %a = call i32 @llvm.riscv.vmv.x.s.nxv1i32( <vscale x 1 x i32> %0)158 ret i32 %a159}160 161define signext i32 @intrinsic_vmv.x.s_s_nxv2i32(<vscale x 2 x i32> %0) nounwind {162; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i32:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma165; CHECK-NEXT: vmv.x.s a0, v8166; CHECK-NEXT: ret167entry:168 %a = call i32 @llvm.riscv.vmv.x.s.nxv2i32( <vscale x 2 x i32> %0)169 ret i32 %a170}171 172define signext i32 @intrinsic_vmv.x.s_s_nxv4i32(<vscale x 4 x i32> %0) nounwind {173; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i32:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma176; CHECK-NEXT: vmv.x.s a0, v8177; CHECK-NEXT: ret178entry:179 %a = call i32 @llvm.riscv.vmv.x.s.nxv4i32( <vscale x 4 x i32> %0)180 ret i32 %a181}182 183define signext i32 @intrinsic_vmv.x.s_s_nxv8i32(<vscale x 8 x i32> %0) nounwind {184; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i32:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma187; CHECK-NEXT: vmv.x.s a0, v8188; CHECK-NEXT: ret189entry:190 %a = call i32 @llvm.riscv.vmv.x.s.nxv8i32( <vscale x 8 x i32> %0)191 ret i32 %a192}193 194define signext i32 @intrinsic_vmv.x.s_s_nxv16i32(<vscale x 16 x i32> %0) nounwind {195; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i32:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma198; CHECK-NEXT: vmv.x.s a0, v8199; CHECK-NEXT: ret200entry:201 %a = call i32 @llvm.riscv.vmv.x.s.nxv16i32( <vscale x 16 x i32> %0)202 ret i32 %a203}204 205define i64 @intrinsic_vmv.x.s_s_nxv1i64(<vscale x 1 x i64> %0) nounwind {206; RV32-LABEL: intrinsic_vmv.x.s_s_nxv1i64:207; RV32: # %bb.0: # %entry208; RV32-NEXT: li a0, 32209; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma210; RV32-NEXT: vsrl.vx v9, v8, a0211; RV32-NEXT: vmv.x.s a1, v9212; RV32-NEXT: vmv.x.s a0, v8213; RV32-NEXT: ret214;215; RV64-LABEL: intrinsic_vmv.x.s_s_nxv1i64:216; RV64: # %bb.0: # %entry217; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma218; RV64-NEXT: vmv.x.s a0, v8219; RV64-NEXT: ret220entry:221 %a = call i64 @llvm.riscv.vmv.x.s.nxv1i64( <vscale x 1 x i64> %0)222 ret i64 %a223}224 225define i64 @intrinsic_vmv.x.s_s_nxv2i64(<vscale x 2 x i64> %0) nounwind {226; RV32-LABEL: intrinsic_vmv.x.s_s_nxv2i64:227; RV32: # %bb.0: # %entry228; RV32-NEXT: li a0, 32229; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma230; RV32-NEXT: vsrl.vx v10, v8, a0231; RV32-NEXT: vmv.x.s a1, v10232; RV32-NEXT: vmv.x.s a0, v8233; RV32-NEXT: ret234;235; RV64-LABEL: intrinsic_vmv.x.s_s_nxv2i64:236; RV64: # %bb.0: # %entry237; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma238; RV64-NEXT: vmv.x.s a0, v8239; RV64-NEXT: ret240entry:241 %a = call i64 @llvm.riscv.vmv.x.s.nxv2i64( <vscale x 2 x i64> %0)242 ret i64 %a243}244 245define i64 @intrinsic_vmv.x.s_s_nxv4i64(<vscale x 4 x i64> %0) nounwind {246; RV32-LABEL: intrinsic_vmv.x.s_s_nxv4i64:247; RV32: # %bb.0: # %entry248; RV32-NEXT: li a0, 32249; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma250; RV32-NEXT: vsrl.vx v12, v8, a0251; RV32-NEXT: vmv.x.s a1, v12252; RV32-NEXT: vmv.x.s a0, v8253; RV32-NEXT: ret254;255; RV64-LABEL: intrinsic_vmv.x.s_s_nxv4i64:256; RV64: # %bb.0: # %entry257; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma258; RV64-NEXT: vmv.x.s a0, v8259; RV64-NEXT: ret260entry:261 %a = call i64 @llvm.riscv.vmv.x.s.nxv4i64( <vscale x 4 x i64> %0)262 ret i64 %a263}264 265define i64 @intrinsic_vmv.x.s_s_nxv8i64(<vscale x 8 x i64> %0) nounwind {266; RV32-LABEL: intrinsic_vmv.x.s_s_nxv8i64:267; RV32: # %bb.0: # %entry268; RV32-NEXT: li a0, 32269; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma270; RV32-NEXT: vsrl.vx v16, v8, a0271; RV32-NEXT: vmv.x.s a1, v16272; RV32-NEXT: vmv.x.s a0, v8273; RV32-NEXT: ret274;275; RV64-LABEL: intrinsic_vmv.x.s_s_nxv8i64:276; RV64: # %bb.0: # %entry277; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma278; RV64-NEXT: vmv.x.s a0, v8279; RV64-NEXT: ret280entry:281 %a = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> %0)282 ret i64 %a283}284