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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i8> @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: csrwi vxrm, 011; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma12; CHECK-NEXT: vnclip.wv v8, v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8(16 <vscale x 1 x i8> poison,17 <vscale x 1 x i16> %0,18 <vscale x 1 x i8> %1,19 iXLen 0, iXLen %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: csrwi vxrm, 028; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu29; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t30; CHECK-NEXT: ret31entry:32 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8(33 <vscale x 1 x i8> %0,34 <vscale x 1 x i16> %1,35 <vscale x 1 x i8> %2,36 <vscale x 1 x i1> %3,37 iXLen 0, iXLen %4, iXLen 1)38 39 ret <vscale x 1 x i8> %a40}41 42define <vscale x 2 x i8> @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {43; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: csrwi vxrm, 046; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma47; CHECK-NEXT: vnclip.wv v8, v8, v948; CHECK-NEXT: ret49entry:50 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8(51 <vscale x 2 x i8> poison,52 <vscale x 2 x i16> %0,53 <vscale x 2 x i8> %1,54 iXLen 0, iXLen %2)55 56 ret <vscale x 2 x i8> %a57}58 59define <vscale x 2 x i8> @intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {60; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: csrwi vxrm, 063; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu64; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t65; CHECK-NEXT: ret66entry:67 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8(68 <vscale x 2 x i8> %0,69 <vscale x 2 x i16> %1,70 <vscale x 2 x i8> %2,71 <vscale x 2 x i1> %3,72 iXLen 0, iXLen %4, iXLen 1)73 74 ret <vscale x 2 x i8> %a75}76 77define <vscale x 4 x i8> @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {78; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: csrwi vxrm, 081; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma82; CHECK-NEXT: vnclip.wv v8, v8, v983; CHECK-NEXT: ret84entry:85 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8(86 <vscale x 4 x i8> poison,87 <vscale x 4 x i16> %0,88 <vscale x 4 x i8> %1,89 iXLen 0, iXLen %2)90 91 ret <vscale x 4 x i8> %a92}93 94define <vscale x 4 x i8> @intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {95; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: csrwi vxrm, 098; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu99; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t100; CHECK-NEXT: ret101entry:102 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8(103 <vscale x 4 x i8> %0,104 <vscale x 4 x i16> %1,105 <vscale x 4 x i8> %2,106 <vscale x 4 x i1> %3,107 iXLen 0, iXLen %4, iXLen 1)108 109 ret <vscale x 4 x i8> %a110}111 112define <vscale x 8 x i8> @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {113; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: csrwi vxrm, 0116; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma117; CHECK-NEXT: vnclip.wv v11, v8, v10118; CHECK-NEXT: vmv.v.v v8, v11119; CHECK-NEXT: ret120entry:121 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8(122 <vscale x 8 x i8> poison,123 <vscale x 8 x i16> %0,124 <vscale x 8 x i8> %1,125 iXLen 0, iXLen %2)126 127 ret <vscale x 8 x i8> %a128}129 130define <vscale x 8 x i8> @intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {131; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8:132; CHECK: # %bb.0: # %entry133; CHECK-NEXT: csrwi vxrm, 0134; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu135; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8(139 <vscale x 8 x i8> %0,140 <vscale x 8 x i16> %1,141 <vscale x 8 x i8> %2,142 <vscale x 8 x i1> %3,143 iXLen 0, iXLen %4, iXLen 1)144 145 ret <vscale x 8 x i8> %a146}147 148define <vscale x 16 x i8> @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {149; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8:150; CHECK: # %bb.0: # %entry151; CHECK-NEXT: csrwi vxrm, 0152; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma153; CHECK-NEXT: vnclip.wv v14, v8, v12154; CHECK-NEXT: vmv.v.v v8, v14155; CHECK-NEXT: ret156entry:157 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8(158 <vscale x 16 x i8> poison,159 <vscale x 16 x i16> %0,160 <vscale x 16 x i8> %1,161 iXLen 0, iXLen %2)162 163 ret <vscale x 16 x i8> %a164}165 166define <vscale x 16 x i8> @intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {167; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8:168; CHECK: # %bb.0: # %entry169; CHECK-NEXT: csrwi vxrm, 0170; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu171; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t172; CHECK-NEXT: ret173entry:174 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8(175 <vscale x 16 x i8> %0,176 <vscale x 16 x i16> %1,177 <vscale x 16 x i8> %2,178 <vscale x 16 x i1> %3,179 iXLen 0, iXLen %4, iXLen 1)180 181 ret <vscale x 16 x i8> %a182}183 184define <vscale x 32 x i8> @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {185; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8:186; CHECK: # %bb.0: # %entry187; CHECK-NEXT: csrwi vxrm, 0188; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma189; CHECK-NEXT: vnclip.wv v20, v8, v16190; CHECK-NEXT: vmv.v.v v8, v20191; CHECK-NEXT: ret192entry:193 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8(194 <vscale x 32 x i8> poison,195 <vscale x 32 x i16> %0,196 <vscale x 32 x i8> %1,197 iXLen 0, iXLen %2)198 199 ret <vscale x 32 x i8> %a200}201 202define <vscale x 32 x i8> @intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {203; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: csrwi vxrm, 0206; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu207; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t208; CHECK-NEXT: ret209entry:210 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8(211 <vscale x 32 x i8> %0,212 <vscale x 32 x i16> %1,213 <vscale x 32 x i8> %2,214 <vscale x 32 x i1> %3,215 iXLen 0, iXLen %4, iXLen 1)216 217 ret <vscale x 32 x i8> %a218}219 220define <vscale x 1 x i16> @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {221; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: csrwi vxrm, 0224; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma225; CHECK-NEXT: vnclip.wv v8, v8, v9226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16(229 <vscale x 1 x i16> poison,230 <vscale x 1 x i32> %0,231 <vscale x 1 x i16> %1,232 iXLen 0, iXLen %2)233 234 ret <vscale x 1 x i16> %a235}236 237define <vscale x 1 x i16> @intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {238; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16:239; CHECK: # %bb.0: # %entry240; CHECK-NEXT: csrwi vxrm, 0241; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu242; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16(246 <vscale x 1 x i16> %0,247 <vscale x 1 x i32> %1,248 <vscale x 1 x i16> %2,249 <vscale x 1 x i1> %3,250 iXLen 0, iXLen %4, iXLen 1)251 252 ret <vscale x 1 x i16> %a253}254 255define <vscale x 2 x i16> @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {256; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: csrwi vxrm, 0259; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma260; CHECK-NEXT: vnclip.wv v8, v8, v9261; CHECK-NEXT: ret262entry:263 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(264 <vscale x 2 x i16> poison,265 <vscale x 2 x i32> %0,266 <vscale x 2 x i16> %1,267 iXLen 0, iXLen %2)268 269 ret <vscale x 2 x i16> %a270}271 272define <vscale x 2 x i16> @intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {273; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: csrwi vxrm, 0276; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu277; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t278; CHECK-NEXT: ret279entry:280 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16(281 <vscale x 2 x i16> %0,282 <vscale x 2 x i32> %1,283 <vscale x 2 x i16> %2,284 <vscale x 2 x i1> %3,285 iXLen 0, iXLen %4, iXLen 1)286 287 ret <vscale x 2 x i16> %a288}289 290define <vscale x 4 x i16> @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {291; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16:292; CHECK: # %bb.0: # %entry293; CHECK-NEXT: csrwi vxrm, 0294; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma295; CHECK-NEXT: vnclip.wv v11, v8, v10296; CHECK-NEXT: vmv.v.v v8, v11297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16(300 <vscale x 4 x i16> poison,301 <vscale x 4 x i32> %0,302 <vscale x 4 x i16> %1,303 iXLen 0, iXLen %2)304 305 ret <vscale x 4 x i16> %a306}307 308define <vscale x 4 x i16> @intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {309; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16:310; CHECK: # %bb.0: # %entry311; CHECK-NEXT: csrwi vxrm, 0312; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu313; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t314; CHECK-NEXT: ret315entry:316 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16(317 <vscale x 4 x i16> %0,318 <vscale x 4 x i32> %1,319 <vscale x 4 x i16> %2,320 <vscale x 4 x i1> %3,321 iXLen 0, iXLen %4, iXLen 1)322 323 ret <vscale x 4 x i16> %a324}325 326define <vscale x 8 x i16> @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {327; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16:328; CHECK: # %bb.0: # %entry329; CHECK-NEXT: csrwi vxrm, 0330; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma331; CHECK-NEXT: vnclip.wv v14, v8, v12332; CHECK-NEXT: vmv.v.v v8, v14333; CHECK-NEXT: ret334entry:335 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16(336 <vscale x 8 x i16> poison,337 <vscale x 8 x i32> %0,338 <vscale x 8 x i16> %1,339 iXLen 0, iXLen %2)340 341 ret <vscale x 8 x i16> %a342}343 344define <vscale x 8 x i16> @intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {345; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: csrwi vxrm, 0348; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu349; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t350; CHECK-NEXT: ret351entry:352 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16(353 <vscale x 8 x i16> %0,354 <vscale x 8 x i32> %1,355 <vscale x 8 x i16> %2,356 <vscale x 8 x i1> %3,357 iXLen 0, iXLen %4, iXLen 1)358 359 ret <vscale x 8 x i16> %a360}361 362define <vscale x 16 x i16> @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {363; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16:364; CHECK: # %bb.0: # %entry365; CHECK-NEXT: csrwi vxrm, 0366; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma367; CHECK-NEXT: vnclip.wv v20, v8, v16368; CHECK-NEXT: vmv.v.v v8, v20369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16(372 <vscale x 16 x i16> poison,373 <vscale x 16 x i32> %0,374 <vscale x 16 x i16> %1,375 iXLen 0, iXLen %2)376 377 ret <vscale x 16 x i16> %a378}379 380define <vscale x 16 x i16> @intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {381; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16:382; CHECK: # %bb.0: # %entry383; CHECK-NEXT: csrwi vxrm, 0384; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu385; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t386; CHECK-NEXT: ret387entry:388 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16(389 <vscale x 16 x i16> %0,390 <vscale x 16 x i32> %1,391 <vscale x 16 x i16> %2,392 <vscale x 16 x i1> %3,393 iXLen 0, iXLen %4, iXLen 1)394 395 ret <vscale x 16 x i16> %a396}397 398define <vscale x 1 x i32> @intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {399; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: csrwi vxrm, 0402; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma403; CHECK-NEXT: vnclip.wv v8, v8, v9404; CHECK-NEXT: ret405entry:406 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32(407 <vscale x 1 x i32> poison,408 <vscale x 1 x i64> %0,409 <vscale x 1 x i32> %1,410 iXLen 0, iXLen %2)411 412 ret <vscale x 1 x i32> %a413}414 415define <vscale x 1 x i32> @intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {416; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: csrwi vxrm, 0419; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu420; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t421; CHECK-NEXT: ret422entry:423 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.nxv1i32(424 <vscale x 1 x i32> %0,425 <vscale x 1 x i64> %1,426 <vscale x 1 x i32> %2,427 <vscale x 1 x i1> %3,428 iXLen 0, iXLen %4, iXLen 1)429 430 ret <vscale x 1 x i32> %a431}432 433define <vscale x 2 x i32> @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {434; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32:435; CHECK: # %bb.0: # %entry436; CHECK-NEXT: csrwi vxrm, 0437; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma438; CHECK-NEXT: vnclip.wv v11, v8, v10439; CHECK-NEXT: vmv.v.v v8, v11440; CHECK-NEXT: ret441entry:442 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32(443 <vscale x 2 x i32> poison,444 <vscale x 2 x i64> %0,445 <vscale x 2 x i32> %1,446 iXLen 0, iXLen %2)447 448 ret <vscale x 2 x i32> %a449}450 451define <vscale x 2 x i32> @intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {452; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32:453; CHECK: # %bb.0: # %entry454; CHECK-NEXT: csrwi vxrm, 0455; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu456; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.nxv2i32(460 <vscale x 2 x i32> %0,461 <vscale x 2 x i64> %1,462 <vscale x 2 x i32> %2,463 <vscale x 2 x i1> %3,464 iXLen 0, iXLen %4, iXLen 1)465 466 ret <vscale x 2 x i32> %a467}468 469define <vscale x 4 x i32> @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: csrwi vxrm, 0473; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma474; CHECK-NEXT: vnclip.wv v14, v8, v12475; CHECK-NEXT: vmv.v.v v8, v14476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32(479 <vscale x 4 x i32> poison,480 <vscale x 4 x i64> %0,481 <vscale x 4 x i32> %1,482 iXLen 0, iXLen %2)483 484 ret <vscale x 4 x i32> %a485}486 487define <vscale x 4 x i32> @intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: csrwi vxrm, 0491; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu492; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t493; CHECK-NEXT: ret494entry:495 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.nxv4i32(496 <vscale x 4 x i32> %0,497 <vscale x 4 x i64> %1,498 <vscale x 4 x i32> %2,499 <vscale x 4 x i1> %3,500 iXLen 0, iXLen %4, iXLen 1)501 502 ret <vscale x 4 x i32> %a503}504 505define <vscale x 8 x i32> @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {506; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32:507; CHECK: # %bb.0: # %entry508; CHECK-NEXT: csrwi vxrm, 0509; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma510; CHECK-NEXT: vnclip.wv v20, v8, v16511; CHECK-NEXT: vmv.v.v v8, v20512; CHECK-NEXT: ret513entry:514 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32(515 <vscale x 8 x i32> poison,516 <vscale x 8 x i64> %0,517 <vscale x 8 x i32> %1,518 iXLen 0, iXLen %2)519 520 ret <vscale x 8 x i32> %a521}522 523define <vscale x 8 x i32> @intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {524; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32:525; CHECK: # %bb.0: # %entry526; CHECK-NEXT: csrwi vxrm, 0527; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu528; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t529; CHECK-NEXT: ret530entry:531 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32(532 <vscale x 8 x i32> %0,533 <vscale x 8 x i64> %1,534 <vscale x 8 x i32> %2,535 <vscale x 8 x i1> %3,536 iXLen 0, iXLen %4, iXLen 1)537 538 ret <vscale x 8 x i32> %a539}540 541define <vscale x 1 x i8> @intrinsic_vnclip_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, iXLen %1, iXLen %2) nounwind {542; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16:543; CHECK: # %bb.0: # %entry544; CHECK-NEXT: csrwi vxrm, 0545; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma546; CHECK-NEXT: vnclip.wx v8, v8, a0547; CHECK-NEXT: ret548entry:549 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(550 <vscale x 1 x i8> poison,551 <vscale x 1 x i16> %0,552 iXLen %1,553 iXLen 0, iXLen %2)554 555 ret <vscale x 1 x i8> %a556}557 558define <vscale x 1 x i8> @intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {559; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16:560; CHECK: # %bb.0: # %entry561; CHECK-NEXT: csrwi vxrm, 0562; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu563; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t564; CHECK-NEXT: ret565entry:566 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(567 <vscale x 1 x i8> %0,568 <vscale x 1 x i16> %1,569 iXLen %2,570 <vscale x 1 x i1> %3,571 iXLen 0, iXLen %4, iXLen 1)572 573 ret <vscale x 1 x i8> %a574}575 576define <vscale x 2 x i8> @intrinsic_vnclip_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, iXLen %1, iXLen %2) nounwind {577; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16:578; CHECK: # %bb.0: # %entry579; CHECK-NEXT: csrwi vxrm, 0580; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma581; CHECK-NEXT: vnclip.wx v8, v8, a0582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(585 <vscale x 2 x i8> poison,586 <vscale x 2 x i16> %0,587 iXLen %1,588 iXLen 0, iXLen %2)589 590 ret <vscale x 2 x i8> %a591}592 593define <vscale x 2 x i8> @intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {594; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16:595; CHECK: # %bb.0: # %entry596; CHECK-NEXT: csrwi vxrm, 0597; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu598; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t599; CHECK-NEXT: ret600entry:601 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(602 <vscale x 2 x i8> %0,603 <vscale x 2 x i16> %1,604 iXLen %2,605 <vscale x 2 x i1> %3,606 iXLen 0, iXLen %4, iXLen 1)607 608 ret <vscale x 2 x i8> %a609}610 611define <vscale x 4 x i8> @intrinsic_vnclip_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, iXLen %1, iXLen %2) nounwind {612; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16:613; CHECK: # %bb.0: # %entry614; CHECK-NEXT: csrwi vxrm, 0615; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma616; CHECK-NEXT: vnclip.wx v8, v8, a0617; CHECK-NEXT: ret618entry:619 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(620 <vscale x 4 x i8> poison,621 <vscale x 4 x i16> %0,622 iXLen %1,623 iXLen 0, iXLen %2)624 625 ret <vscale x 4 x i8> %a626}627 628define <vscale x 4 x i8> @intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {629; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16:630; CHECK: # %bb.0: # %entry631; CHECK-NEXT: csrwi vxrm, 0632; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu633; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t634; CHECK-NEXT: ret635entry:636 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(637 <vscale x 4 x i8> %0,638 <vscale x 4 x i16> %1,639 iXLen %2,640 <vscale x 4 x i1> %3,641 iXLen 0, iXLen %4, iXLen 1)642 643 ret <vscale x 4 x i8> %a644}645 646define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, iXLen %1, iXLen %2) nounwind {647; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16:648; CHECK: # %bb.0: # %entry649; CHECK-NEXT: csrwi vxrm, 0650; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma651; CHECK-NEXT: vnclip.wx v10, v8, a0652; CHECK-NEXT: vmv.v.v v8, v10653; CHECK-NEXT: ret654entry:655 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(656 <vscale x 8 x i8> poison,657 <vscale x 8 x i16> %0,658 iXLen %1,659 iXLen 0, iXLen %2)660 661 ret <vscale x 8 x i8> %a662}663 664define <vscale x 8 x i8> @intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {665; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16:666; CHECK: # %bb.0: # %entry667; CHECK-NEXT: csrwi vxrm, 0668; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu669; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t670; CHECK-NEXT: ret671entry:672 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(673 <vscale x 8 x i8> %0,674 <vscale x 8 x i16> %1,675 iXLen %2,676 <vscale x 8 x i1> %3,677 iXLen 0, iXLen %4, iXLen 1)678 679 ret <vscale x 8 x i8> %a680}681 682define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, iXLen %1, iXLen %2) nounwind {683; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16:684; CHECK: # %bb.0: # %entry685; CHECK-NEXT: csrwi vxrm, 0686; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma687; CHECK-NEXT: vnclip.wx v12, v8, a0688; CHECK-NEXT: vmv.v.v v8, v12689; CHECK-NEXT: ret690entry:691 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(692 <vscale x 16 x i8> poison,693 <vscale x 16 x i16> %0,694 iXLen %1,695 iXLen 0, iXLen %2)696 697 ret <vscale x 16 x i8> %a698}699 700define <vscale x 16 x i8> @intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {701; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: csrwi vxrm, 0704; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu705; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t706; CHECK-NEXT: ret707entry:708 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(709 <vscale x 16 x i8> %0,710 <vscale x 16 x i16> %1,711 iXLen %2,712 <vscale x 16 x i1> %3,713 iXLen 0, iXLen %4, iXLen 1)714 715 ret <vscale x 16 x i8> %a716}717 718define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, iXLen %1, iXLen %2) nounwind {719; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16:720; CHECK: # %bb.0: # %entry721; CHECK-NEXT: csrwi vxrm, 0722; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma723; CHECK-NEXT: vnclip.wx v16, v8, a0724; CHECK-NEXT: vmv.v.v v8, v16725; CHECK-NEXT: ret726entry:727 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(728 <vscale x 32 x i8> poison,729 <vscale x 32 x i16> %0,730 iXLen %1,731 iXLen 0, iXLen %2)732 733 ret <vscale x 32 x i8> %a734}735 736define <vscale x 32 x i8> @intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {737; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16:738; CHECK: # %bb.0: # %entry739; CHECK-NEXT: csrwi vxrm, 0740; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu741; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t742; CHECK-NEXT: ret743entry:744 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(745 <vscale x 32 x i8> %0,746 <vscale x 32 x i16> %1,747 iXLen %2,748 <vscale x 32 x i1> %3,749 iXLen 0, iXLen %4, iXLen 1)750 751 ret <vscale x 32 x i8> %a752}753 754define <vscale x 1 x i16> @intrinsic_vnclip_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1, iXLen %2) nounwind {755; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32:756; CHECK: # %bb.0: # %entry757; CHECK-NEXT: csrwi vxrm, 0758; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma759; CHECK-NEXT: vnclip.wx v8, v8, a0760; CHECK-NEXT: ret761entry:762 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(763 <vscale x 1 x i16> poison,764 <vscale x 1 x i32> %0,765 iXLen %1,766 iXLen 0, iXLen %2)767 768 ret <vscale x 1 x i16> %a769}770 771define <vscale x 1 x i16> @intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {772; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32:773; CHECK: # %bb.0: # %entry774; CHECK-NEXT: csrwi vxrm, 0775; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu776; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t777; CHECK-NEXT: ret778entry:779 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(780 <vscale x 1 x i16> %0,781 <vscale x 1 x i32> %1,782 iXLen %2,783 <vscale x 1 x i1> %3,784 iXLen 0, iXLen %4, iXLen 1)785 786 ret <vscale x 1 x i16> %a787}788 789define <vscale x 2 x i16> @intrinsic_vnclip_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1, iXLen %2) nounwind {790; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32:791; CHECK: # %bb.0: # %entry792; CHECK-NEXT: csrwi vxrm, 0793; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma794; CHECK-NEXT: vnclip.wx v8, v8, a0795; CHECK-NEXT: ret796entry:797 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(798 <vscale x 2 x i16> poison,799 <vscale x 2 x i32> %0,800 iXLen %1,801 iXLen 0, iXLen %2)802 803 ret <vscale x 2 x i16> %a804}805 806define <vscale x 2 x i16> @intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {807; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32:808; CHECK: # %bb.0: # %entry809; CHECK-NEXT: csrwi vxrm, 0810; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu811; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t812; CHECK-NEXT: ret813entry:814 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(815 <vscale x 2 x i16> %0,816 <vscale x 2 x i32> %1,817 iXLen %2,818 <vscale x 2 x i1> %3,819 iXLen 0, iXLen %4, iXLen 1)820 821 ret <vscale x 2 x i16> %a822}823 824define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1, iXLen %2) nounwind {825; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32:826; CHECK: # %bb.0: # %entry827; CHECK-NEXT: csrwi vxrm, 0828; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma829; CHECK-NEXT: vnclip.wx v10, v8, a0830; CHECK-NEXT: vmv.v.v v8, v10831; CHECK-NEXT: ret832entry:833 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(834 <vscale x 4 x i16> poison,835 <vscale x 4 x i32> %0,836 iXLen %1,837 iXLen 0, iXLen %2)838 839 ret <vscale x 4 x i16> %a840}841 842define <vscale x 4 x i16> @intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {843; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32:844; CHECK: # %bb.0: # %entry845; CHECK-NEXT: csrwi vxrm, 0846; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu847; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t848; CHECK-NEXT: ret849entry:850 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(851 <vscale x 4 x i16> %0,852 <vscale x 4 x i32> %1,853 iXLen %2,854 <vscale x 4 x i1> %3,855 iXLen 0, iXLen %4, iXLen 1)856 857 ret <vscale x 4 x i16> %a858}859 860define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1, iXLen %2) nounwind {861; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32:862; CHECK: # %bb.0: # %entry863; CHECK-NEXT: csrwi vxrm, 0864; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma865; CHECK-NEXT: vnclip.wx v12, v8, a0866; CHECK-NEXT: vmv.v.v v8, v12867; CHECK-NEXT: ret868entry:869 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(870 <vscale x 8 x i16> poison,871 <vscale x 8 x i32> %0,872 iXLen %1,873 iXLen 0, iXLen %2)874 875 ret <vscale x 8 x i16> %a876}877 878define <vscale x 8 x i16> @intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {879; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32:880; CHECK: # %bb.0: # %entry881; CHECK-NEXT: csrwi vxrm, 0882; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu883; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t884; CHECK-NEXT: ret885entry:886 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(887 <vscale x 8 x i16> %0,888 <vscale x 8 x i32> %1,889 iXLen %2,890 <vscale x 8 x i1> %3,891 iXLen 0, iXLen %4, iXLen 1)892 893 ret <vscale x 8 x i16> %a894}895 896define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1, iXLen %2) nounwind {897; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32:898; CHECK: # %bb.0: # %entry899; CHECK-NEXT: csrwi vxrm, 0900; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma901; CHECK-NEXT: vnclip.wx v16, v8, a0902; CHECK-NEXT: vmv.v.v v8, v16903; CHECK-NEXT: ret904entry:905 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(906 <vscale x 16 x i16> poison,907 <vscale x 16 x i32> %0,908 iXLen %1,909 iXLen 0, iXLen %2)910 911 ret <vscale x 16 x i16> %a912}913 914define <vscale x 16 x i16> @intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {915; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: csrwi vxrm, 0918; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu919; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t920; CHECK-NEXT: ret921entry:922 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(923 <vscale x 16 x i16> %0,924 <vscale x 16 x i32> %1,925 iXLen %2,926 <vscale x 16 x i1> %3,927 iXLen 0, iXLen %4, iXLen 1)928 929 ret <vscale x 16 x i16> %a930}931 932define <vscale x 1 x i32> @intrinsic_vnclip_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1, iXLen %2) nounwind {933; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64:934; CHECK: # %bb.0: # %entry935; CHECK-NEXT: csrwi vxrm, 0936; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma937; CHECK-NEXT: vnclip.wx v8, v8, a0938; CHECK-NEXT: ret939entry:940 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(941 <vscale x 1 x i32> poison,942 <vscale x 1 x i64> %0,943 iXLen %1,944 iXLen 0, iXLen %2)945 946 ret <vscale x 1 x i32> %a947}948 949define <vscale x 1 x i32> @intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {950; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64:951; CHECK: # %bb.0: # %entry952; CHECK-NEXT: csrwi vxrm, 0953; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu954; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t955; CHECK-NEXT: ret956entry:957 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64(958 <vscale x 1 x i32> %0,959 <vscale x 1 x i64> %1,960 iXLen %2,961 <vscale x 1 x i1> %3,962 iXLen 0, iXLen %4, iXLen 1)963 964 ret <vscale x 1 x i32> %a965}966 967define <vscale x 2 x i32> @intrinsic_vnclip_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1, iXLen %2) nounwind {968; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64:969; CHECK: # %bb.0: # %entry970; CHECK-NEXT: csrwi vxrm, 0971; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma972; CHECK-NEXT: vnclip.wx v10, v8, a0973; CHECK-NEXT: vmv.v.v v8, v10974; CHECK-NEXT: ret975entry:976 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(977 <vscale x 2 x i32> poison,978 <vscale x 2 x i64> %0,979 iXLen %1,980 iXLen 0, iXLen %2)981 982 ret <vscale x 2 x i32> %a983}984 985define <vscale x 2 x i32> @intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {986; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64:987; CHECK: # %bb.0: # %entry988; CHECK-NEXT: csrwi vxrm, 0989; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu990; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t991; CHECK-NEXT: ret992entry:993 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64(994 <vscale x 2 x i32> %0,995 <vscale x 2 x i64> %1,996 iXLen %2,997 <vscale x 2 x i1> %3,998 iXLen 0, iXLen %4, iXLen 1)999 1000 ret <vscale x 2 x i32> %a1001}1002 1003define <vscale x 4 x i32> @intrinsic_vnclip_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1, iXLen %2) nounwind {1004; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64:1005; CHECK: # %bb.0: # %entry1006; CHECK-NEXT: csrwi vxrm, 01007; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1008; CHECK-NEXT: vnclip.wx v12, v8, a01009; CHECK-NEXT: vmv.v.v v8, v121010; CHECK-NEXT: ret1011entry:1012 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(1013 <vscale x 4 x i32> poison,1014 <vscale x 4 x i64> %0,1015 iXLen %1,1016 iXLen 0, iXLen %2)1017 1018 ret <vscale x 4 x i32> %a1019}1020 1021define <vscale x 4 x i32> @intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1022; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64:1023; CHECK: # %bb.0: # %entry1024; CHECK-NEXT: csrwi vxrm, 01025; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1026; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t1027; CHECK-NEXT: ret1028entry:1029 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64(1030 <vscale x 4 x i32> %0,1031 <vscale x 4 x i64> %1,1032 iXLen %2,1033 <vscale x 4 x i1> %3,1034 iXLen 0, iXLen %4, iXLen 1)1035 1036 ret <vscale x 4 x i32> %a1037}1038 1039define <vscale x 8 x i32> @intrinsic_vnclip_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1, iXLen %2) nounwind {1040; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64:1041; CHECK: # %bb.0: # %entry1042; CHECK-NEXT: csrwi vxrm, 01043; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1044; CHECK-NEXT: vnclip.wx v16, v8, a01045; CHECK-NEXT: vmv.v.v v8, v161046; CHECK-NEXT: ret1047entry:1048 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(1049 <vscale x 8 x i32> poison,1050 <vscale x 8 x i64> %0,1051 iXLen %1,1052 iXLen 0, iXLen %2)1053 1054 ret <vscale x 8 x i32> %a1055}1056 1057define <vscale x 8 x i32> @intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1058; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64:1059; CHECK: # %bb.0: # %entry1060; CHECK-NEXT: csrwi vxrm, 01061; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1062; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t1063; CHECK-NEXT: ret1064entry:1065 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64(1066 <vscale x 8 x i32> %0,1067 <vscale x 8 x i64> %1,1068 iXLen %2,1069 <vscale x 8 x i1> %3,1070 iXLen 0, iXLen %4, iXLen 1)1071 1072 ret <vscale x 8 x i32> %a1073}1074 1075define <vscale x 1 x i8> @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, iXLen %1) nounwind {1076; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8:1077; CHECK: # %bb.0: # %entry1078; CHECK-NEXT: csrwi vxrm, 01079; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1080; CHECK-NEXT: vnclip.wi v8, v8, 91081; CHECK-NEXT: ret1082entry:1083 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(1084 <vscale x 1 x i8> poison,1085 <vscale x 1 x i16> %0,1086 iXLen 9,1087 iXLen 0, iXLen %1)1088 1089 ret <vscale x 1 x i8> %a1090}1091 1092define <vscale x 1 x i8> @intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1093; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8:1094; CHECK: # %bb.0: # %entry1095; CHECK-NEXT: csrwi vxrm, 01096; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1097; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1098; CHECK-NEXT: ret1099entry:1100 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16(1101 <vscale x 1 x i8> %0,1102 <vscale x 1 x i16> %1,1103 iXLen 9,1104 <vscale x 1 x i1> %2,1105 iXLen 0, iXLen %3, iXLen 1)1106 1107 ret <vscale x 1 x i8> %a1108}1109 1110define <vscale x 2 x i8> @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, iXLen %1) nounwind {1111; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8:1112; CHECK: # %bb.0: # %entry1113; CHECK-NEXT: csrwi vxrm, 01114; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1115; CHECK-NEXT: vnclip.wi v8, v8, 91116; CHECK-NEXT: ret1117entry:1118 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(1119 <vscale x 2 x i8> poison,1120 <vscale x 2 x i16> %0,1121 iXLen 9,1122 iXLen 0, iXLen %1)1123 1124 ret <vscale x 2 x i8> %a1125}1126 1127define <vscale x 2 x i8> @intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1128; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8:1129; CHECK: # %bb.0: # %entry1130; CHECK-NEXT: csrwi vxrm, 01131; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1132; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1133; CHECK-NEXT: ret1134entry:1135 %a = call <vscale x 2 x i8> @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16(1136 <vscale x 2 x i8> %0,1137 <vscale x 2 x i16> %1,1138 iXLen 9,1139 <vscale x 2 x i1> %2,1140 iXLen 0, iXLen %3, iXLen 1)1141 1142 ret <vscale x 2 x i8> %a1143}1144 1145define <vscale x 4 x i8> @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, iXLen %1) nounwind {1146; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8:1147; CHECK: # %bb.0: # %entry1148; CHECK-NEXT: csrwi vxrm, 01149; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1150; CHECK-NEXT: vnclip.wi v8, v8, 91151; CHECK-NEXT: ret1152entry:1153 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(1154 <vscale x 4 x i8> poison,1155 <vscale x 4 x i16> %0,1156 iXLen 9,1157 iXLen 0, iXLen %1)1158 1159 ret <vscale x 4 x i8> %a1160}1161 1162define <vscale x 4 x i8> @intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1163; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8:1164; CHECK: # %bb.0: # %entry1165; CHECK-NEXT: csrwi vxrm, 01166; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1167; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1168; CHECK-NEXT: ret1169entry:1170 %a = call <vscale x 4 x i8> @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16(1171 <vscale x 4 x i8> %0,1172 <vscale x 4 x i16> %1,1173 iXLen 9,1174 <vscale x 4 x i1> %2,1175 iXLen 0, iXLen %3, iXLen 1)1176 1177 ret <vscale x 4 x i8> %a1178}1179 1180define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, iXLen %1) nounwind {1181; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8:1182; CHECK: # %bb.0: # %entry1183; CHECK-NEXT: csrwi vxrm, 01184; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1185; CHECK-NEXT: vnclip.wi v10, v8, 91186; CHECK-NEXT: vmv.v.v v8, v101187; CHECK-NEXT: ret1188entry:1189 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(1190 <vscale x 8 x i8> poison,1191 <vscale x 8 x i16> %0,1192 iXLen 9,1193 iXLen 0, iXLen %1)1194 1195 ret <vscale x 8 x i8> %a1196}1197 1198define <vscale x 8 x i8> @intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1199; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8:1200; CHECK: # %bb.0: # %entry1201; CHECK-NEXT: csrwi vxrm, 01202; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1203; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t1204; CHECK-NEXT: ret1205entry:1206 %a = call <vscale x 8 x i8> @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16(1207 <vscale x 8 x i8> %0,1208 <vscale x 8 x i16> %1,1209 iXLen 9,1210 <vscale x 8 x i1> %2,1211 iXLen 0, iXLen %3, iXLen 1)1212 1213 ret <vscale x 8 x i8> %a1214}1215 1216define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, iXLen %1) nounwind {1217; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8:1218; CHECK: # %bb.0: # %entry1219; CHECK-NEXT: csrwi vxrm, 01220; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1221; CHECK-NEXT: vnclip.wi v12, v8, 91222; CHECK-NEXT: vmv.v.v v8, v121223; CHECK-NEXT: ret1224entry:1225 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(1226 <vscale x 16 x i8> poison,1227 <vscale x 16 x i16> %0,1228 iXLen 9,1229 iXLen 0, iXLen %1)1230 1231 ret <vscale x 16 x i8> %a1232}1233 1234define <vscale x 16 x i8> @intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1235; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8:1236; CHECK: # %bb.0: # %entry1237; CHECK-NEXT: csrwi vxrm, 01238; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1239; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t1240; CHECK-NEXT: ret1241entry:1242 %a = call <vscale x 16 x i8> @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16(1243 <vscale x 16 x i8> %0,1244 <vscale x 16 x i16> %1,1245 iXLen 9,1246 <vscale x 16 x i1> %2,1247 iXLen 0, iXLen %3, iXLen 1)1248 1249 ret <vscale x 16 x i8> %a1250}1251 1252define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, iXLen %1) nounwind {1253; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8:1254; CHECK: # %bb.0: # %entry1255; CHECK-NEXT: csrwi vxrm, 01256; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1257; CHECK-NEXT: vnclip.wi v16, v8, 91258; CHECK-NEXT: vmv.v.v v8, v161259; CHECK-NEXT: ret1260entry:1261 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(1262 <vscale x 32 x i8> poison,1263 <vscale x 32 x i16> %0,1264 iXLen 9,1265 iXLen 0, iXLen %1)1266 1267 ret <vscale x 32 x i8> %a1268}1269 1270define <vscale x 32 x i8> @intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1271; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8:1272; CHECK: # %bb.0: # %entry1273; CHECK-NEXT: csrwi vxrm, 01274; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1275; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t1276; CHECK-NEXT: ret1277entry:1278 %a = call <vscale x 32 x i8> @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16(1279 <vscale x 32 x i8> %0,1280 <vscale x 32 x i16> %1,1281 iXLen 9,1282 <vscale x 32 x i1> %2,1283 iXLen 0, iXLen %3, iXLen 1)1284 1285 ret <vscale x 32 x i8> %a1286}1287 1288define <vscale x 1 x i16> @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, iXLen %1) nounwind {1289; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16:1290; CHECK: # %bb.0: # %entry1291; CHECK-NEXT: csrwi vxrm, 01292; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1293; CHECK-NEXT: vnclip.wi v8, v8, 91294; CHECK-NEXT: ret1295entry:1296 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(1297 <vscale x 1 x i16> poison,1298 <vscale x 1 x i32> %0,1299 iXLen 9,1300 iXLen 0, iXLen %1)1301 1302 ret <vscale x 1 x i16> %a1303}1304 1305define <vscale x 1 x i16> @intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1306; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16:1307; CHECK: # %bb.0: # %entry1308; CHECK-NEXT: csrwi vxrm, 01309; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1310; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1311; CHECK-NEXT: ret1312entry:1313 %a = call <vscale x 1 x i16> @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32(1314 <vscale x 1 x i16> %0,1315 <vscale x 1 x i32> %1,1316 iXLen 9,1317 <vscale x 1 x i1> %2,1318 iXLen 0, iXLen %3, iXLen 1)1319 1320 ret <vscale x 1 x i16> %a1321}1322 1323define <vscale x 2 x i16> @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, iXLen %1) nounwind {1324; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16:1325; CHECK: # %bb.0: # %entry1326; CHECK-NEXT: csrwi vxrm, 01327; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1328; CHECK-NEXT: vnclip.wi v8, v8, 91329; CHECK-NEXT: ret1330entry:1331 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(1332 <vscale x 2 x i16> poison,1333 <vscale x 2 x i32> %0,1334 iXLen 9,1335 iXLen 0, iXLen %1)1336 1337 ret <vscale x 2 x i16> %a1338}1339 1340define <vscale x 2 x i16> @intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1341; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16:1342; CHECK: # %bb.0: # %entry1343; CHECK-NEXT: csrwi vxrm, 01344; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1345; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1346; CHECK-NEXT: ret1347entry:1348 %a = call <vscale x 2 x i16> @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32(1349 <vscale x 2 x i16> %0,1350 <vscale x 2 x i32> %1,1351 iXLen 9,1352 <vscale x 2 x i1> %2,1353 iXLen 0, iXLen %3, iXLen 1)1354 1355 ret <vscale x 2 x i16> %a1356}1357 1358define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, iXLen %1) nounwind {1359; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16:1360; CHECK: # %bb.0: # %entry1361; CHECK-NEXT: csrwi vxrm, 01362; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1363; CHECK-NEXT: vnclip.wi v10, v8, 91364; CHECK-NEXT: vmv.v.v v8, v101365; CHECK-NEXT: ret1366entry:1367 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(1368 <vscale x 4 x i16> poison,1369 <vscale x 4 x i32> %0,1370 iXLen 9,1371 iXLen 0, iXLen %1)1372 1373 ret <vscale x 4 x i16> %a1374}1375 1376define <vscale x 4 x i16> @intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1377; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16:1378; CHECK: # %bb.0: # %entry1379; CHECK-NEXT: csrwi vxrm, 01380; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1381; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t1382; CHECK-NEXT: ret1383entry:1384 %a = call <vscale x 4 x i16> @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32(1385 <vscale x 4 x i16> %0,1386 <vscale x 4 x i32> %1,1387 iXLen 9,1388 <vscale x 4 x i1> %2,1389 iXLen 0, iXLen %3, iXLen 1)1390 1391 ret <vscale x 4 x i16> %a1392}1393 1394define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, iXLen %1) nounwind {1395; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16:1396; CHECK: # %bb.0: # %entry1397; CHECK-NEXT: csrwi vxrm, 01398; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1399; CHECK-NEXT: vnclip.wi v12, v8, 91400; CHECK-NEXT: vmv.v.v v8, v121401; CHECK-NEXT: ret1402entry:1403 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(1404 <vscale x 8 x i16> poison,1405 <vscale x 8 x i32> %0,1406 iXLen 9,1407 iXLen 0, iXLen %1)1408 1409 ret <vscale x 8 x i16> %a1410}1411 1412define <vscale x 8 x i16> @intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1413; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16:1414; CHECK: # %bb.0: # %entry1415; CHECK-NEXT: csrwi vxrm, 01416; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1417; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t1418; CHECK-NEXT: ret1419entry:1420 %a = call <vscale x 8 x i16> @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32(1421 <vscale x 8 x i16> %0,1422 <vscale x 8 x i32> %1,1423 iXLen 9,1424 <vscale x 8 x i1> %2,1425 iXLen 0, iXLen %3, iXLen 1)1426 1427 ret <vscale x 8 x i16> %a1428}1429 1430define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, iXLen %1) nounwind {1431; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16:1432; CHECK: # %bb.0: # %entry1433; CHECK-NEXT: csrwi vxrm, 01434; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1435; CHECK-NEXT: vnclip.wi v16, v8, 91436; CHECK-NEXT: vmv.v.v v8, v161437; CHECK-NEXT: ret1438entry:1439 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(1440 <vscale x 16 x i16> poison,1441 <vscale x 16 x i32> %0,1442 iXLen 9,1443 iXLen 0, iXLen %1)1444 1445 ret <vscale x 16 x i16> %a1446}1447 1448define <vscale x 16 x i16> @intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1449; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16:1450; CHECK: # %bb.0: # %entry1451; CHECK-NEXT: csrwi vxrm, 01452; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1453; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t1454; CHECK-NEXT: ret1455entry:1456 %a = call <vscale x 16 x i16> @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32(1457 <vscale x 16 x i16> %0,1458 <vscale x 16 x i32> %1,1459 iXLen 9,1460 <vscale x 16 x i1> %2,1461 iXLen 0, iXLen %3, iXLen 1)1462 1463 ret <vscale x 16 x i16> %a1464}1465 1466define <vscale x 1 x i32> @intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, iXLen %1) nounwind {1467; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32:1468; CHECK: # %bb.0: # %entry1469; CHECK-NEXT: csrwi vxrm, 01470; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1471; CHECK-NEXT: vnclip.wi v8, v8, 91472; CHECK-NEXT: ret1473entry:1474 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(1475 <vscale x 1 x i32> poison,1476 <vscale x 1 x i64> %0,1477 iXLen 9,1478 iXLen 0, iXLen %1)1479 1480 ret <vscale x 1 x i32> %a1481}1482 1483define <vscale x 1 x i32> @intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1484; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32:1485; CHECK: # %bb.0: # %entry1486; CHECK-NEXT: csrwi vxrm, 01487; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1488; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t1489; CHECK-NEXT: ret1490entry:1491 %a = call <vscale x 1 x i32> @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64(1492 <vscale x 1 x i32> %0,1493 <vscale x 1 x i64> %1,1494 iXLen 9,1495 <vscale x 1 x i1> %2,1496 iXLen 0, iXLen %3, iXLen 1)1497 1498 ret <vscale x 1 x i32> %a1499}1500 1501define <vscale x 2 x i32> @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, iXLen %1) nounwind {1502; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32:1503; CHECK: # %bb.0: # %entry1504; CHECK-NEXT: csrwi vxrm, 01505; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1506; CHECK-NEXT: vnclip.wi v10, v8, 91507; CHECK-NEXT: vmv.v.v v8, v101508; CHECK-NEXT: ret1509entry:1510 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(1511 <vscale x 2 x i32> poison,1512 <vscale x 2 x i64> %0,1513 iXLen 9,1514 iXLen 0, iXLen %1)1515 1516 ret <vscale x 2 x i32> %a1517}1518 1519define <vscale x 2 x i32> @intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1520; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32:1521; CHECK: # %bb.0: # %entry1522; CHECK-NEXT: csrwi vxrm, 01523; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1524; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t1525; CHECK-NEXT: ret1526entry:1527 %a = call <vscale x 2 x i32> @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64(1528 <vscale x 2 x i32> %0,1529 <vscale x 2 x i64> %1,1530 iXLen 9,1531 <vscale x 2 x i1> %2,1532 iXLen 0, iXLen %3, iXLen 1)1533 1534 ret <vscale x 2 x i32> %a1535}1536 1537define <vscale x 4 x i32> @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, iXLen %1) nounwind {1538; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32:1539; CHECK: # %bb.0: # %entry1540; CHECK-NEXT: csrwi vxrm, 01541; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1542; CHECK-NEXT: vnclip.wi v12, v8, 91543; CHECK-NEXT: vmv.v.v v8, v121544; CHECK-NEXT: ret1545entry:1546 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(1547 <vscale x 4 x i32> poison,1548 <vscale x 4 x i64> %0,1549 iXLen 9,1550 iXLen 0, iXLen %1)1551 1552 ret <vscale x 4 x i32> %a1553}1554 1555define <vscale x 4 x i32> @intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1556; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32:1557; CHECK: # %bb.0: # %entry1558; CHECK-NEXT: csrwi vxrm, 01559; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1560; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t1561; CHECK-NEXT: ret1562entry:1563 %a = call <vscale x 4 x i32> @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64(1564 <vscale x 4 x i32> %0,1565 <vscale x 4 x i64> %1,1566 iXLen 9,1567 <vscale x 4 x i1> %2,1568 iXLen 0, iXLen %3, iXLen 1)1569 1570 ret <vscale x 4 x i32> %a1571}1572 1573define <vscale x 8 x i32> @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, iXLen %1) nounwind {1574; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32:1575; CHECK: # %bb.0: # %entry1576; CHECK-NEXT: csrwi vxrm, 01577; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1578; CHECK-NEXT: vnclip.wi v16, v8, 91579; CHECK-NEXT: vmv.v.v v8, v161580; CHECK-NEXT: ret1581entry:1582 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(1583 <vscale x 8 x i32> poison,1584 <vscale x 8 x i64> %0,1585 iXLen 9,1586 iXLen 0, iXLen %1)1587 1588 ret <vscale x 8 x i32> %a1589}1590 1591define <vscale x 8 x i32> @intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1592; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32:1593; CHECK: # %bb.0: # %entry1594; CHECK-NEXT: csrwi vxrm, 01595; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1596; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t1597; CHECK-NEXT: ret1598entry:1599 %a = call <vscale x 8 x i32> @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64(1600 <vscale x 8 x i32> %0,1601 <vscale x 8 x i64> %1,1602 iXLen 9,1603 <vscale x 8 x i1> %2,1604 iXLen 0, iXLen %3, iXLen 1)1605 1606 ret <vscale x 8 x i32> %a1607}1608