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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vnsrl.wv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i16> %0,17 <vscale x 1 x i8> %1,18 iXLen %2)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.nxv1i8(31 <vscale x 1 x i8> %0,32 <vscale x 1 x i16> %1,33 <vscale x 1 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT: vnsrl.wv v8, v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8(48 <vscale x 2 x i8> poison,49 <vscale x 2 x i16> %0,50 <vscale x 2 x i8> %1,51 iXLen %2)52 53 ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu60; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.nxv2i8(64 <vscale x 2 x i8> %0,65 <vscale x 2 x i16> %1,66 <vscale x 2 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma77; CHECK-NEXT: vnsrl.wv v8, v8, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8(81 <vscale x 4 x i8> poison,82 <vscale x 4 x i16> %0,83 <vscale x 4 x i8> %1,84 iXLen %2)85 86 ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu93; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.nxv4i8(97 <vscale x 4 x i8> %0,98 <vscale x 4 x i16> %1,99 <vscale x 4 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma110; CHECK-NEXT: vnsrl.wv v11, v8, v10111; CHECK-NEXT: vmv.v.v v8, v11112; CHECK-NEXT: ret113entry:114 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8(115 <vscale x 8 x i8> poison,116 <vscale x 8 x i16> %0,117 <vscale x 8 x i8> %1,118 iXLen %2)119 120 ret <vscale x 8 x i8> %a121}122 123define <vscale x 8 x i8> @intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {124; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu127; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t128; CHECK-NEXT: ret129entry:130 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.nxv8i8(131 <vscale x 8 x i8> %0,132 <vscale x 8 x i16> %1,133 <vscale x 8 x i8> %2,134 <vscale x 8 x i1> %3,135 iXLen %4, iXLen 1)136 137 ret <vscale x 8 x i8> %a138}139 140define <vscale x 16 x i8> @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {141; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8:142; CHECK: # %bb.0: # %entry143; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma144; CHECK-NEXT: vnsrl.wv v14, v8, v12145; CHECK-NEXT: vmv.v.v v8, v14146; CHECK-NEXT: ret147entry:148 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8(149 <vscale x 16 x i8> poison,150 <vscale x 16 x i16> %0,151 <vscale x 16 x i8> %1,152 iXLen %2)153 154 ret <vscale x 16 x i8> %a155}156 157define <vscale x 16 x i8> @intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {158; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu161; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.nxv16i8(165 <vscale x 16 x i8> %0,166 <vscale x 16 x i16> %1,167 <vscale x 16 x i8> %2,168 <vscale x 16 x i1> %3,169 iXLen %4, iXLen 1)170 171 ret <vscale x 16 x i8> %a172}173 174define <vscale x 32 x i8> @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {175; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8:176; CHECK: # %bb.0: # %entry177; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma178; CHECK-NEXT: vnsrl.wv v20, v8, v16179; CHECK-NEXT: vmv.v.v v8, v20180; CHECK-NEXT: ret181entry:182 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8(183 <vscale x 32 x i8> poison,184 <vscale x 32 x i16> %0,185 <vscale x 32 x i8> %1,186 iXLen %2)187 188 ret <vscale x 32 x i8> %a189}190 191define <vscale x 32 x i8> @intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {192; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8:193; CHECK: # %bb.0: # %entry194; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu195; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t196; CHECK-NEXT: ret197entry:198 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.nxv32i8(199 <vscale x 32 x i8> %0,200 <vscale x 32 x i16> %1,201 <vscale x 32 x i8> %2,202 <vscale x 32 x i1> %3,203 iXLen %4, iXLen 1)204 205 ret <vscale x 32 x i8> %a206}207 208define <vscale x 1 x i16> @intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {209; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma212; CHECK-NEXT: vnsrl.wv v8, v8, v9213; CHECK-NEXT: ret214entry:215 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32.nxv1i16(216 <vscale x 1 x i16> poison,217 <vscale x 1 x i32> %0,218 <vscale x 1 x i16> %1,219 iXLen %2)220 221 ret <vscale x 1 x i16> %a222}223 224define <vscale x 1 x i16> @intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {225; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu228; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t229; CHECK-NEXT: ret230entry:231 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.nxv1i16(232 <vscale x 1 x i16> %0,233 <vscale x 1 x i32> %1,234 <vscale x 1 x i16> %2,235 <vscale x 1 x i1> %3,236 iXLen %4, iXLen 1)237 238 ret <vscale x 1 x i16> %a239}240 241define <vscale x 2 x i16> @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {242; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma245; CHECK-NEXT: vnsrl.wv v8, v8, v9246; CHECK-NEXT: ret247entry:248 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(249 <vscale x 2 x i16> poison,250 <vscale x 2 x i32> %0,251 <vscale x 2 x i16> %1,252 iXLen %2)253 254 ret <vscale x 2 x i16> %a255}256 257define <vscale x 2 x i16> @intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {258; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu261; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t262; CHECK-NEXT: ret263entry:264 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.nxv2i16(265 <vscale x 2 x i16> %0,266 <vscale x 2 x i32> %1,267 <vscale x 2 x i16> %2,268 <vscale x 2 x i1> %3,269 iXLen %4, iXLen 1)270 271 ret <vscale x 2 x i16> %a272}273 274define <vscale x 4 x i16> @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {275; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16:276; CHECK: # %bb.0: # %entry277; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma278; CHECK-NEXT: vnsrl.wv v11, v8, v10279; CHECK-NEXT: vmv.v.v v8, v11280; CHECK-NEXT: ret281entry:282 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16(283 <vscale x 4 x i16> poison,284 <vscale x 4 x i32> %0,285 <vscale x 4 x i16> %1,286 iXLen %2)287 288 ret <vscale x 4 x i16> %a289}290 291define <vscale x 4 x i16> @intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {292; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16:293; CHECK: # %bb.0: # %entry294; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu295; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t296; CHECK-NEXT: ret297entry:298 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.nxv4i16(299 <vscale x 4 x i16> %0,300 <vscale x 4 x i32> %1,301 <vscale x 4 x i16> %2,302 <vscale x 4 x i1> %3,303 iXLen %4, iXLen 1)304 305 ret <vscale x 4 x i16> %a306}307 308define <vscale x 8 x i16> @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {309; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16:310; CHECK: # %bb.0: # %entry311; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma312; CHECK-NEXT: vnsrl.wv v14, v8, v12313; CHECK-NEXT: vmv.v.v v8, v14314; CHECK-NEXT: ret315entry:316 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16(317 <vscale x 8 x i16> poison,318 <vscale x 8 x i32> %0,319 <vscale x 8 x i16> %1,320 iXLen %2)321 322 ret <vscale x 8 x i16> %a323}324 325define <vscale x 8 x i16> @intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {326; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16:327; CHECK: # %bb.0: # %entry328; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu329; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.nxv8i16(333 <vscale x 8 x i16> %0,334 <vscale x 8 x i32> %1,335 <vscale x 8 x i16> %2,336 <vscale x 8 x i1> %3,337 iXLen %4, iXLen 1)338 339 ret <vscale x 8 x i16> %a340}341 342define <vscale x 16 x i16> @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {343; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16:344; CHECK: # %bb.0: # %entry345; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma346; CHECK-NEXT: vnsrl.wv v20, v8, v16347; CHECK-NEXT: vmv.v.v v8, v20348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16(351 <vscale x 16 x i16> poison,352 <vscale x 16 x i32> %0,353 <vscale x 16 x i16> %1,354 iXLen %2)355 356 ret <vscale x 16 x i16> %a357}358 359define <vscale x 16 x i16> @intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {360; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu363; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.nxv16i16(367 <vscale x 16 x i16> %0,368 <vscale x 16 x i32> %1,369 <vscale x 16 x i16> %2,370 <vscale x 16 x i1> %3,371 iXLen %4, iXLen 1)372 373 ret <vscale x 16 x i16> %a374}375 376define <vscale x 1 x i32> @intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {377; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32:378; CHECK: # %bb.0: # %entry379; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma380; CHECK-NEXT: vnsrl.wv v8, v8, v9381; CHECK-NEXT: ret382entry:383 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32(384 <vscale x 1 x i32> poison,385 <vscale x 1 x i64> %0,386 <vscale x 1 x i32> %1,387 iXLen %2)388 389 ret <vscale x 1 x i32> %a390}391 392define <vscale x 1 x i32> @intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {393; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu396; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t397; CHECK-NEXT: ret398entry:399 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32(400 <vscale x 1 x i32> %0,401 <vscale x 1 x i64> %1,402 <vscale x 1 x i32> %2,403 <vscale x 1 x i1> %3,404 iXLen %4, iXLen 1)405 406 ret <vscale x 1 x i32> %a407}408 409define <vscale x 2 x i32> @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {410; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32:411; CHECK: # %bb.0: # %entry412; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma413; CHECK-NEXT: vnsrl.wv v11, v8, v10414; CHECK-NEXT: vmv.v.v v8, v11415; CHECK-NEXT: ret416entry:417 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32(418 <vscale x 2 x i32> poison,419 <vscale x 2 x i64> %0,420 <vscale x 2 x i32> %1,421 iXLen %2)422 423 ret <vscale x 2 x i32> %a424}425 426define <vscale x 2 x i32> @intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {427; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu430; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t431; CHECK-NEXT: ret432entry:433 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32(434 <vscale x 2 x i32> %0,435 <vscale x 2 x i64> %1,436 <vscale x 2 x i32> %2,437 <vscale x 2 x i1> %3,438 iXLen %4, iXLen 1)439 440 ret <vscale x 2 x i32> %a441}442 443define <vscale x 4 x i32> @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {444; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32:445; CHECK: # %bb.0: # %entry446; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma447; CHECK-NEXT: vnsrl.wv v14, v8, v12448; CHECK-NEXT: vmv.v.v v8, v14449; CHECK-NEXT: ret450entry:451 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32(452 <vscale x 4 x i32> poison,453 <vscale x 4 x i64> %0,454 <vscale x 4 x i32> %1,455 iXLen %2)456 457 ret <vscale x 4 x i32> %a458}459 460define <vscale x 4 x i32> @intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {461; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32:462; CHECK: # %bb.0: # %entry463; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu464; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t465; CHECK-NEXT: ret466entry:467 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32(468 <vscale x 4 x i32> %0,469 <vscale x 4 x i64> %1,470 <vscale x 4 x i32> %2,471 <vscale x 4 x i1> %3,472 iXLen %4, iXLen 1)473 474 ret <vscale x 4 x i32> %a475}476 477define <vscale x 8 x i32> @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {478; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32:479; CHECK: # %bb.0: # %entry480; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma481; CHECK-NEXT: vnsrl.wv v20, v8, v16482; CHECK-NEXT: vmv.v.v v8, v20483; CHECK-NEXT: ret484entry:485 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32(486 <vscale x 8 x i32> poison,487 <vscale x 8 x i64> %0,488 <vscale x 8 x i32> %1,489 iXLen %2)490 491 ret <vscale x 8 x i32> %a492}493 494define <vscale x 8 x i32> @intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {495; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32:496; CHECK: # %bb.0: # %entry497; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu498; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t499; CHECK-NEXT: ret500entry:501 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32(502 <vscale x 8 x i32> %0,503 <vscale x 8 x i64> %1,504 <vscale x 8 x i32> %2,505 <vscale x 8 x i1> %3,506 iXLen %4, iXLen 1)507 508 ret <vscale x 8 x i32> %a509}510 511define <vscale x 1 x i8> @intrinsic_vnsrl_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %0, iXLen %1, iXLen %2) nounwind {512; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i8_nxv1i16:513; CHECK: # %bb.0: # %entry514; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma515; CHECK-NEXT: vnsrl.wx v8, v8, a0516; CHECK-NEXT: ret517entry:518 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(519 <vscale x 1 x i8> poison,520 <vscale x 1 x i16> %0,521 iXLen %1,522 iXLen %2)523 524 ret <vscale x 1 x i8> %a525}526 527define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {528; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i8_nxv1i16:529; CHECK: # %bb.0: # %entry530; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu531; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t532; CHECK-NEXT: ret533entry:534 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(535 <vscale x 1 x i8> %0,536 <vscale x 1 x i16> %1,537 iXLen %2,538 <vscale x 1 x i1> %3,539 iXLen %4, iXLen 1)540 541 ret <vscale x 1 x i8> %a542}543 544define <vscale x 2 x i8> @intrinsic_vnsrl_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %0, iXLen %1, iXLen %2) nounwind {545; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i8_nxv2i16:546; CHECK: # %bb.0: # %entry547; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma548; CHECK-NEXT: vnsrl.wx v8, v8, a0549; CHECK-NEXT: ret550entry:551 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(552 <vscale x 2 x i8> poison,553 <vscale x 2 x i16> %0,554 iXLen %1,555 iXLen %2)556 557 ret <vscale x 2 x i8> %a558}559 560define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {561; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i8_nxv2i16:562; CHECK: # %bb.0: # %entry563; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu564; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t565; CHECK-NEXT: ret566entry:567 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(568 <vscale x 2 x i8> %0,569 <vscale x 2 x i16> %1,570 iXLen %2,571 <vscale x 2 x i1> %3,572 iXLen %4, iXLen 1)573 574 ret <vscale x 2 x i8> %a575}576 577define <vscale x 4 x i8> @intrinsic_vnsrl_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, iXLen %1, iXLen %2) nounwind {578; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i8_nxv4i16:579; CHECK: # %bb.0: # %entry580; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma581; CHECK-NEXT: vnsrl.wx v8, v8, a0582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(585 <vscale x 4 x i8> poison,586 <vscale x 4 x i16> %0,587 iXLen %1,588 iXLen %2)589 590 ret <vscale x 4 x i8> %a591}592 593define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {594; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i8_nxv4i16:595; CHECK: # %bb.0: # %entry596; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu597; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t598; CHECK-NEXT: ret599entry:600 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(601 <vscale x 4 x i8> %0,602 <vscale x 4 x i16> %1,603 iXLen %2,604 <vscale x 4 x i1> %3,605 iXLen %4, iXLen 1)606 607 ret <vscale x 4 x i8> %a608}609 610define <vscale x 8 x i8> @intrinsic_vnsrl_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %0, iXLen %1, iXLen %2) nounwind {611; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i8_nxv8i16:612; CHECK: # %bb.0: # %entry613; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma614; CHECK-NEXT: vnsrl.wx v10, v8, a0615; CHECK-NEXT: vmv.v.v v8, v10616; CHECK-NEXT: ret617entry:618 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(619 <vscale x 8 x i8> poison,620 <vscale x 8 x i16> %0,621 iXLen %1,622 iXLen %2)623 624 ret <vscale x 8 x i8> %a625}626 627define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {628; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i8_nxv8i16:629; CHECK: # %bb.0: # %entry630; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu631; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t632; CHECK-NEXT: ret633entry:634 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(635 <vscale x 8 x i8> %0,636 <vscale x 8 x i16> %1,637 iXLen %2,638 <vscale x 8 x i1> %3,639 iXLen %4, iXLen 1)640 641 ret <vscale x 8 x i8> %a642}643 644define <vscale x 16 x i8> @intrinsic_vnsrl_vx_nxv16i8_nxv16i16(<vscale x 16 x i16> %0, iXLen %1, iXLen %2) nounwind {645; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i8_nxv16i16:646; CHECK: # %bb.0: # %entry647; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma648; CHECK-NEXT: vnsrl.wx v12, v8, a0649; CHECK-NEXT: vmv.v.v v8, v12650; CHECK-NEXT: ret651entry:652 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(653 <vscale x 16 x i8> poison,654 <vscale x 16 x i16> %0,655 iXLen %1,656 iXLen %2)657 658 ret <vscale x 16 x i8> %a659}660 661define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {662; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i8_nxv16i16:663; CHECK: # %bb.0: # %entry664; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu665; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t666; CHECK-NEXT: ret667entry:668 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(669 <vscale x 16 x i8> %0,670 <vscale x 16 x i16> %1,671 iXLen %2,672 <vscale x 16 x i1> %3,673 iXLen %4, iXLen 1)674 675 ret <vscale x 16 x i8> %a676}677 678define <vscale x 32 x i8> @intrinsic_vnsrl_vx_nxv32i8_nxv32i16(<vscale x 32 x i16> %0, iXLen %1, iXLen %2) nounwind {679; CHECK-LABEL: intrinsic_vnsrl_vx_nxv32i8_nxv32i16:680; CHECK: # %bb.0: # %entry681; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma682; CHECK-NEXT: vnsrl.wx v16, v8, a0683; CHECK-NEXT: vmv.v.v v8, v16684; CHECK-NEXT: ret685entry:686 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(687 <vscale x 32 x i8> poison,688 <vscale x 32 x i16> %0,689 iXLen %1,690 iXLen %2)691 692 ret <vscale x 32 x i8> %a693}694 695define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {696; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv32i8_nxv32i16:697; CHECK: # %bb.0: # %entry698; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu699; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t700; CHECK-NEXT: ret701entry:702 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(703 <vscale x 32 x i8> %0,704 <vscale x 32 x i16> %1,705 iXLen %2,706 <vscale x 32 x i1> %3,707 iXLen %4, iXLen 1)708 709 ret <vscale x 32 x i8> %a710}711 712define <vscale x 1 x i16> @intrinsic_vnsrl_vx_nxv1i16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1, iXLen %2) nounwind {713; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i16_nxv1i32:714; CHECK: # %bb.0: # %entry715; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma716; CHECK-NEXT: vnsrl.wx v8, v8, a0717; CHECK-NEXT: ret718entry:719 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(720 <vscale x 1 x i16> poison,721 <vscale x 1 x i32> %0,722 iXLen %1,723 iXLen %2)724 725 ret <vscale x 1 x i16> %a726}727 728define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {729; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i16_nxv1i32:730; CHECK: # %bb.0: # %entry731; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu732; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t733; CHECK-NEXT: ret734entry:735 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(736 <vscale x 1 x i16> %0,737 <vscale x 1 x i32> %1,738 iXLen %2,739 <vscale x 1 x i1> %3,740 iXLen %4, iXLen 1)741 742 ret <vscale x 1 x i16> %a743}744 745define <vscale x 2 x i16> @intrinsic_vnsrl_vx_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1, iXLen %2) nounwind {746; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i16_nxv2i32:747; CHECK: # %bb.0: # %entry748; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma749; CHECK-NEXT: vnsrl.wx v8, v8, a0750; CHECK-NEXT: ret751entry:752 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(753 <vscale x 2 x i16> poison,754 <vscale x 2 x i32> %0,755 iXLen %1,756 iXLen %2)757 758 ret <vscale x 2 x i16> %a759}760 761define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {762; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i16_nxv2i32:763; CHECK: # %bb.0: # %entry764; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu765; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t766; CHECK-NEXT: ret767entry:768 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(769 <vscale x 2 x i16> %0,770 <vscale x 2 x i32> %1,771 iXLen %2,772 <vscale x 2 x i1> %3,773 iXLen %4, iXLen 1)774 775 ret <vscale x 2 x i16> %a776}777 778define <vscale x 4 x i16> @intrinsic_vnsrl_vx_nxv4i16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1, iXLen %2) nounwind {779; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i16_nxv4i32:780; CHECK: # %bb.0: # %entry781; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma782; CHECK-NEXT: vnsrl.wx v10, v8, a0783; CHECK-NEXT: vmv.v.v v8, v10784; CHECK-NEXT: ret785entry:786 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(787 <vscale x 4 x i16> poison,788 <vscale x 4 x i32> %0,789 iXLen %1,790 iXLen %2)791 792 ret <vscale x 4 x i16> %a793}794 795define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {796; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i16_nxv4i32:797; CHECK: # %bb.0: # %entry798; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu799; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t800; CHECK-NEXT: ret801entry:802 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(803 <vscale x 4 x i16> %0,804 <vscale x 4 x i32> %1,805 iXLen %2,806 <vscale x 4 x i1> %3,807 iXLen %4, iXLen 1)808 809 ret <vscale x 4 x i16> %a810}811 812define <vscale x 8 x i16> @intrinsic_vnsrl_vx_nxv8i16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1, iXLen %2) nounwind {813; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i16_nxv8i32:814; CHECK: # %bb.0: # %entry815; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma816; CHECK-NEXT: vnsrl.wx v12, v8, a0817; CHECK-NEXT: vmv.v.v v8, v12818; CHECK-NEXT: ret819entry:820 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(821 <vscale x 8 x i16> poison,822 <vscale x 8 x i32> %0,823 iXLen %1,824 iXLen %2)825 826 ret <vscale x 8 x i16> %a827}828 829define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {830; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i16_nxv8i32:831; CHECK: # %bb.0: # %entry832; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu833; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t834; CHECK-NEXT: ret835entry:836 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(837 <vscale x 8 x i16> %0,838 <vscale x 8 x i32> %1,839 iXLen %2,840 <vscale x 8 x i1> %3,841 iXLen %4, iXLen 1)842 843 ret <vscale x 8 x i16> %a844}845 846define <vscale x 16 x i16> @intrinsic_vnsrl_vx_nxv16i16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1, iXLen %2) nounwind {847; CHECK-LABEL: intrinsic_vnsrl_vx_nxv16i16_nxv16i32:848; CHECK: # %bb.0: # %entry849; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma850; CHECK-NEXT: vnsrl.wx v16, v8, a0851; CHECK-NEXT: vmv.v.v v8, v16852; CHECK-NEXT: ret853entry:854 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(855 <vscale x 16 x i16> poison,856 <vscale x 16 x i32> %0,857 iXLen %1,858 iXLen %2)859 860 ret <vscale x 16 x i16> %a861}862 863define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {864; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv16i16_nxv16i32:865; CHECK: # %bb.0: # %entry866; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu867; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t868; CHECK-NEXT: ret869entry:870 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(871 <vscale x 16 x i16> %0,872 <vscale x 16 x i32> %1,873 iXLen %2,874 <vscale x 16 x i1> %3,875 iXLen %4, iXLen 1)876 877 ret <vscale x 16 x i16> %a878}879 880define <vscale x 1 x i32> @intrinsic_vnsrl_vx_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1, iXLen %2) nounwind {881; CHECK-LABEL: intrinsic_vnsrl_vx_nxv1i32_nxv1i64:882; CHECK: # %bb.0: # %entry883; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma884; CHECK-NEXT: vnsrl.wx v8, v8, a0885; CHECK-NEXT: ret886entry:887 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(888 <vscale x 1 x i32> poison,889 <vscale x 1 x i64> %0,890 iXLen %1,891 iXLen %2)892 893 ret <vscale x 1 x i32> %a894}895 896define <vscale x 1 x i32> @intrinsic_vnsrl_mask_vx_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {897; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv1i32_nxv1i64:898; CHECK: # %bb.0: # %entry899; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu900; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t901; CHECK-NEXT: ret902entry:903 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64(904 <vscale x 1 x i32> %0,905 <vscale x 1 x i64> %1,906 iXLen %2,907 <vscale x 1 x i1> %3,908 iXLen %4, iXLen 1)909 910 ret <vscale x 1 x i32> %a911}912 913define <vscale x 2 x i32> @intrinsic_vnsrl_vx_nxv2i32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1, iXLen %2) nounwind {914; CHECK-LABEL: intrinsic_vnsrl_vx_nxv2i32_nxv2i64:915; CHECK: # %bb.0: # %entry916; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma917; CHECK-NEXT: vnsrl.wx v10, v8, a0918; CHECK-NEXT: vmv.v.v v8, v10919; CHECK-NEXT: ret920entry:921 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(922 <vscale x 2 x i32> poison,923 <vscale x 2 x i64> %0,924 iXLen %1,925 iXLen %2)926 927 ret <vscale x 2 x i32> %a928}929 930define <vscale x 2 x i32> @intrinsic_vnsrl_mask_vx_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {931; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv2i32_nxv2i64:932; CHECK: # %bb.0: # %entry933; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu934; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t935; CHECK-NEXT: ret936entry:937 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64(938 <vscale x 2 x i32> %0,939 <vscale x 2 x i64> %1,940 iXLen %2,941 <vscale x 2 x i1> %3,942 iXLen %4, iXLen 1)943 944 ret <vscale x 2 x i32> %a945}946 947define <vscale x 4 x i32> @intrinsic_vnsrl_vx_nxv4i32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1, iXLen %2) nounwind {948; CHECK-LABEL: intrinsic_vnsrl_vx_nxv4i32_nxv4i64:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma951; CHECK-NEXT: vnsrl.wx v12, v8, a0952; CHECK-NEXT: vmv.v.v v8, v12953; CHECK-NEXT: ret954entry:955 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(956 <vscale x 4 x i32> poison,957 <vscale x 4 x i64> %0,958 iXLen %1,959 iXLen %2)960 961 ret <vscale x 4 x i32> %a962}963 964define <vscale x 4 x i32> @intrinsic_vnsrl_mask_vx_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {965; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv4i32_nxv4i64:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu968; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t969; CHECK-NEXT: ret970entry:971 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64(972 <vscale x 4 x i32> %0,973 <vscale x 4 x i64> %1,974 iXLen %2,975 <vscale x 4 x i1> %3,976 iXLen %4, iXLen 1)977 978 ret <vscale x 4 x i32> %a979}980 981define <vscale x 8 x i32> @intrinsic_vnsrl_vx_nxv8i32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1, iXLen %2) nounwind {982; CHECK-LABEL: intrinsic_vnsrl_vx_nxv8i32_nxv8i64:983; CHECK: # %bb.0: # %entry984; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma985; CHECK-NEXT: vnsrl.wx v16, v8, a0986; CHECK-NEXT: vmv.v.v v8, v16987; CHECK-NEXT: ret988entry:989 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(990 <vscale x 8 x i32> poison,991 <vscale x 8 x i64> %0,992 iXLen %1,993 iXLen %2)994 995 ret <vscale x 8 x i32> %a996}997 998define <vscale x 8 x i32> @intrinsic_vnsrl_mask_vx_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {999; CHECK-LABEL: intrinsic_vnsrl_mask_vx_nxv8i32_nxv8i64:1000; CHECK: # %bb.0: # %entry1001; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1002; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t1003; CHECK-NEXT: ret1004entry:1005 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64(1006 <vscale x 8 x i32> %0,1007 <vscale x 8 x i64> %1,1008 iXLen %2,1009 <vscale x 8 x i1> %3,1010 iXLen %4, iXLen 1)1011 1012 ret <vscale x 8 x i32> %a1013}1014 1015define <vscale x 1 x i8> @intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16> %0, iXLen %1) nounwind {1016; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i8_nxv1i16_i8:1017; CHECK: # %bb.0: # %entry1018; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1019; CHECK-NEXT: vnsrl.wi v8, v8, 91020; CHECK-NEXT: ret1021entry:1022 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16(1023 <vscale x 1 x i8> poison,1024 <vscale x 1 x i16> %0,1025 iXLen 9,1026 iXLen %1)1027 1028 ret <vscale x 1 x i8> %a1029}1030 1031define <vscale x 1 x i8> @intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1032; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i8_nxv1i16_i8:1033; CHECK: # %bb.0: # %entry1034; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1035; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1036; CHECK-NEXT: ret1037entry:1038 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16(1039 <vscale x 1 x i8> %0,1040 <vscale x 1 x i16> %1,1041 iXLen 9,1042 <vscale x 1 x i1> %2,1043 iXLen %3, iXLen 1)1044 1045 ret <vscale x 1 x i8> %a1046}1047 1048define <vscale x 2 x i8> @intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16> %0, iXLen %1) nounwind {1049; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i8_nxv2i16_i8:1050; CHECK: # %bb.0: # %entry1051; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1052; CHECK-NEXT: vnsrl.wi v8, v8, 91053; CHECK-NEXT: ret1054entry:1055 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.nxv2i8.nxv2i16(1056 <vscale x 2 x i8> poison,1057 <vscale x 2 x i16> %0,1058 iXLen 9,1059 iXLen %1)1060 1061 ret <vscale x 2 x i8> %a1062}1063 1064define <vscale x 2 x i8> @intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1065; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i8_nxv2i16_i8:1066; CHECK: # %bb.0: # %entry1067; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1068; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1069; CHECK-NEXT: ret1070entry:1071 %a = call <vscale x 2 x i8> @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16(1072 <vscale x 2 x i8> %0,1073 <vscale x 2 x i16> %1,1074 iXLen 9,1075 <vscale x 2 x i1> %2,1076 iXLen %3, iXLen 1)1077 1078 ret <vscale x 2 x i8> %a1079}1080 1081define <vscale x 4 x i8> @intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16> %0, iXLen %1) nounwind {1082; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i8_nxv4i16_i8:1083; CHECK: # %bb.0: # %entry1084; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1085; CHECK-NEXT: vnsrl.wi v8, v8, 91086; CHECK-NEXT: ret1087entry:1088 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.nxv4i8.nxv4i16(1089 <vscale x 4 x i8> poison,1090 <vscale x 4 x i16> %0,1091 iXLen 9,1092 iXLen %1)1093 1094 ret <vscale x 4 x i8> %a1095}1096 1097define <vscale x 4 x i8> @intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1098; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i8_nxv4i16_i8:1099; CHECK: # %bb.0: # %entry1100; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1101; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1102; CHECK-NEXT: ret1103entry:1104 %a = call <vscale x 4 x i8> @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16(1105 <vscale x 4 x i8> %0,1106 <vscale x 4 x i16> %1,1107 iXLen 9,1108 <vscale x 4 x i1> %2,1109 iXLen %3, iXLen 1)1110 1111 ret <vscale x 4 x i8> %a1112}1113 1114define <vscale x 8 x i8> @intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16> %0, iXLen %1) nounwind {1115; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i8_nxv8i16_i8:1116; CHECK: # %bb.0: # %entry1117; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1118; CHECK-NEXT: vnsrl.wi v10, v8, 91119; CHECK-NEXT: vmv.v.v v8, v101120; CHECK-NEXT: ret1121entry:1122 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.nxv8i8.nxv8i16(1123 <vscale x 8 x i8> poison,1124 <vscale x 8 x i16> %0,1125 iXLen 9,1126 iXLen %1)1127 1128 ret <vscale x 8 x i8> %a1129}1130 1131define <vscale x 8 x i8> @intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1132; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i8_nxv8i16_i8:1133; CHECK: # %bb.0: # %entry1134; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1135; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t1136; CHECK-NEXT: ret1137entry:1138 %a = call <vscale x 8 x i8> @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16(1139 <vscale x 8 x i8> %0,1140 <vscale x 8 x i16> %1,1141 iXLen 9,1142 <vscale x 8 x i1> %2,1143 iXLen %3, iXLen 1)1144 1145 ret <vscale x 8 x i8> %a1146}1147 1148define <vscale x 16 x i8> @intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i16> %0, iXLen %1) nounwind {1149; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i8_nxv16i16_i8:1150; CHECK: # %bb.0: # %entry1151; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1152; CHECK-NEXT: vnsrl.wi v12, v8, 91153; CHECK-NEXT: vmv.v.v v8, v121154; CHECK-NEXT: ret1155entry:1156 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.nxv16i8.nxv16i16(1157 <vscale x 16 x i8> poison,1158 <vscale x 16 x i16> %0,1159 iXLen 9,1160 iXLen %1)1161 1162 ret <vscale x 16 x i8> %a1163}1164 1165define <vscale x 16 x i8> @intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1166; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i8_nxv16i16_i8:1167; CHECK: # %bb.0: # %entry1168; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1169; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t1170; CHECK-NEXT: ret1171entry:1172 %a = call <vscale x 16 x i8> @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16(1173 <vscale x 16 x i8> %0,1174 <vscale x 16 x i16> %1,1175 iXLen 9,1176 <vscale x 16 x i1> %2,1177 iXLen %3, iXLen 1)1178 1179 ret <vscale x 16 x i8> %a1180}1181 1182define <vscale x 32 x i8> @intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i16> %0, iXLen %1) nounwind {1183; CHECK-LABEL: intrinsic_vnsrl_vi_nxv32i8_nxv32i16_i8:1184; CHECK: # %bb.0: # %entry1185; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1186; CHECK-NEXT: vnsrl.wi v16, v8, 91187; CHECK-NEXT: vmv.v.v v8, v161188; CHECK-NEXT: ret1189entry:1190 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.nxv32i8.nxv32i16(1191 <vscale x 32 x i8> poison,1192 <vscale x 32 x i16> %0,1193 iXLen 9,1194 iXLen %1)1195 1196 ret <vscale x 32 x i8> %a1197}1198 1199define <vscale x 32 x i8> @intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1200; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv32i8_nxv32i16_i8:1201; CHECK: # %bb.0: # %entry1202; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1203; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t1204; CHECK-NEXT: ret1205entry:1206 %a = call <vscale x 32 x i8> @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16(1207 <vscale x 32 x i8> %0,1208 <vscale x 32 x i16> %1,1209 iXLen 9,1210 <vscale x 32 x i1> %2,1211 iXLen %3, iXLen 1)1212 1213 ret <vscale x 32 x i8> %a1214}1215 1216define <vscale x 1 x i16> @intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i32> %0, iXLen %1) nounwind {1217; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i16_nxv1i32_i16:1218; CHECK: # %bb.0: # %entry1219; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1220; CHECK-NEXT: vnsrl.wi v8, v8, 91221; CHECK-NEXT: ret1222entry:1223 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.nxv1i16.nxv1i32(1224 <vscale x 1 x i16> poison,1225 <vscale x 1 x i32> %0,1226 iXLen 9,1227 iXLen %1)1228 1229 ret <vscale x 1 x i16> %a1230}1231 1232define <vscale x 1 x i16> @intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1233; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i16_nxv1i32_i16:1234; CHECK: # %bb.0: # %entry1235; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1236; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1237; CHECK-NEXT: ret1238entry:1239 %a = call <vscale x 1 x i16> @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32(1240 <vscale x 1 x i16> %0,1241 <vscale x 1 x i32> %1,1242 iXLen 9,1243 <vscale x 1 x i1> %2,1244 iXLen %3, iXLen 1)1245 1246 ret <vscale x 1 x i16> %a1247}1248 1249define <vscale x 2 x i16> @intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i32> %0, iXLen %1) nounwind {1250; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i16_nxv2i32_i16:1251; CHECK: # %bb.0: # %entry1252; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1253; CHECK-NEXT: vnsrl.wi v8, v8, 91254; CHECK-NEXT: ret1255entry:1256 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32(1257 <vscale x 2 x i16> poison,1258 <vscale x 2 x i32> %0,1259 iXLen 9,1260 iXLen %1)1261 1262 ret <vscale x 2 x i16> %a1263}1264 1265define <vscale x 2 x i16> @intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1266; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i16_nxv2i32_i16:1267; CHECK: # %bb.0: # %entry1268; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1269; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1270; CHECK-NEXT: ret1271entry:1272 %a = call <vscale x 2 x i16> @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32(1273 <vscale x 2 x i16> %0,1274 <vscale x 2 x i32> %1,1275 iXLen 9,1276 <vscale x 2 x i1> %2,1277 iXLen %3, iXLen 1)1278 1279 ret <vscale x 2 x i16> %a1280}1281 1282define <vscale x 4 x i16> @intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i32> %0, iXLen %1) nounwind {1283; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i16_nxv4i32_i16:1284; CHECK: # %bb.0: # %entry1285; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1286; CHECK-NEXT: vnsrl.wi v10, v8, 91287; CHECK-NEXT: vmv.v.v v8, v101288; CHECK-NEXT: ret1289entry:1290 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.nxv4i16.nxv4i32(1291 <vscale x 4 x i16> poison,1292 <vscale x 4 x i32> %0,1293 iXLen 9,1294 iXLen %1)1295 1296 ret <vscale x 4 x i16> %a1297}1298 1299define <vscale x 4 x i16> @intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1300; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i16_nxv4i32_i16:1301; CHECK: # %bb.0: # %entry1302; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1303; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t1304; CHECK-NEXT: ret1305entry:1306 %a = call <vscale x 4 x i16> @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32(1307 <vscale x 4 x i16> %0,1308 <vscale x 4 x i32> %1,1309 iXLen 9,1310 <vscale x 4 x i1> %2,1311 iXLen %3, iXLen 1)1312 1313 ret <vscale x 4 x i16> %a1314}1315 1316define <vscale x 8 x i16> @intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i32> %0, iXLen %1) nounwind {1317; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i16_nxv8i32_i16:1318; CHECK: # %bb.0: # %entry1319; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1320; CHECK-NEXT: vnsrl.wi v12, v8, 91321; CHECK-NEXT: vmv.v.v v8, v121322; CHECK-NEXT: ret1323entry:1324 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.nxv8i16.nxv8i32(1325 <vscale x 8 x i16> poison,1326 <vscale x 8 x i32> %0,1327 iXLen 9,1328 iXLen %1)1329 1330 ret <vscale x 8 x i16> %a1331}1332 1333define <vscale x 8 x i16> @intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1334; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i16_nxv8i32_i16:1335; CHECK: # %bb.0: # %entry1336; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1337; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t1338; CHECK-NEXT: ret1339entry:1340 %a = call <vscale x 8 x i16> @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32(1341 <vscale x 8 x i16> %0,1342 <vscale x 8 x i32> %1,1343 iXLen 9,1344 <vscale x 8 x i1> %2,1345 iXLen %3, iXLen 1)1346 1347 ret <vscale x 8 x i16> %a1348}1349 1350define <vscale x 16 x i16> @intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i32> %0, iXLen %1) nounwind {1351; CHECK-LABEL: intrinsic_vnsrl_vi_nxv16i16_nxv16i32_i16:1352; CHECK: # %bb.0: # %entry1353; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1354; CHECK-NEXT: vnsrl.wi v16, v8, 91355; CHECK-NEXT: vmv.v.v v8, v161356; CHECK-NEXT: ret1357entry:1358 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.nxv16i16.nxv16i32(1359 <vscale x 16 x i16> poison,1360 <vscale x 16 x i32> %0,1361 iXLen 9,1362 iXLen %1)1363 1364 ret <vscale x 16 x i16> %a1365}1366 1367define <vscale x 16 x i16> @intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16(<vscale x 16 x i16> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1368; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv16i16_nxv16i32_i16:1369; CHECK: # %bb.0: # %entry1370; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1371; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t1372; CHECK-NEXT: ret1373entry:1374 %a = call <vscale x 16 x i16> @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32(1375 <vscale x 16 x i16> %0,1376 <vscale x 16 x i32> %1,1377 iXLen 9,1378 <vscale x 16 x i1> %2,1379 iXLen %3, iXLen 1)1380 1381 ret <vscale x 16 x i16> %a1382}1383 1384define <vscale x 1 x i32> @intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i64> %0, iXLen %1) nounwind {1385; CHECK-LABEL: intrinsic_vnsrl_vi_nxv1i32_nxv1i64_i32:1386; CHECK: # %bb.0: # %entry1387; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1388; CHECK-NEXT: vnsrl.wi v8, v8, 91389; CHECK-NEXT: ret1390entry:1391 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.nxv1i32.nxv1i64(1392 <vscale x 1 x i32> poison,1393 <vscale x 1 x i64> %0,1394 iXLen 9,1395 iXLen %1)1396 1397 ret <vscale x 1 x i32> %a1398}1399 1400define <vscale x 1 x i32> @intrinsic_vnsrl_mask_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1401; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv1i32_nxv1i64_i32:1402; CHECK: # %bb.0: # %entry1403; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1404; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t1405; CHECK-NEXT: ret1406entry:1407 %a = call <vscale x 1 x i32> @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64(1408 <vscale x 1 x i32> %0,1409 <vscale x 1 x i64> %1,1410 iXLen 9,1411 <vscale x 1 x i1> %2,1412 iXLen %3, iXLen 1)1413 1414 ret <vscale x 1 x i32> %a1415}1416 1417define <vscale x 2 x i32> @intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i64> %0, iXLen %1) nounwind {1418; CHECK-LABEL: intrinsic_vnsrl_vi_nxv2i32_nxv2i64_i32:1419; CHECK: # %bb.0: # %entry1420; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1421; CHECK-NEXT: vnsrl.wi v10, v8, 91422; CHECK-NEXT: vmv.v.v v8, v101423; CHECK-NEXT: ret1424entry:1425 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.nxv2i32.nxv2i64(1426 <vscale x 2 x i32> poison,1427 <vscale x 2 x i64> %0,1428 iXLen 9,1429 iXLen %1)1430 1431 ret <vscale x 2 x i32> %a1432}1433 1434define <vscale x 2 x i32> @intrinsic_vnsrl_mask_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1435; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv2i32_nxv2i64_i32:1436; CHECK: # %bb.0: # %entry1437; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1438; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t1439; CHECK-NEXT: ret1440entry:1441 %a = call <vscale x 2 x i32> @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64(1442 <vscale x 2 x i32> %0,1443 <vscale x 2 x i64> %1,1444 iXLen 9,1445 <vscale x 2 x i1> %2,1446 iXLen %3, iXLen 1)1447 1448 ret <vscale x 2 x i32> %a1449}1450 1451define <vscale x 4 x i32> @intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i64> %0, iXLen %1) nounwind {1452; CHECK-LABEL: intrinsic_vnsrl_vi_nxv4i32_nxv4i64_i32:1453; CHECK: # %bb.0: # %entry1454; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1455; CHECK-NEXT: vnsrl.wi v12, v8, 91456; CHECK-NEXT: vmv.v.v v8, v121457; CHECK-NEXT: ret1458entry:1459 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.nxv4i32.nxv4i64(1460 <vscale x 4 x i32> poison,1461 <vscale x 4 x i64> %0,1462 iXLen 9,1463 iXLen %1)1464 1465 ret <vscale x 4 x i32> %a1466}1467 1468define <vscale x 4 x i32> @intrinsic_vnsrl_mask_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1469; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv4i32_nxv4i64_i32:1470; CHECK: # %bb.0: # %entry1471; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1472; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t1473; CHECK-NEXT: ret1474entry:1475 %a = call <vscale x 4 x i32> @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64(1476 <vscale x 4 x i32> %0,1477 <vscale x 4 x i64> %1,1478 iXLen 9,1479 <vscale x 4 x i1> %2,1480 iXLen %3, iXLen 1)1481 1482 ret <vscale x 4 x i32> %a1483}1484 1485define <vscale x 8 x i32> @intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i64> %0, iXLen %1) nounwind {1486; CHECK-LABEL: intrinsic_vnsrl_vi_nxv8i32_nxv8i64_i32:1487; CHECK: # %bb.0: # %entry1488; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1489; CHECK-NEXT: vnsrl.wi v16, v8, 91490; CHECK-NEXT: vmv.v.v v8, v161491; CHECK-NEXT: ret1492entry:1493 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.nxv8i32.nxv8i64(1494 <vscale x 8 x i32> poison,1495 <vscale x 8 x i64> %0,1496 iXLen 9,1497 iXLen %1)1498 1499 ret <vscale x 8 x i32> %a1500}1501 1502define <vscale x 8 x i32> @intrinsic_vnsrl_mask_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1503; CHECK-LABEL: intrinsic_vnsrl_mask_vi_nxv8i32_nxv8i64_i32:1504; CHECK: # %bb.0: # %entry1505; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1506; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t1507; CHECK-NEXT: ret1508entry:1509 %a = call <vscale x 8 x i32> @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64(1510 <vscale x 8 x i32> %0,1511 <vscale x 8 x i64> %1,1512 iXLen 9,1513 <vscale x 8 x i1> %2,1514 iXLen %3, iXLen 1)1515 1516 ret <vscale x 8 x i32> %a1517}1518