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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @vor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {6; CHECK-LABEL: vor_vx_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma9; CHECK-NEXT: vor.vx v8, v8, a010; CHECK-NEXT: ret11 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 012 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer13 %vc = or <vscale x 1 x i8> %va, %splat14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {18; CHECK-LABEL: vor_vx_nxv1i8_0:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma21; CHECK-NEXT: vor.vi v8, v8, -1222; CHECK-NEXT: ret23 %vc = or <vscale x 1 x i8> %va, splat (i8 -12)24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 1 x i8> @vor_vx_nxv1i8_1(<vscale x 1 x i8> %va) {28; CHECK-LABEL: vor_vx_nxv1i8_1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vor.vi v8, v8, 1532; CHECK-NEXT: ret33 %vc = or <vscale x 1 x i8> %va, splat (i8 15)34 ret <vscale x 1 x i8> %vc35}36 37define <vscale x 1 x i8> @vor_vx_nxv1i8_2(<vscale x 1 x i8> %va) {38; CHECK-LABEL: vor_vx_nxv1i8_2:39; CHECK: # %bb.0:40; CHECK-NEXT: li a0, 1641; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma42; CHECK-NEXT: vor.vx v8, v8, a043; CHECK-NEXT: ret44 %vc = or <vscale x 1 x i8> %va, splat (i8 16)45 ret <vscale x 1 x i8> %vc46}47 48define <vscale x 2 x i8> @vor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {49; CHECK-LABEL: vor_vx_nxv2i8:50; CHECK: # %bb.0:51; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma52; CHECK-NEXT: vor.vx v8, v8, a053; CHECK-NEXT: ret54 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 055 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer56 %vc = or <vscale x 2 x i8> %va, %splat57 ret <vscale x 2 x i8> %vc58}59 60define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {61; CHECK-LABEL: vor_vx_nxv2i8_0:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma64; CHECK-NEXT: vor.vi v8, v8, -1265; CHECK-NEXT: ret66 %vc = or <vscale x 2 x i8> %va, splat (i8 -12)67 ret <vscale x 2 x i8> %vc68}69 70define <vscale x 2 x i8> @vor_vx_nxv2i8_1(<vscale x 2 x i8> %va) {71; CHECK-LABEL: vor_vx_nxv2i8_1:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma74; CHECK-NEXT: vor.vi v8, v8, 1575; CHECK-NEXT: ret76 %vc = or <vscale x 2 x i8> %va, splat (i8 15)77 ret <vscale x 2 x i8> %vc78}79 80define <vscale x 2 x i8> @vor_vx_nxv2i8_2(<vscale x 2 x i8> %va) {81; CHECK-LABEL: vor_vx_nxv2i8_2:82; CHECK: # %bb.0:83; CHECK-NEXT: li a0, 1684; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma85; CHECK-NEXT: vor.vx v8, v8, a086; CHECK-NEXT: ret87 %vc = or <vscale x 2 x i8> %va, splat (i8 16)88 ret <vscale x 2 x i8> %vc89}90 91define <vscale x 4 x i8> @vor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {92; CHECK-LABEL: vor_vx_nxv4i8:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma95; CHECK-NEXT: vor.vx v8, v8, a096; CHECK-NEXT: ret97 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 098 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer99 %vc = or <vscale x 4 x i8> %va, %splat100 ret <vscale x 4 x i8> %vc101}102 103define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {104; CHECK-LABEL: vor_vx_nxv4i8_0:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma107; CHECK-NEXT: vor.vi v8, v8, -12108; CHECK-NEXT: ret109 %vc = or <vscale x 4 x i8> %va, splat (i8 -12)110 ret <vscale x 4 x i8> %vc111}112 113define <vscale x 4 x i8> @vor_vx_nxv4i8_1(<vscale x 4 x i8> %va) {114; CHECK-LABEL: vor_vx_nxv4i8_1:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma117; CHECK-NEXT: vor.vi v8, v8, 15118; CHECK-NEXT: ret119 %vc = or <vscale x 4 x i8> %va, splat (i8 15)120 ret <vscale x 4 x i8> %vc121}122 123define <vscale x 4 x i8> @vor_vx_nxv4i8_2(<vscale x 4 x i8> %va) {124; CHECK-LABEL: vor_vx_nxv4i8_2:125; CHECK: # %bb.0:126; CHECK-NEXT: li a0, 16127; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma128; CHECK-NEXT: vor.vx v8, v8, a0129; CHECK-NEXT: ret130 %vc = or <vscale x 4 x i8> %va, splat (i8 16)131 ret <vscale x 4 x i8> %vc132}133 134define <vscale x 8 x i8> @vor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {135; CHECK-LABEL: vor_vx_nxv8i8:136; CHECK: # %bb.0:137; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma138; CHECK-NEXT: vor.vx v8, v8, a0139; CHECK-NEXT: ret140 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0141 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer142 %vc = or <vscale x 8 x i8> %va, %splat143 ret <vscale x 8 x i8> %vc144}145 146define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {147; CHECK-LABEL: vor_vx_nxv8i8_0:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma150; CHECK-NEXT: vor.vi v8, v8, -12151; CHECK-NEXT: ret152 %vc = or <vscale x 8 x i8> %va, splat (i8 -12)153 ret <vscale x 8 x i8> %vc154}155 156define <vscale x 8 x i8> @vor_vx_nxv8i8_1(<vscale x 8 x i8> %va) {157; CHECK-LABEL: vor_vx_nxv8i8_1:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma160; CHECK-NEXT: vor.vi v8, v8, 15161; CHECK-NEXT: ret162 %vc = or <vscale x 8 x i8> %va, splat (i8 15)163 ret <vscale x 8 x i8> %vc164}165 166define <vscale x 8 x i8> @vor_vx_nxv8i8_2(<vscale x 8 x i8> %va) {167; CHECK-LABEL: vor_vx_nxv8i8_2:168; CHECK: # %bb.0:169; CHECK-NEXT: li a0, 16170; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma171; CHECK-NEXT: vor.vx v8, v8, a0172; CHECK-NEXT: ret173 %vc = or <vscale x 8 x i8> %va, splat (i8 16)174 ret <vscale x 8 x i8> %vc175}176 177define <vscale x 16 x i8> @vor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {178; CHECK-LABEL: vor_vx_nxv16i8:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma181; CHECK-NEXT: vor.vx v8, v8, a0182; CHECK-NEXT: ret183 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0184 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer185 %vc = or <vscale x 16 x i8> %va, %splat186 ret <vscale x 16 x i8> %vc187}188 189define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {190; CHECK-LABEL: vor_vx_nxv16i8_0:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma193; CHECK-NEXT: vor.vi v8, v8, -12194; CHECK-NEXT: ret195 %vc = or <vscale x 16 x i8> %va, splat (i8 -12)196 ret <vscale x 16 x i8> %vc197}198 199define <vscale x 16 x i8> @vor_vx_nxv16i8_1(<vscale x 16 x i8> %va) {200; CHECK-LABEL: vor_vx_nxv16i8_1:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma203; CHECK-NEXT: vor.vi v8, v8, 15204; CHECK-NEXT: ret205 %vc = or <vscale x 16 x i8> %va, splat (i8 15)206 ret <vscale x 16 x i8> %vc207}208 209define <vscale x 16 x i8> @vor_vx_nxv16i8_2(<vscale x 16 x i8> %va) {210; CHECK-LABEL: vor_vx_nxv16i8_2:211; CHECK: # %bb.0:212; CHECK-NEXT: li a0, 16213; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma214; CHECK-NEXT: vor.vx v8, v8, a0215; CHECK-NEXT: ret216 %vc = or <vscale x 16 x i8> %va, splat (i8 16)217 ret <vscale x 16 x i8> %vc218}219 220define <vscale x 32 x i8> @vor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {221; CHECK-LABEL: vor_vx_nxv32i8:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma224; CHECK-NEXT: vor.vx v8, v8, a0225; CHECK-NEXT: ret226 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0227 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer228 %vc = or <vscale x 32 x i8> %va, %splat229 ret <vscale x 32 x i8> %vc230}231 232define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {233; CHECK-LABEL: vor_vx_nxv32i8_0:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma236; CHECK-NEXT: vor.vi v8, v8, -12237; CHECK-NEXT: ret238 %vc = or <vscale x 32 x i8> %va, splat (i8 -12)239 ret <vscale x 32 x i8> %vc240}241 242define <vscale x 32 x i8> @vor_vx_nxv32i8_1(<vscale x 32 x i8> %va) {243; CHECK-LABEL: vor_vx_nxv32i8_1:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma246; CHECK-NEXT: vor.vi v8, v8, 15247; CHECK-NEXT: ret248 %vc = or <vscale x 32 x i8> %va, splat (i8 15)249 ret <vscale x 32 x i8> %vc250}251 252define <vscale x 32 x i8> @vor_vx_nxv32i8_2(<vscale x 32 x i8> %va) {253; CHECK-LABEL: vor_vx_nxv32i8_2:254; CHECK: # %bb.0:255; CHECK-NEXT: li a0, 16256; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma257; CHECK-NEXT: vor.vx v8, v8, a0258; CHECK-NEXT: ret259 %vc = or <vscale x 32 x i8> %va, splat (i8 16)260 ret <vscale x 32 x i8> %vc261}262 263define <vscale x 64 x i8> @vor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {264; CHECK-LABEL: vor_vx_nxv64i8:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma267; CHECK-NEXT: vor.vx v8, v8, a0268; CHECK-NEXT: ret269 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0270 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer271 %vc = or <vscale x 64 x i8> %va, %splat272 ret <vscale x 64 x i8> %vc273}274 275define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {276; CHECK-LABEL: vor_vx_nxv64i8_0:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma279; CHECK-NEXT: vor.vi v8, v8, -12280; CHECK-NEXT: ret281 %vc = or <vscale x 64 x i8> %va, splat (i8 -12)282 ret <vscale x 64 x i8> %vc283}284 285define <vscale x 64 x i8> @vor_vx_nxv64i8_1(<vscale x 64 x i8> %va) {286; CHECK-LABEL: vor_vx_nxv64i8_1:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma289; CHECK-NEXT: vor.vi v8, v8, 15290; CHECK-NEXT: ret291 %vc = or <vscale x 64 x i8> %va, splat (i8 15)292 ret <vscale x 64 x i8> %vc293}294 295define <vscale x 64 x i8> @vor_vx_nxv64i8_2(<vscale x 64 x i8> %va) {296; CHECK-LABEL: vor_vx_nxv64i8_2:297; CHECK: # %bb.0:298; CHECK-NEXT: li a0, 16299; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma300; CHECK-NEXT: vor.vx v8, v8, a0301; CHECK-NEXT: ret302 %vc = or <vscale x 64 x i8> %va, splat (i8 16)303 ret <vscale x 64 x i8> %vc304}305 306define <vscale x 1 x i16> @vor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {307; CHECK-LABEL: vor_vx_nxv1i16:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma310; CHECK-NEXT: vor.vx v8, v8, a0311; CHECK-NEXT: ret312 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0313 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer314 %vc = or <vscale x 1 x i16> %va, %splat315 ret <vscale x 1 x i16> %vc316}317 318define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {319; CHECK-LABEL: vor_vx_nxv1i16_0:320; CHECK: # %bb.0:321; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma322; CHECK-NEXT: vor.vi v8, v8, -12323; CHECK-NEXT: ret324 %vc = or <vscale x 1 x i16> %va, splat (i16 -12)325 ret <vscale x 1 x i16> %vc326}327 328define <vscale x 1 x i16> @vor_vx_nxv1i16_1(<vscale x 1 x i16> %va) {329; CHECK-LABEL: vor_vx_nxv1i16_1:330; CHECK: # %bb.0:331; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma332; CHECK-NEXT: vor.vi v8, v8, 15333; CHECK-NEXT: ret334 %vc = or <vscale x 1 x i16> %va, splat (i16 15)335 ret <vscale x 1 x i16> %vc336}337 338define <vscale x 1 x i16> @vor_vx_nxv1i16_2(<vscale x 1 x i16> %va) {339; CHECK-LABEL: vor_vx_nxv1i16_2:340; CHECK: # %bb.0:341; CHECK-NEXT: li a0, 16342; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma343; CHECK-NEXT: vor.vx v8, v8, a0344; CHECK-NEXT: ret345 %vc = or <vscale x 1 x i16> %va, splat (i16 16)346 ret <vscale x 1 x i16> %vc347}348 349define <vscale x 2 x i16> @vor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {350; CHECK-LABEL: vor_vx_nxv2i16:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma353; CHECK-NEXT: vor.vx v8, v8, a0354; CHECK-NEXT: ret355 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0356 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer357 %vc = or <vscale x 2 x i16> %va, %splat358 ret <vscale x 2 x i16> %vc359}360 361define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {362; CHECK-LABEL: vor_vx_nxv2i16_0:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma365; CHECK-NEXT: vor.vi v8, v8, -12366; CHECK-NEXT: ret367 %vc = or <vscale x 2 x i16> %va, splat (i16 -12)368 ret <vscale x 2 x i16> %vc369}370 371define <vscale x 2 x i16> @vor_vx_nxv2i16_1(<vscale x 2 x i16> %va) {372; CHECK-LABEL: vor_vx_nxv2i16_1:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma375; CHECK-NEXT: vor.vi v8, v8, 15376; CHECK-NEXT: ret377 %vc = or <vscale x 2 x i16> %va, splat (i16 15)378 ret <vscale x 2 x i16> %vc379}380 381define <vscale x 2 x i16> @vor_vx_nxv2i16_2(<vscale x 2 x i16> %va) {382; CHECK-LABEL: vor_vx_nxv2i16_2:383; CHECK: # %bb.0:384; CHECK-NEXT: li a0, 16385; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma386; CHECK-NEXT: vor.vx v8, v8, a0387; CHECK-NEXT: ret388 %vc = or <vscale x 2 x i16> %va, splat (i16 16)389 ret <vscale x 2 x i16> %vc390}391 392define <vscale x 4 x i16> @vor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {393; CHECK-LABEL: vor_vx_nxv4i16:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma396; CHECK-NEXT: vor.vx v8, v8, a0397; CHECK-NEXT: ret398 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0399 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer400 %vc = or <vscale x 4 x i16> %va, %splat401 ret <vscale x 4 x i16> %vc402}403 404define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {405; CHECK-LABEL: vor_vx_nxv4i16_0:406; CHECK: # %bb.0:407; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma408; CHECK-NEXT: vor.vi v8, v8, -12409; CHECK-NEXT: ret410 %vc = or <vscale x 4 x i16> %va, splat (i16 -12)411 ret <vscale x 4 x i16> %vc412}413 414define <vscale x 4 x i16> @vor_vx_nxv4i16_1(<vscale x 4 x i16> %va) {415; CHECK-LABEL: vor_vx_nxv4i16_1:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma418; CHECK-NEXT: vor.vi v8, v8, 15419; CHECK-NEXT: ret420 %vc = or <vscale x 4 x i16> %va, splat (i16 15)421 ret <vscale x 4 x i16> %vc422}423 424define <vscale x 4 x i16> @vor_vx_nxv4i16_2(<vscale x 4 x i16> %va) {425; CHECK-LABEL: vor_vx_nxv4i16_2:426; CHECK: # %bb.0:427; CHECK-NEXT: li a0, 16428; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma429; CHECK-NEXT: vor.vx v8, v8, a0430; CHECK-NEXT: ret431 %vc = or <vscale x 4 x i16> %va, splat (i16 16)432 ret <vscale x 4 x i16> %vc433}434 435define <vscale x 8 x i16> @vor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {436; CHECK-LABEL: vor_vx_nxv8i16:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma439; CHECK-NEXT: vor.vx v8, v8, a0440; CHECK-NEXT: ret441 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0442 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer443 %vc = or <vscale x 8 x i16> %va, %splat444 ret <vscale x 8 x i16> %vc445}446 447define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {448; CHECK-LABEL: vor_vx_nxv8i16_0:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma451; CHECK-NEXT: vor.vi v8, v8, -12452; CHECK-NEXT: ret453 %vc = or <vscale x 8 x i16> %va, splat (i16 -12)454 ret <vscale x 8 x i16> %vc455}456 457define <vscale x 8 x i16> @vor_vx_nxv8i16_1(<vscale x 8 x i16> %va) {458; CHECK-LABEL: vor_vx_nxv8i16_1:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma461; CHECK-NEXT: vor.vi v8, v8, 15462; CHECK-NEXT: ret463 %vc = or <vscale x 8 x i16> %va, splat (i16 15)464 ret <vscale x 8 x i16> %vc465}466 467define <vscale x 8 x i16> @vor_vx_nxv8i16_2(<vscale x 8 x i16> %va) {468; CHECK-LABEL: vor_vx_nxv8i16_2:469; CHECK: # %bb.0:470; CHECK-NEXT: li a0, 16471; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma472; CHECK-NEXT: vor.vx v8, v8, a0473; CHECK-NEXT: ret474 %vc = or <vscale x 8 x i16> %va, splat (i16 16)475 ret <vscale x 8 x i16> %vc476}477 478define <vscale x 16 x i16> @vor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {479; CHECK-LABEL: vor_vx_nxv16i16:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma482; CHECK-NEXT: vor.vx v8, v8, a0483; CHECK-NEXT: ret484 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0485 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer486 %vc = or <vscale x 16 x i16> %va, %splat487 ret <vscale x 16 x i16> %vc488}489 490define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {491; CHECK-LABEL: vor_vx_nxv16i16_0:492; CHECK: # %bb.0:493; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma494; CHECK-NEXT: vor.vi v8, v8, -12495; CHECK-NEXT: ret496 %vc = or <vscale x 16 x i16> %va, splat (i16 -12)497 ret <vscale x 16 x i16> %vc498}499 500define <vscale x 16 x i16> @vor_vx_nxv16i16_1(<vscale x 16 x i16> %va) {501; CHECK-LABEL: vor_vx_nxv16i16_1:502; CHECK: # %bb.0:503; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma504; CHECK-NEXT: vor.vi v8, v8, 15505; CHECK-NEXT: ret506 %vc = or <vscale x 16 x i16> %va, splat (i16 15)507 ret <vscale x 16 x i16> %vc508}509 510define <vscale x 16 x i16> @vor_vx_nxv16i16_2(<vscale x 16 x i16> %va) {511; CHECK-LABEL: vor_vx_nxv16i16_2:512; CHECK: # %bb.0:513; CHECK-NEXT: li a0, 16514; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma515; CHECK-NEXT: vor.vx v8, v8, a0516; CHECK-NEXT: ret517 %vc = or <vscale x 16 x i16> %va, splat (i16 16)518 ret <vscale x 16 x i16> %vc519}520 521define <vscale x 32 x i16> @vor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {522; CHECK-LABEL: vor_vx_nxv32i16:523; CHECK: # %bb.0:524; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma525; CHECK-NEXT: vor.vx v8, v8, a0526; CHECK-NEXT: ret527 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0528 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer529 %vc = or <vscale x 32 x i16> %va, %splat530 ret <vscale x 32 x i16> %vc531}532 533define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {534; CHECK-LABEL: vor_vx_nxv32i16_0:535; CHECK: # %bb.0:536; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma537; CHECK-NEXT: vor.vi v8, v8, -12538; CHECK-NEXT: ret539 %vc = or <vscale x 32 x i16> %va, splat (i16 -12)540 ret <vscale x 32 x i16> %vc541}542 543define <vscale x 32 x i16> @vor_vx_nxv32i16_1(<vscale x 32 x i16> %va) {544; CHECK-LABEL: vor_vx_nxv32i16_1:545; CHECK: # %bb.0:546; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma547; CHECK-NEXT: vor.vi v8, v8, 15548; CHECK-NEXT: ret549 %vc = or <vscale x 32 x i16> %va, splat (i16 15)550 ret <vscale x 32 x i16> %vc551}552 553define <vscale x 32 x i16> @vor_vx_nxv32i16_2(<vscale x 32 x i16> %va) {554; CHECK-LABEL: vor_vx_nxv32i16_2:555; CHECK: # %bb.0:556; CHECK-NEXT: li a0, 16557; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma558; CHECK-NEXT: vor.vx v8, v8, a0559; CHECK-NEXT: ret560 %vc = or <vscale x 32 x i16> %va, splat (i16 16)561 ret <vscale x 32 x i16> %vc562}563 564define <vscale x 1 x i32> @vor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {565; CHECK-LABEL: vor_vx_nxv1i32:566; CHECK: # %bb.0:567; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma568; CHECK-NEXT: vor.vx v8, v8, a0569; CHECK-NEXT: ret570 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0571 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer572 %vc = or <vscale x 1 x i32> %va, %splat573 ret <vscale x 1 x i32> %vc574}575 576define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {577; CHECK-LABEL: vor_vx_nxv1i32_0:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma580; CHECK-NEXT: vor.vi v8, v8, -12581; CHECK-NEXT: ret582 %vc = or <vscale x 1 x i32> %va, splat (i32 -12)583 ret <vscale x 1 x i32> %vc584}585 586define <vscale x 1 x i32> @vor_vx_nxv1i32_1(<vscale x 1 x i32> %va) {587; CHECK-LABEL: vor_vx_nxv1i32_1:588; CHECK: # %bb.0:589; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma590; CHECK-NEXT: vor.vi v8, v8, 15591; CHECK-NEXT: ret592 %vc = or <vscale x 1 x i32> %va, splat (i32 15)593 ret <vscale x 1 x i32> %vc594}595 596define <vscale x 1 x i32> @vor_vx_nxv1i32_2(<vscale x 1 x i32> %va) {597; CHECK-LABEL: vor_vx_nxv1i32_2:598; CHECK: # %bb.0:599; CHECK-NEXT: li a0, 16600; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma601; CHECK-NEXT: vor.vx v8, v8, a0602; CHECK-NEXT: ret603 %vc = or <vscale x 1 x i32> %va, splat (i32 16)604 ret <vscale x 1 x i32> %vc605}606 607define <vscale x 2 x i32> @vor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {608; CHECK-LABEL: vor_vx_nxv2i32:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma611; CHECK-NEXT: vor.vx v8, v8, a0612; CHECK-NEXT: ret613 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0614 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer615 %vc = or <vscale x 2 x i32> %va, %splat616 ret <vscale x 2 x i32> %vc617}618 619define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {620; CHECK-LABEL: vor_vx_nxv2i32_0:621; CHECK: # %bb.0:622; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma623; CHECK-NEXT: vor.vi v8, v8, -12624; CHECK-NEXT: ret625 %vc = or <vscale x 2 x i32> %va, splat (i32 -12)626 ret <vscale x 2 x i32> %vc627}628 629define <vscale x 2 x i32> @vor_vx_nxv2i32_1(<vscale x 2 x i32> %va) {630; CHECK-LABEL: vor_vx_nxv2i32_1:631; CHECK: # %bb.0:632; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma633; CHECK-NEXT: vor.vi v8, v8, 15634; CHECK-NEXT: ret635 %vc = or <vscale x 2 x i32> %va, splat (i32 15)636 ret <vscale x 2 x i32> %vc637}638 639define <vscale x 2 x i32> @vor_vx_nxv2i32_2(<vscale x 2 x i32> %va) {640; CHECK-LABEL: vor_vx_nxv2i32_2:641; CHECK: # %bb.0:642; CHECK-NEXT: li a0, 16643; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma644; CHECK-NEXT: vor.vx v8, v8, a0645; CHECK-NEXT: ret646 %vc = or <vscale x 2 x i32> %va, splat (i32 16)647 ret <vscale x 2 x i32> %vc648}649 650define <vscale x 4 x i32> @vor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {651; CHECK-LABEL: vor_vx_nxv4i32:652; CHECK: # %bb.0:653; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma654; CHECK-NEXT: vor.vx v8, v8, a0655; CHECK-NEXT: ret656 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0657 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer658 %vc = or <vscale x 4 x i32> %va, %splat659 ret <vscale x 4 x i32> %vc660}661 662define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {663; CHECK-LABEL: vor_vx_nxv4i32_0:664; CHECK: # %bb.0:665; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma666; CHECK-NEXT: vor.vi v8, v8, -12667; CHECK-NEXT: ret668 %vc = or <vscale x 4 x i32> %va, splat (i32 -12)669 ret <vscale x 4 x i32> %vc670}671 672define <vscale x 4 x i32> @vor_vx_nxv4i32_1(<vscale x 4 x i32> %va) {673; CHECK-LABEL: vor_vx_nxv4i32_1:674; CHECK: # %bb.0:675; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma676; CHECK-NEXT: vor.vi v8, v8, 15677; CHECK-NEXT: ret678 %vc = or <vscale x 4 x i32> %va, splat (i32 15)679 ret <vscale x 4 x i32> %vc680}681 682define <vscale x 4 x i32> @vor_vx_nxv4i32_2(<vscale x 4 x i32> %va) {683; CHECK-LABEL: vor_vx_nxv4i32_2:684; CHECK: # %bb.0:685; CHECK-NEXT: li a0, 16686; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma687; CHECK-NEXT: vor.vx v8, v8, a0688; CHECK-NEXT: ret689 %vc = or <vscale x 4 x i32> %va, splat (i32 16)690 ret <vscale x 4 x i32> %vc691}692 693define <vscale x 8 x i32> @vor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {694; CHECK-LABEL: vor_vx_nxv8i32:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma697; CHECK-NEXT: vor.vx v8, v8, a0698; CHECK-NEXT: ret699 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0700 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer701 %vc = or <vscale x 8 x i32> %va, %splat702 ret <vscale x 8 x i32> %vc703}704 705define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {706; CHECK-LABEL: vor_vx_nxv8i32_0:707; CHECK: # %bb.0:708; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma709; CHECK-NEXT: vor.vi v8, v8, -12710; CHECK-NEXT: ret711 %vc = or <vscale x 8 x i32> %va, splat (i32 -12)712 ret <vscale x 8 x i32> %vc713}714 715define <vscale x 8 x i32> @vor_vx_nxv8i32_1(<vscale x 8 x i32> %va) {716; CHECK-LABEL: vor_vx_nxv8i32_1:717; CHECK: # %bb.0:718; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma719; CHECK-NEXT: vor.vi v8, v8, 15720; CHECK-NEXT: ret721 %vc = or <vscale x 8 x i32> %va, splat (i32 15)722 ret <vscale x 8 x i32> %vc723}724 725define <vscale x 8 x i32> @vor_vx_nxv8i32_2(<vscale x 8 x i32> %va) {726; CHECK-LABEL: vor_vx_nxv8i32_2:727; CHECK: # %bb.0:728; CHECK-NEXT: li a0, 16729; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma730; CHECK-NEXT: vor.vx v8, v8, a0731; CHECK-NEXT: ret732 %vc = or <vscale x 8 x i32> %va, splat (i32 16)733 ret <vscale x 8 x i32> %vc734}735 736define <vscale x 16 x i32> @vor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {737; CHECK-LABEL: vor_vx_nxv16i32:738; CHECK: # %bb.0:739; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma740; CHECK-NEXT: vor.vx v8, v8, a0741; CHECK-NEXT: ret742 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0743 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer744 %vc = or <vscale x 16 x i32> %va, %splat745 ret <vscale x 16 x i32> %vc746}747 748define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {749; CHECK-LABEL: vor_vx_nxv16i32_0:750; CHECK: # %bb.0:751; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma752; CHECK-NEXT: vor.vi v8, v8, -12753; CHECK-NEXT: ret754 %vc = or <vscale x 16 x i32> %va, splat (i32 -12)755 ret <vscale x 16 x i32> %vc756}757 758define <vscale x 16 x i32> @vor_vx_nxv16i32_1(<vscale x 16 x i32> %va) {759; CHECK-LABEL: vor_vx_nxv16i32_1:760; CHECK: # %bb.0:761; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma762; CHECK-NEXT: vor.vi v8, v8, 15763; CHECK-NEXT: ret764 %vc = or <vscale x 16 x i32> %va, splat (i32 15)765 ret <vscale x 16 x i32> %vc766}767 768define <vscale x 16 x i32> @vor_vx_nxv16i32_2(<vscale x 16 x i32> %va) {769; CHECK-LABEL: vor_vx_nxv16i32_2:770; CHECK: # %bb.0:771; CHECK-NEXT: li a0, 16772; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma773; CHECK-NEXT: vor.vx v8, v8, a0774; CHECK-NEXT: ret775 %vc = or <vscale x 16 x i32> %va, splat (i32 16)776 ret <vscale x 16 x i32> %vc777}778 779define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {780; RV32-LABEL: vor_vx_nxv1i64:781; RV32: # %bb.0:782; RV32-NEXT: addi sp, sp, -16783; RV32-NEXT: .cfi_def_cfa_offset 16784; RV32-NEXT: sw a0, 8(sp)785; RV32-NEXT: sw a1, 12(sp)786; RV32-NEXT: addi a0, sp, 8787; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma788; RV32-NEXT: vlse64.v v9, (a0), zero789; RV32-NEXT: vor.vv v8, v8, v9790; RV32-NEXT: addi sp, sp, 16791; RV32-NEXT: .cfi_def_cfa_offset 0792; RV32-NEXT: ret793;794; RV64-LABEL: vor_vx_nxv1i64:795; RV64: # %bb.0:796; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma797; RV64-NEXT: vor.vx v8, v8, a0798; RV64-NEXT: ret799 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0800 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer801 %vc = or <vscale x 1 x i64> %va, %splat802 ret <vscale x 1 x i64> %vc803}804 805define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {806; CHECK-LABEL: vor_vx_nxv1i64_0:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma809; CHECK-NEXT: vor.vi v8, v8, -12810; CHECK-NEXT: ret811 %vc = or <vscale x 1 x i64> %va, splat (i64 -12)812 ret <vscale x 1 x i64> %vc813}814 815define <vscale x 1 x i64> @vor_vx_nxv1i64_1(<vscale x 1 x i64> %va) {816; CHECK-LABEL: vor_vx_nxv1i64_1:817; CHECK: # %bb.0:818; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma819; CHECK-NEXT: vor.vi v8, v8, 15820; CHECK-NEXT: ret821 %vc = or <vscale x 1 x i64> %va, splat (i64 15)822 ret <vscale x 1 x i64> %vc823}824 825define <vscale x 1 x i64> @vor_vx_nxv1i64_2(<vscale x 1 x i64> %va) {826; CHECK-LABEL: vor_vx_nxv1i64_2:827; CHECK: # %bb.0:828; CHECK-NEXT: li a0, 16829; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma830; CHECK-NEXT: vor.vx v8, v8, a0831; CHECK-NEXT: ret832 %vc = or <vscale x 1 x i64> %va, splat (i64 16)833 ret <vscale x 1 x i64> %vc834}835 836define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {837; RV32-LABEL: vor_vx_nxv2i64:838; RV32: # %bb.0:839; RV32-NEXT: addi sp, sp, -16840; RV32-NEXT: .cfi_def_cfa_offset 16841; RV32-NEXT: sw a0, 8(sp)842; RV32-NEXT: sw a1, 12(sp)843; RV32-NEXT: addi a0, sp, 8844; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma845; RV32-NEXT: vlse64.v v10, (a0), zero846; RV32-NEXT: vor.vv v8, v8, v10847; RV32-NEXT: addi sp, sp, 16848; RV32-NEXT: .cfi_def_cfa_offset 0849; RV32-NEXT: ret850;851; RV64-LABEL: vor_vx_nxv2i64:852; RV64: # %bb.0:853; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma854; RV64-NEXT: vor.vx v8, v8, a0855; RV64-NEXT: ret856 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0857 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer858 %vc = or <vscale x 2 x i64> %va, %splat859 ret <vscale x 2 x i64> %vc860}861 862define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {863; CHECK-LABEL: vor_vx_nxv2i64_0:864; CHECK: # %bb.0:865; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma866; CHECK-NEXT: vor.vi v8, v8, -12867; CHECK-NEXT: ret868 %vc = or <vscale x 2 x i64> %va, splat (i64 -12)869 ret <vscale x 2 x i64> %vc870}871 872define <vscale x 2 x i64> @vor_vx_nxv2i64_1(<vscale x 2 x i64> %va) {873; CHECK-LABEL: vor_vx_nxv2i64_1:874; CHECK: # %bb.0:875; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma876; CHECK-NEXT: vor.vi v8, v8, 15877; CHECK-NEXT: ret878 %vc = or <vscale x 2 x i64> %va, splat (i64 15)879 ret <vscale x 2 x i64> %vc880}881 882define <vscale x 2 x i64> @vor_vx_nxv2i64_2(<vscale x 2 x i64> %va) {883; CHECK-LABEL: vor_vx_nxv2i64_2:884; CHECK: # %bb.0:885; CHECK-NEXT: li a0, 16886; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma887; CHECK-NEXT: vor.vx v8, v8, a0888; CHECK-NEXT: ret889 %vc = or <vscale x 2 x i64> %va, splat (i64 16)890 ret <vscale x 2 x i64> %vc891}892 893define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {894; RV32-LABEL: vor_vx_nxv4i64:895; RV32: # %bb.0:896; RV32-NEXT: addi sp, sp, -16897; RV32-NEXT: .cfi_def_cfa_offset 16898; RV32-NEXT: sw a0, 8(sp)899; RV32-NEXT: sw a1, 12(sp)900; RV32-NEXT: addi a0, sp, 8901; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma902; RV32-NEXT: vlse64.v v12, (a0), zero903; RV32-NEXT: vor.vv v8, v8, v12904; RV32-NEXT: addi sp, sp, 16905; RV32-NEXT: .cfi_def_cfa_offset 0906; RV32-NEXT: ret907;908; RV64-LABEL: vor_vx_nxv4i64:909; RV64: # %bb.0:910; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma911; RV64-NEXT: vor.vx v8, v8, a0912; RV64-NEXT: ret913 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0914 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer915 %vc = or <vscale x 4 x i64> %va, %splat916 ret <vscale x 4 x i64> %vc917}918 919define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {920; CHECK-LABEL: vor_vx_nxv4i64_0:921; CHECK: # %bb.0:922; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma923; CHECK-NEXT: vor.vi v8, v8, -12924; CHECK-NEXT: ret925 %vc = or <vscale x 4 x i64> %va, splat (i64 -12)926 ret <vscale x 4 x i64> %vc927}928 929define <vscale x 4 x i64> @vor_vx_nxv4i64_1(<vscale x 4 x i64> %va) {930; CHECK-LABEL: vor_vx_nxv4i64_1:931; CHECK: # %bb.0:932; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma933; CHECK-NEXT: vor.vi v8, v8, 15934; CHECK-NEXT: ret935 %vc = or <vscale x 4 x i64> %va, splat (i64 15)936 ret <vscale x 4 x i64> %vc937}938 939define <vscale x 4 x i64> @vor_vx_nxv4i64_2(<vscale x 4 x i64> %va) {940; CHECK-LABEL: vor_vx_nxv4i64_2:941; CHECK: # %bb.0:942; CHECK-NEXT: li a0, 16943; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma944; CHECK-NEXT: vor.vx v8, v8, a0945; CHECK-NEXT: ret946 %vc = or <vscale x 4 x i64> %va, splat (i64 16)947 ret <vscale x 4 x i64> %vc948}949 950define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {951; RV32-LABEL: vor_vx_nxv8i64:952; RV32: # %bb.0:953; RV32-NEXT: addi sp, sp, -16954; RV32-NEXT: .cfi_def_cfa_offset 16955; RV32-NEXT: sw a0, 8(sp)956; RV32-NEXT: sw a1, 12(sp)957; RV32-NEXT: addi a0, sp, 8958; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma959; RV32-NEXT: vlse64.v v16, (a0), zero960; RV32-NEXT: vor.vv v8, v8, v16961; RV32-NEXT: addi sp, sp, 16962; RV32-NEXT: .cfi_def_cfa_offset 0963; RV32-NEXT: ret964;965; RV64-LABEL: vor_vx_nxv8i64:966; RV64: # %bb.0:967; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma968; RV64-NEXT: vor.vx v8, v8, a0969; RV64-NEXT: ret970 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0971 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer972 %vc = or <vscale x 8 x i64> %va, %splat973 ret <vscale x 8 x i64> %vc974}975 976define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {977; CHECK-LABEL: vor_vx_nxv8i64_0:978; CHECK: # %bb.0:979; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma980; CHECK-NEXT: vor.vi v8, v8, -12981; CHECK-NEXT: ret982 %vc = or <vscale x 8 x i64> %va, splat (i64 -12)983 ret <vscale x 8 x i64> %vc984}985 986define <vscale x 8 x i64> @vor_vx_nxv8i64_1(<vscale x 8 x i64> %va) {987; CHECK-LABEL: vor_vx_nxv8i64_1:988; CHECK: # %bb.0:989; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma990; CHECK-NEXT: vor.vi v8, v8, 15991; CHECK-NEXT: ret992 %vc = or <vscale x 8 x i64> %va, splat (i64 15)993 ret <vscale x 8 x i64> %vc994}995 996define <vscale x 8 x i64> @vor_vx_nxv8i64_2(<vscale x 8 x i64> %va) {997; CHECK-LABEL: vor_vx_nxv8i64_2:998; CHECK: # %bb.0:999; CHECK-NEXT: li a0, 161000; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1001; CHECK-NEXT: vor.vx v8, v8, a01002; CHECK-NEXT: ret1003 %vc = or <vscale x 8 x i64> %va, splat (i64 16)1004 ret <vscale x 8 x i64> %vc1005}1006 1007 1008define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) {1009; CHECK-LABEL: vor_vx_nxv8i64_3:1010; CHECK: # %bb.0:1011; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1012; CHECK-NEXT: vmv.v.i v8, -11013; CHECK-NEXT: ret1014 %vc = or <vscale x 8 x i64> %va, splat (i64 -1)1015 ret <vscale x 8 x i64> %vc1016}1017 1018define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {1019; RV32-LABEL: vor_xx_nxv8i64:1020; RV32: # %bb.0:1021; RV32-NEXT: addi sp, sp, -161022; RV32-NEXT: or a1, a1, a31023; RV32-NEXT: or a0, a0, a21024; RV32-NEXT: sw a0, 8(sp)1025; RV32-NEXT: sw a1, 12(sp)1026; RV32-NEXT: addi a0, sp, 81027; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1028; RV32-NEXT: vlse64.v v8, (a0), zero1029; RV32-NEXT: addi sp, sp, 161030; RV32-NEXT: ret1031;1032; RV64-LABEL: vor_xx_nxv8i64:1033; RV64: # %bb.0:1034; RV64-NEXT: or a0, a0, a11035; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1036; RV64-NEXT: vmv.v.x v8, a01037; RV64-NEXT: ret1038 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 01039 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1040 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01041 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1042 %v = or <vscale x 8 x i64> %splat1, %splat21043 ret <vscale x 8 x i64> %v1044}1045 1046define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {1047; CHECK-LABEL: vor_vv_mask_nxv8i32:1048; CHECK: # %bb.0:1049; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu1050; CHECK-NEXT: vor.vv v8, v8, v12, v0.t1051; CHECK-NEXT: ret1052 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer1053 %vc = or <vscale x 8 x i32> %va, %vs1054 ret <vscale x 8 x i32> %vc1055}1056 1057define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {1058; CHECK-LABEL: vor_vx_mask_nxv8i32:1059; CHECK: # %bb.0:1060; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu1061; CHECK-NEXT: vor.vx v8, v8, a0, v0.t1062; CHECK-NEXT: ret1063 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01064 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1065 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer1066 %vc = or <vscale x 8 x i32> %va, %vs1067 ret <vscale x 8 x i32> %vc1068}1069 1070define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {1071; CHECK-LABEL: vor_vi_mask_nxv8i32:1072; CHECK: # %bb.0:1073; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu1074; CHECK-NEXT: vor.vi v8, v8, 7, v0.t1075; CHECK-NEXT: ret1076 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> zeroinitializer1077 %vc = or <vscale x 8 x i32> %va, %vs1078 ret <vscale x 8 x i32> %vc1079}1080