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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s4 5define void @test_store_reverse_combiner(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, i32 zeroext %evl) {6; CHECK-LABEL: test_store_reverse_combiner:7; CHECK: # %bb.0:8; CHECK-NEXT: slli a2, a1, 29; CHECK-NEXT: add a0, a2, a010; CHECK-NEXT: addi a0, a0, -411; CHECK-NEXT: li a2, -412; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma13; CHECK-NEXT: vsse32.v v8, (a0), a214; CHECK-NEXT: ret15 %rev = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %val, <vscale x 2 x i1> splat (i1 true), i32 %evl)16 call void @llvm.vp.store.nxv2f32.p0nxv2f32(<vscale x 2 x float> %rev, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)17 ret void18}19 20define void @test_store_mask_is_vp_reverse(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %mask, i32 zeroext %evl) {21; CHECK-LABEL: test_store_mask_is_vp_reverse:22; CHECK: # %bb.0:23; CHECK-NEXT: slli a2, a1, 224; CHECK-NEXT: add a0, a2, a025; CHECK-NEXT: addi a0, a0, -426; CHECK-NEXT: li a2, -427; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma28; CHECK-NEXT: vsse32.v v8, (a0), a2, v0.t29; CHECK-NEXT: ret30 %storemask = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> splat (i1 true), i32 %evl)31 %rev = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %val, <vscale x 2 x i1> splat (i1 true), i32 %evl)32 call void @llvm.vp.store.nxv2f32.p0nxv2f32(<vscale x 2 x float> %rev, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %storemask, i32 %evl)33 ret void34}35 36define void @test_store_mask_not_all_one(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %notallones, i32 zeroext %evl) {37; CHECK-LABEL: test_store_mask_not_all_one:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma40; CHECK-NEXT: vid.v v9, v0.t41; CHECK-NEXT: addi a1, a1, -142; CHECK-NEXT: vrsub.vx v9, v9, a1, v0.t43; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t44; CHECK-NEXT: vse32.v v10, (a0), v0.t45; CHECK-NEXT: ret46 %rev = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %val, <vscale x 2 x i1> %notallones, i32 %evl)47 call void @llvm.vp.store.nxv2f32.p0nxv2f32(<vscale x 2 x float> %rev, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %notallones, i32 %evl)48 ret void49}50 51define void @test_different_evl(<vscale x 2 x float> %val, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %mask, i32 zeroext %evl1, i32 zeroext %evl2) {52; CHECK-LABEL: test_different_evl:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma55; CHECK-NEXT: vid.v v956; CHECK-NEXT: addi a1, a1, -157; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma58; CHECK-NEXT: vmv.v.i v10, 059; CHECK-NEXT: vmerge.vim v10, v10, 1, v060; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma61; CHECK-NEXT: vid.v v1162; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma63; CHECK-NEXT: vrsub.vx v9, v9, a164; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma65; CHECK-NEXT: vrsub.vx v11, v11, a166; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma67; CHECK-NEXT: vrgatherei16.vv v12, v10, v968; CHECK-NEXT: vmsne.vi v0, v12, 069; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma70; CHECK-NEXT: vrgather.vv v9, v8, v1171; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma72; CHECK-NEXT: vse32.v v9, (a0), v0.t73; CHECK-NEXT: ret74 %storemask = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> splat (i1 true), i32 %evl1)75 %rev = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %val, <vscale x 2 x i1> splat (i1 true), i32 %evl1)76 call void @llvm.vp.store.nxv2f32.p0nxv2f32(<vscale x 2 x float> %rev, <vscale x 2 x float>* %ptr, <vscale x 2 x i1> %storemask, i32 %evl2)77 ret void78}79 80