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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr='+v' -verify-machineinstrs | FileCheck %s --check-prefix=RV323; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr='+v' -verify-machineinstrs | FileCheck %s --check-prefix=RV644 5define iXLen @bool_vec(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m, i32 %evl) {6; RV32-LABEL: bool_vec:7; RV32: # %bb.0:8; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma9; RV32-NEXT: vmv1r.v v9, v010; RV32-NEXT: vmv1r.v v0, v811; RV32-NEXT: vfirst.m a1, v9, v0.t12; RV32-NEXT: bltz a1, .LBB0_213; RV32-NEXT: # %bb.1:14; RV32-NEXT: mv a0, a115; RV32-NEXT: .LBB0_2:16; RV32-NEXT: ret17;18; RV64-LABEL: bool_vec:19; RV64: # %bb.0:20; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma21; RV64-NEXT: vmv1r.v v9, v022; RV64-NEXT: slli a0, a0, 3223; RV64-NEXT: srli a0, a0, 3224; RV64-NEXT: vmv1r.v v0, v825; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma26; RV64-NEXT: vfirst.m a1, v9, v0.t27; RV64-NEXT: bltz a1, .LBB0_228; RV64-NEXT: # %bb.1:29; RV64-NEXT: mv a0, a130; RV64-NEXT: .LBB0_2:31; RV64-NEXT: ret32 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i1(<vscale x 2 x i1> %src, i1 0, <vscale x 2 x i1> %m, i32 %evl)33 ret iXLen %r34}35 36define iXLen @bool_vec_zero_poison(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m, i32 %evl) {37; RV32-LABEL: bool_vec_zero_poison:38; RV32: # %bb.0:39; RV32-NEXT: vsetvli zero, a0, e8, mf4, ta, ma40; RV32-NEXT: vmv1r.v v9, v041; RV32-NEXT: vmv1r.v v0, v842; RV32-NEXT: vfirst.m a0, v9, v0.t43; RV32-NEXT: ret44;45; RV64-LABEL: bool_vec_zero_poison:46; RV64: # %bb.0:47; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma48; RV64-NEXT: vmv1r.v v9, v049; RV64-NEXT: slli a0, a0, 3250; RV64-NEXT: srli a0, a0, 3251; RV64-NEXT: vmv1r.v v0, v852; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma53; RV64-NEXT: vfirst.m a0, v9, v0.t54; RV64-NEXT: ret55 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i1(<vscale x 2 x i1> %src, i1 1, <vscale x 2 x i1> %m, i32 %evl)56 ret iXLen %r57}58 59define iXLen @nxv2i32(<vscale x 2 x i32> %src, <vscale x 2 x i1> %m, i32 %evl) {60; RV32-LABEL: nxv2i32:61; RV32: # %bb.0:62; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma63; RV32-NEXT: vmsne.vi v8, v8, 0, v0.t64; RV32-NEXT: vfirst.m a1, v8, v0.t65; RV32-NEXT: bltz a1, .LBB2_266; RV32-NEXT: # %bb.1:67; RV32-NEXT: mv a0, a168; RV32-NEXT: .LBB2_2:69; RV32-NEXT: ret70;71; RV64-LABEL: nxv2i32:72; RV64: # %bb.0:73; RV64-NEXT: slli a0, a0, 3274; RV64-NEXT: srli a0, a0, 3275; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma76; RV64-NEXT: vmsne.vi v8, v8, 0, v0.t77; RV64-NEXT: vfirst.m a1, v8, v0.t78; RV64-NEXT: bltz a1, .LBB2_279; RV64-NEXT: # %bb.1:80; RV64-NEXT: mv a0, a181; RV64-NEXT: .LBB2_2:82; RV64-NEXT: ret83 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i32(<vscale x 2 x i32> %src, i1 0, <vscale x 2 x i1> %m, i32 %evl)84 ret iXLen %r85}86 87define iXLen @nxv2i32_zero_poison(<vscale x 2 x i32> %src, <vscale x 2 x i1> %m, i32 %evl) {88; RV32-LABEL: nxv2i32_zero_poison:89; RV32: # %bb.0:90; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma91; RV32-NEXT: vmsne.vi v8, v8, 0, v0.t92; RV32-NEXT: vfirst.m a0, v8, v0.t93; RV32-NEXT: ret94;95; RV64-LABEL: nxv2i32_zero_poison:96; RV64: # %bb.0:97; RV64-NEXT: slli a0, a0, 3298; RV64-NEXT: srli a0, a0, 3299; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma100; RV64-NEXT: vmsne.vi v8, v8, 0, v0.t101; RV64-NEXT: vfirst.m a0, v8, v0.t102; RV64-NEXT: ret103 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i32(<vscale x 2 x i32> %src, i1 1, <vscale x 2 x i1> %m, i32 %evl)104 ret iXLen %r105}106 107define iXLen @nxv2i64(<vscale x 2 x i64> %src, <vscale x 2 x i1> %m, i32 %evl) {108; RV32-LABEL: nxv2i64:109; RV32: # %bb.0:110; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma111; RV32-NEXT: vmsne.vi v10, v8, 0, v0.t112; RV32-NEXT: vfirst.m a1, v10, v0.t113; RV32-NEXT: bltz a1, .LBB4_2114; RV32-NEXT: # %bb.1:115; RV32-NEXT: mv a0, a1116; RV32-NEXT: .LBB4_2:117; RV32-NEXT: ret118;119; RV64-LABEL: nxv2i64:120; RV64: # %bb.0:121; RV64-NEXT: slli a0, a0, 32122; RV64-NEXT: srli a0, a0, 32123; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma124; RV64-NEXT: vmsne.vi v10, v8, 0, v0.t125; RV64-NEXT: vfirst.m a1, v10, v0.t126; RV64-NEXT: bltz a1, .LBB4_2127; RV64-NEXT: # %bb.1:128; RV64-NEXT: mv a0, a1129; RV64-NEXT: .LBB4_2:130; RV64-NEXT: ret131 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i64(<vscale x 2 x i64> %src, i1 0, <vscale x 2 x i1> %m, i32 %evl)132 ret iXLen %r133}134 135define iXLen @nxv2i64_zero_poison(<vscale x 2 x i64> %src, <vscale x 2 x i1> %m, i32 %evl) {136; RV32-LABEL: nxv2i64_zero_poison:137; RV32: # %bb.0:138; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma139; RV32-NEXT: vmsne.vi v10, v8, 0, v0.t140; RV32-NEXT: vfirst.m a0, v10, v0.t141; RV32-NEXT: ret142;143; RV64-LABEL: nxv2i64_zero_poison:144; RV64: # %bb.0:145; RV64-NEXT: slli a0, a0, 32146; RV64-NEXT: srli a0, a0, 32147; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma148; RV64-NEXT: vmsne.vi v10, v8, 0, v0.t149; RV64-NEXT: vfirst.m a0, v10, v0.t150; RV64-NEXT: ret151 %r = call iXLen @llvm.vp.cttz.elts.iXLen.nxv2i64(<vscale x 2 x i64> %src, i1 1, <vscale x 2 x i1> %m, i32 %evl)152 ret iXLen %r153}154 155define i1 @nxv2i32_cmp_evl(<vscale x 2 x i32> %src, <vscale x 2 x i1> %m, i32 %evl) {156; RV32-LABEL: nxv2i32_cmp_evl:157; RV32: # %bb.0:158; RV32-NEXT: vsetvli zero, a0, e32, m1, ta, ma159; RV32-NEXT: vmsne.vi v8, v8, 0, v0.t160; RV32-NEXT: vfirst.m a2, v8, v0.t161; RV32-NEXT: mv a1, a0162; RV32-NEXT: bltz a2, .LBB6_2163; RV32-NEXT: # %bb.1:164; RV32-NEXT: mv a1, a2165; RV32-NEXT: .LBB6_2:166; RV32-NEXT: xor a0, a1, a0167; RV32-NEXT: seqz a0, a0168; RV32-NEXT: ret169;170; RV64-LABEL: nxv2i32_cmp_evl:171; RV64: # %bb.0:172; RV64-NEXT: slli a1, a0, 32173; RV64-NEXT: srli a1, a1, 32174; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma175; RV64-NEXT: vmsne.vi v8, v8, 0, v0.t176; RV64-NEXT: vfirst.m a2, v8, v0.t177; RV64-NEXT: sext.w a0, a0178; RV64-NEXT: bltz a2, .LBB6_2179; RV64-NEXT: # %bb.1:180; RV64-NEXT: mv a1, a2181; RV64-NEXT: .LBB6_2:182; RV64-NEXT: sext.w a1, a1183; RV64-NEXT: xor a0, a1, a0184; RV64-NEXT: seqz a0, a0185; RV64-NEXT: ret186 %r = call i32 @llvm.vp.cttz.elts.i32.nxv2i32(<vscale x 2 x i32> %src, i1 0, <vscale x 2 x i1> %m, i32 %evl)187 %cmp = icmp eq i32 %r, %evl188 ret i1 %cmp189}190 191define iXLen @fixed_v2i64(<2 x i64> %src, <2 x i1> %m, i32 %evl) {192; RV32-LABEL: fixed_v2i64:193; RV32: # %bb.0:194; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma195; RV32-NEXT: vmsne.vi v8, v8, 0, v0.t196; RV32-NEXT: vfirst.m a1, v8, v0.t197; RV32-NEXT: bltz a1, .LBB7_2198; RV32-NEXT: # %bb.1:199; RV32-NEXT: mv a0, a1200; RV32-NEXT: .LBB7_2:201; RV32-NEXT: ret202;203; RV64-LABEL: fixed_v2i64:204; RV64: # %bb.0:205; RV64-NEXT: slli a0, a0, 32206; RV64-NEXT: srli a0, a0, 32207; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma208; RV64-NEXT: vmsne.vi v8, v8, 0, v0.t209; RV64-NEXT: vfirst.m a1, v8, v0.t210; RV64-NEXT: bltz a1, .LBB7_2211; RV64-NEXT: # %bb.1:212; RV64-NEXT: mv a0, a1213; RV64-NEXT: .LBB7_2:214; RV64-NEXT: ret215 %r = call iXLen @llvm.vp.cttz.elts.iXLen.v2i64(<2 x i64> %src, i1 0, <2 x i1> %m, i32 %evl)216 ret iXLen %r217}218 219define iXLen @fixed_v2i64_zero_poison(<2 x i64> %src, <2 x i1> %m, i32 %evl) {220; RV32-LABEL: fixed_v2i64_zero_poison:221; RV32: # %bb.0:222; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma223; RV32-NEXT: vmsne.vi v8, v8, 0, v0.t224; RV32-NEXT: vfirst.m a0, v8, v0.t225; RV32-NEXT: ret226;227; RV64-LABEL: fixed_v2i64_zero_poison:228; RV64: # %bb.0:229; RV64-NEXT: slli a0, a0, 32230; RV64-NEXT: srli a0, a0, 32231; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma232; RV64-NEXT: vmsne.vi v8, v8, 0, v0.t233; RV64-NEXT: vfirst.m a0, v8, v0.t234; RV64-NEXT: ret235 %r = call iXLen @llvm.vp.cttz.elts.iXLen.v2i64(<2 x i64> %src, i1 1, <2 x i1> %m, i32 %evl)236 ret iXLen %r237}238 239