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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s3 4define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {5; CHECK-LABEL: inttoptr_nxv4p0_nxv4i8:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma8; CHECK-NEXT: vmv1r.v v12, v89; CHECK-NEXT: vzext.vf8 v8, v12, v0.t10; CHECK-NEXT: ret11 %v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl)12 ret <vscale x 4 x ptr> %v13}14 15define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: inttoptr_nxv4p0_nxv4i16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma19; CHECK-NEXT: vmv1r.v v12, v820; CHECK-NEXT: vzext.vf4 v8, v12, v0.t21; CHECK-NEXT: ret22 %v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)23 ret <vscale x 4 x ptr> %v24}25 26define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {27; CHECK-LABEL: inttoptr_nxv4p0_nxv4i32:28; CHECK: # %bb.0:29; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma30; CHECK-NEXT: vmv2r.v v12, v831; CHECK-NEXT: vzext.vf2 v8, v12, v0.t32; CHECK-NEXT: ret33 %v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)34 ret <vscale x 4 x ptr> %v35}36 37define <vscale x 4 x ptr> @inttoptr_nxv4p0_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: inttoptr_nxv4p0_nxv4i64:39; CHECK: # %bb.0:40; CHECK-NEXT: ret41 %v = call <vscale x 4 x ptr> @llvm.vp.inttoptr.nxv4p0.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)42 ret <vscale x 4 x ptr> %v43}44 45define <vscale x 4 x i8> @ptrtoint_nxv4i8_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {46; CHECK-LABEL: ptrtoint_nxv4i8_nxv4p0:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma49; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t50; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma51; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t52; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma53; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t54; CHECK-NEXT: ret55 %v = call <vscale x 4 x i8> @llvm.vp.ptrtoint.nxv4i8.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)56 ret <vscale x 4 x i8> %v57}58 59define <vscale x 4 x i16> @ptrtoint_nxv4i16_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: ptrtoint_nxv4i16_nxv4p0:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma63; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t64; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma65; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t66; CHECK-NEXT: ret67 %v = call <vscale x 4 x i16> @llvm.vp.ptrtoint.nxv4i16.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)68 ret <vscale x 4 x i16> %v69}70 71define <vscale x 4 x i32> @ptrtoint_nxv4i32_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: ptrtoint_nxv4i32_nxv4p0:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma75; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t76; CHECK-NEXT: vmv.v.v v8, v1277; CHECK-NEXT: ret78 %v = call <vscale x 4 x i32> @llvm.vp.ptrtoint.nxv4i32.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)79 ret <vscale x 4 x i32> %v80}81 82define <vscale x 4 x i64> @ptrtoint_nxv4i64_nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {83; CHECK-LABEL: ptrtoint_nxv4i64_nxv4p0:84; CHECK: # %bb.0:85; CHECK-NEXT: ret86 %v = call <vscale x 4 x i64> @llvm.vp.ptrtoint.nxv4i64.nxv4p0(<vscale x 4 x ptr> %va, <vscale x 4 x i1> %m, i32 %evl)87 ret <vscale x 4 x i64> %v88}89