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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x half> @test_vp_reverse_nxv1f16_masked(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {6; CHECK-LABEL: test_vp_reverse_nxv1f16_masked:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma9; CHECK-NEXT: vid.v v9, v0.t10; CHECK-NEXT: addi a0, a0, -111; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t12; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t13; CHECK-NEXT: vmv1r.v v8, v914; CHECK-NEXT: ret15 %dst = call <vscale x 1 x half> @llvm.experimental.vp.reverse.nxv1f16(<vscale x 1 x half> %src, <vscale x 1 x i1> %mask, i32 %evl)16 ret <vscale x 1 x half> %dst17}18 19define <vscale x 1 x half> @test_vp_reverse_nxv1f16(<vscale x 1 x half> %src, i32 zeroext %evl) {20; CHECK-LABEL: test_vp_reverse_nxv1f16:21; CHECK: # %bb.0:22; CHECK-NEXT: addi a1, a0, -123; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma24; CHECK-NEXT: vid.v v925; CHECK-NEXT: vrsub.vx v10, v9, a126; CHECK-NEXT: vrgather.vv v9, v8, v1027; CHECK-NEXT: vmv1r.v v8, v928; CHECK-NEXT: ret29 30 %dst = call <vscale x 1 x half> @llvm.experimental.vp.reverse.nxv1f16(<vscale x 1 x half> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)31 ret <vscale x 1 x half> %dst32}33 34define <vscale x 1 x float> @test_vp_reverse_nxv1f32_masked(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {35; CHECK-LABEL: test_vp_reverse_nxv1f32_masked:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma38; CHECK-NEXT: vid.v v9, v0.t39; CHECK-NEXT: addi a0, a0, -140; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t41; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t42; CHECK-NEXT: vmv1r.v v8, v943; CHECK-NEXT: ret44 %dst = call <vscale x 1 x float> @llvm.experimental.vp.reverse.nxv1f32(<vscale x 1 x float> %src, <vscale x 1 x i1> %mask, i32 %evl)45 ret <vscale x 1 x float> %dst46}47 48define <vscale x 1 x float> @test_vp_reverse_nxv1f32(<vscale x 1 x float> %src, i32 zeroext %evl) {49; CHECK-LABEL: test_vp_reverse_nxv1f32:50; CHECK: # %bb.0:51; CHECK-NEXT: addi a1, a0, -152; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma53; CHECK-NEXT: vid.v v954; CHECK-NEXT: vrsub.vx v10, v9, a155; CHECK-NEXT: vrgather.vv v9, v8, v1056; CHECK-NEXT: vmv1r.v v8, v957; CHECK-NEXT: ret58 59 %dst = call <vscale x 1 x float> @llvm.experimental.vp.reverse.nxv1f32(<vscale x 1 x float> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)60 ret <vscale x 1 x float> %dst61}62 63define <vscale x 2 x half> @test_vp_reverse_nxv2f16_masked(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {64; CHECK-LABEL: test_vp_reverse_nxv2f16_masked:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma67; CHECK-NEXT: vid.v v9, v0.t68; CHECK-NEXT: addi a0, a0, -169; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t70; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t71; CHECK-NEXT: vmv1r.v v8, v972; CHECK-NEXT: ret73 %dst = call <vscale x 2 x half> @llvm.experimental.vp.reverse.nxv2f16(<vscale x 2 x half> %src, <vscale x 2 x i1> %mask, i32 %evl)74 ret <vscale x 2 x half> %dst75}76 77define <vscale x 2 x half> @test_vp_reverse_nxv2f16(<vscale x 2 x half> %src, i32 zeroext %evl) {78; CHECK-LABEL: test_vp_reverse_nxv2f16:79; CHECK: # %bb.0:80; CHECK-NEXT: addi a1, a0, -181; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma82; CHECK-NEXT: vid.v v983; CHECK-NEXT: vrsub.vx v10, v9, a184; CHECK-NEXT: vrgather.vv v9, v8, v1085; CHECK-NEXT: vmv1r.v v8, v986; CHECK-NEXT: ret87 88 %dst = call <vscale x 2 x half> @llvm.experimental.vp.reverse.nxv2f16(<vscale x 2 x half> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)89 ret <vscale x 2 x half> %dst90}91 92define <vscale x 1 x double> @test_vp_reverse_nxv1f64_masked(<vscale x 1 x double> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {93; CHECK-LABEL: test_vp_reverse_nxv1f64_masked:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma96; CHECK-NEXT: vid.v v9, v0.t97; CHECK-NEXT: addi a0, a0, -198; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t99; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t100; CHECK-NEXT: vmv.v.v v8, v9101; CHECK-NEXT: ret102 %dst = call <vscale x 1 x double> @llvm.experimental.vp.reverse.nxv1f64(<vscale x 1 x double> %src, <vscale x 1 x i1> %mask, i32 %evl)103 ret <vscale x 1 x double> %dst104}105 106define <vscale x 1 x double> @test_vp_reverse_nxv1f64(<vscale x 1 x double> %src, i32 zeroext %evl) {107; CHECK-LABEL: test_vp_reverse_nxv1f64:108; CHECK: # %bb.0:109; CHECK-NEXT: addi a1, a0, -1110; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma111; CHECK-NEXT: vid.v v9112; CHECK-NEXT: vrsub.vx v10, v9, a1113; CHECK-NEXT: vrgather.vv v9, v8, v10114; CHECK-NEXT: vmv.v.v v8, v9115; CHECK-NEXT: ret116 117 %dst = call <vscale x 1 x double> @llvm.experimental.vp.reverse.nxv1f64(<vscale x 1 x double> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)118 ret <vscale x 1 x double> %dst119}120 121define <vscale x 2 x float> @test_vp_reverse_nxv2f32_masked(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {122; CHECK-LABEL: test_vp_reverse_nxv2f32_masked:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma125; CHECK-NEXT: vid.v v9, v0.t126; CHECK-NEXT: addi a0, a0, -1127; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t128; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t129; CHECK-NEXT: vmv.v.v v8, v9130; CHECK-NEXT: ret131 %dst = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %src, <vscale x 2 x i1> %mask, i32 %evl)132 ret <vscale x 2 x float> %dst133}134 135define <vscale x 2 x float> @test_vp_reverse_nxv2f32(<vscale x 2 x float> %src, i32 zeroext %evl) {136; CHECK-LABEL: test_vp_reverse_nxv2f32:137; CHECK: # %bb.0:138; CHECK-NEXT: addi a1, a0, -1139; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma140; CHECK-NEXT: vid.v v9141; CHECK-NEXT: vrsub.vx v10, v9, a1142; CHECK-NEXT: vrgather.vv v9, v8, v10143; CHECK-NEXT: vmv.v.v v8, v9144; CHECK-NEXT: ret145 146 %dst = call <vscale x 2 x float> @llvm.experimental.vp.reverse.nxv2f32(<vscale x 2 x float> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)147 ret <vscale x 2 x float> %dst148}149 150define <vscale x 4 x half> @test_vp_reverse_nxv4f16_masked(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {151; CHECK-LABEL: test_vp_reverse_nxv4f16_masked:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma154; CHECK-NEXT: vid.v v9, v0.t155; CHECK-NEXT: addi a0, a0, -1156; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t157; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t158; CHECK-NEXT: vmv.v.v v8, v9159; CHECK-NEXT: ret160 %dst = call <vscale x 4 x half> @llvm.experimental.vp.reverse.nxv4f16(<vscale x 4 x half> %src, <vscale x 4 x i1> %mask, i32 %evl)161 ret <vscale x 4 x half> %dst162}163 164define <vscale x 4 x half> @test_vp_reverse_nxv4f16(<vscale x 4 x half> %src, i32 zeroext %evl) {165; CHECK-LABEL: test_vp_reverse_nxv4f16:166; CHECK: # %bb.0:167; CHECK-NEXT: addi a1, a0, -1168; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma169; CHECK-NEXT: vid.v v9170; CHECK-NEXT: vrsub.vx v10, v9, a1171; CHECK-NEXT: vrgather.vv v9, v8, v10172; CHECK-NEXT: vmv.v.v v8, v9173; CHECK-NEXT: ret174 175 %dst = call <vscale x 4 x half> @llvm.experimental.vp.reverse.nxv4f16(<vscale x 4 x half> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)176 ret <vscale x 4 x half> %dst177}178 179define <vscale x 2 x double> @test_vp_reverse_nxv2f64_masked(<vscale x 2 x double> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {180; CHECK-LABEL: test_vp_reverse_nxv2f64_masked:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma183; CHECK-NEXT: vid.v v10, v0.t184; CHECK-NEXT: addi a0, a0, -1185; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t186; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t187; CHECK-NEXT: vmv.v.v v8, v10188; CHECK-NEXT: ret189 %dst = call <vscale x 2 x double> @llvm.experimental.vp.reverse.nxv2f64(<vscale x 2 x double> %src, <vscale x 2 x i1> %mask, i32 %evl)190 ret <vscale x 2 x double> %dst191}192 193define <vscale x 2 x double> @test_vp_reverse_nxv2f64(<vscale x 2 x double> %src, i32 zeroext %evl) {194; CHECK-LABEL: test_vp_reverse_nxv2f64:195; CHECK: # %bb.0:196; CHECK-NEXT: addi a1, a0, -1197; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma198; CHECK-NEXT: vid.v v10199; CHECK-NEXT: vrsub.vx v12, v10, a1200; CHECK-NEXT: vrgather.vv v10, v8, v12201; CHECK-NEXT: vmv.v.v v8, v10202; CHECK-NEXT: ret203 204 %dst = call <vscale x 2 x double> @llvm.experimental.vp.reverse.nxv2f64(<vscale x 2 x double> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)205 ret <vscale x 2 x double> %dst206}207 208define <vscale x 4 x float> @test_vp_reverse_nxv4f32_masked(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {209; CHECK-LABEL: test_vp_reverse_nxv4f32_masked:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma212; CHECK-NEXT: vid.v v10, v0.t213; CHECK-NEXT: addi a0, a0, -1214; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t215; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t216; CHECK-NEXT: vmv.v.v v8, v10217; CHECK-NEXT: ret218 %dst = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> %src, <vscale x 4 x i1> %mask, i32 %evl)219 ret <vscale x 4 x float> %dst220}221 222define <vscale x 4 x float> @test_vp_reverse_nxv4f32(<vscale x 4 x float> %src, i32 zeroext %evl) {223; CHECK-LABEL: test_vp_reverse_nxv4f32:224; CHECK: # %bb.0:225; CHECK-NEXT: addi a1, a0, -1226; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma227; CHECK-NEXT: vid.v v10228; CHECK-NEXT: vrsub.vx v12, v10, a1229; CHECK-NEXT: vrgather.vv v10, v8, v12230; CHECK-NEXT: vmv.v.v v8, v10231; CHECK-NEXT: ret232 233 %dst = call <vscale x 4 x float> @llvm.experimental.vp.reverse.nxv4f32(<vscale x 4 x float> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)234 ret <vscale x 4 x float> %dst235}236 237define <vscale x 8 x half> @test_vp_reverse_nxv8f16_masked(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {238; CHECK-LABEL: test_vp_reverse_nxv8f16_masked:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma241; CHECK-NEXT: vid.v v10, v0.t242; CHECK-NEXT: addi a0, a0, -1243; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t244; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t245; CHECK-NEXT: vmv.v.v v8, v10246; CHECK-NEXT: ret247 %dst = call <vscale x 8 x half> @llvm.experimental.vp.reverse.nxv8f16(<vscale x 8 x half> %src, <vscale x 8 x i1> %mask, i32 %evl)248 ret <vscale x 8 x half> %dst249}250 251define <vscale x 8 x half> @test_vp_reverse_nxv8f16(<vscale x 8 x half> %src, i32 zeroext %evl) {252; CHECK-LABEL: test_vp_reverse_nxv8f16:253; CHECK: # %bb.0:254; CHECK-NEXT: addi a1, a0, -1255; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma256; CHECK-NEXT: vid.v v10257; CHECK-NEXT: vrsub.vx v12, v10, a1258; CHECK-NEXT: vrgather.vv v10, v8, v12259; CHECK-NEXT: vmv.v.v v8, v10260; CHECK-NEXT: ret261 262 %dst = call <vscale x 8 x half> @llvm.experimental.vp.reverse.nxv8f16(<vscale x 8 x half> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)263 ret <vscale x 8 x half> %dst264}265 266define <vscale x 4 x double> @test_vp_reverse_nxv4f64_masked(<vscale x 4 x double> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {267; CHECK-LABEL: test_vp_reverse_nxv4f64_masked:268; CHECK: # %bb.0:269; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma270; CHECK-NEXT: vid.v v12, v0.t271; CHECK-NEXT: addi a0, a0, -1272; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t273; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t274; CHECK-NEXT: vmv.v.v v8, v12275; CHECK-NEXT: ret276 %dst = call <vscale x 4 x double> @llvm.experimental.vp.reverse.nxv4f64(<vscale x 4 x double> %src, <vscale x 4 x i1> %mask, i32 %evl)277 ret <vscale x 4 x double> %dst278}279 280define <vscale x 4 x double> @test_vp_reverse_nxv4f64(<vscale x 4 x double> %src, i32 zeroext %evl) {281; CHECK-LABEL: test_vp_reverse_nxv4f64:282; CHECK: # %bb.0:283; CHECK-NEXT: addi a1, a0, -1284; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma285; CHECK-NEXT: vid.v v12286; CHECK-NEXT: vrsub.vx v16, v12, a1287; CHECK-NEXT: vrgather.vv v12, v8, v16288; CHECK-NEXT: vmv.v.v v8, v12289; CHECK-NEXT: ret290 291 %dst = call <vscale x 4 x double> @llvm.experimental.vp.reverse.nxv4f64(<vscale x 4 x double> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)292 ret <vscale x 4 x double> %dst293}294 295define <vscale x 8 x float> @test_vp_reverse_nxv8f32_masked(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {296; CHECK-LABEL: test_vp_reverse_nxv8f32_masked:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma299; CHECK-NEXT: vid.v v12, v0.t300; CHECK-NEXT: addi a0, a0, -1301; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t302; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t303; CHECK-NEXT: vmv.v.v v8, v12304; CHECK-NEXT: ret305 %dst = call <vscale x 8 x float> @llvm.experimental.vp.reverse.nxv8f32(<vscale x 8 x float> %src, <vscale x 8 x i1> %mask, i32 %evl)306 ret <vscale x 8 x float> %dst307}308 309define <vscale x 8 x float> @test_vp_reverse_nxv8f32(<vscale x 8 x float> %src, i32 zeroext %evl) {310; CHECK-LABEL: test_vp_reverse_nxv8f32:311; CHECK: # %bb.0:312; CHECK-NEXT: addi a1, a0, -1313; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma314; CHECK-NEXT: vid.v v12315; CHECK-NEXT: vrsub.vx v16, v12, a1316; CHECK-NEXT: vrgather.vv v12, v8, v16317; CHECK-NEXT: vmv.v.v v8, v12318; CHECK-NEXT: ret319 320 %dst = call <vscale x 8 x float> @llvm.experimental.vp.reverse.nxv8f32(<vscale x 8 x float> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)321 ret <vscale x 8 x float> %dst322}323 324define <vscale x 16 x half> @test_vp_reverse_nxv16f16_masked(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {325; CHECK-LABEL: test_vp_reverse_nxv16f16_masked:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma328; CHECK-NEXT: vid.v v12, v0.t329; CHECK-NEXT: addi a0, a0, -1330; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t331; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t332; CHECK-NEXT: vmv.v.v v8, v12333; CHECK-NEXT: ret334 %dst = call <vscale x 16 x half> @llvm.experimental.vp.reverse.nxv16f16(<vscale x 16 x half> %src, <vscale x 16 x i1> %mask, i32 %evl)335 ret <vscale x 16 x half> %dst336}337 338define <vscale x 16 x half> @test_vp_reverse_nxv16f16(<vscale x 16 x half> %src, i32 zeroext %evl) {339; CHECK-LABEL: test_vp_reverse_nxv16f16:340; CHECK: # %bb.0:341; CHECK-NEXT: addi a1, a0, -1342; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma343; CHECK-NEXT: vid.v v12344; CHECK-NEXT: vrsub.vx v16, v12, a1345; CHECK-NEXT: vrgather.vv v12, v8, v16346; CHECK-NEXT: vmv.v.v v8, v12347; CHECK-NEXT: ret348 349 %dst = call <vscale x 16 x half> @llvm.experimental.vp.reverse.nxv16f16(<vscale x 16 x half> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)350 ret <vscale x 16 x half> %dst351}352 353define <vscale x 8 x double> @test_vp_reverse_nxv8f64_masked(<vscale x 8 x double> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {354; CHECK-LABEL: test_vp_reverse_nxv8f64_masked:355; CHECK: # %bb.0:356; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma357; CHECK-NEXT: vid.v v16, v0.t358; CHECK-NEXT: addi a0, a0, -1359; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t360; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t361; CHECK-NEXT: vmv.v.v v8, v16362; CHECK-NEXT: ret363 %dst = call <vscale x 8 x double> @llvm.experimental.vp.reverse.nxv8f64(<vscale x 8 x double> %src, <vscale x 8 x i1> %mask, i32 %evl)364 ret <vscale x 8 x double> %dst365}366 367define <vscale x 8 x double> @test_vp_reverse_nxv8f64(<vscale x 8 x double> %src, i32 zeroext %evl) {368; CHECK-LABEL: test_vp_reverse_nxv8f64:369; CHECK: # %bb.0:370; CHECK-NEXT: addi a1, a0, -1371; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma372; CHECK-NEXT: vid.v v16373; CHECK-NEXT: vrsub.vx v24, v16, a1374; CHECK-NEXT: vrgather.vv v16, v8, v24375; CHECK-NEXT: vmv.v.v v8, v16376; CHECK-NEXT: ret377 378 %dst = call <vscale x 8 x double> @llvm.experimental.vp.reverse.nxv8f64(<vscale x 8 x double> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)379 ret <vscale x 8 x double> %dst380}381 382define <vscale x 16 x float> @test_vp_reverse_nxv16f32_masked(<vscale x 16 x float> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {383; CHECK-LABEL: test_vp_reverse_nxv16f32_masked:384; CHECK: # %bb.0:385; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma386; CHECK-NEXT: vid.v v16, v0.t387; CHECK-NEXT: addi a0, a0, -1388; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t389; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t390; CHECK-NEXT: vmv.v.v v8, v16391; CHECK-NEXT: ret392 %dst = call <vscale x 16 x float> @llvm.experimental.vp.reverse.nxv16f32(<vscale x 16 x float> %src, <vscale x 16 x i1> %mask, i32 %evl)393 ret <vscale x 16 x float> %dst394}395 396define <vscale x 16 x float> @test_vp_reverse_nxv16f32(<vscale x 16 x float> %src, i32 zeroext %evl) {397; CHECK-LABEL: test_vp_reverse_nxv16f32:398; CHECK: # %bb.0:399; CHECK-NEXT: addi a1, a0, -1400; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma401; CHECK-NEXT: vid.v v16402; CHECK-NEXT: vrsub.vx v24, v16, a1403; CHECK-NEXT: vrgather.vv v16, v8, v24404; CHECK-NEXT: vmv.v.v v8, v16405; CHECK-NEXT: ret406 407 %dst = call <vscale x 16 x float> @llvm.experimental.vp.reverse.nxv16f32(<vscale x 16 x float> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)408 ret <vscale x 16 x float> %dst409}410 411define <vscale x 32 x half> @test_vp_reverse_nxv32f16_masked(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {412; CHECK-LABEL: test_vp_reverse_nxv32f16_masked:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma415; CHECK-NEXT: vid.v v16, v0.t416; CHECK-NEXT: addi a0, a0, -1417; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t418; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t419; CHECK-NEXT: vmv.v.v v8, v16420; CHECK-NEXT: ret421 %dst = call <vscale x 32 x half> @llvm.experimental.vp.reverse.nxv32f16(<vscale x 32 x half> %src, <vscale x 32 x i1> %mask, i32 %evl)422 ret <vscale x 32 x half> %dst423}424 425define <vscale x 32 x half> @test_vp_reverse_nxv32f16(<vscale x 32 x half> %src, i32 zeroext %evl) {426; CHECK-LABEL: test_vp_reverse_nxv32f16:427; CHECK: # %bb.0:428; CHECK-NEXT: addi a1, a0, -1429; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma430; CHECK-NEXT: vid.v v16431; CHECK-NEXT: vrsub.vx v24, v16, a1432; CHECK-NEXT: vrgather.vv v16, v8, v24433; CHECK-NEXT: vmv.v.v v8, v16434; CHECK-NEXT: ret435 436 %dst = call <vscale x 32 x half> @llvm.experimental.vp.reverse.nxv32f16(<vscale x 32 x half> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)437 ret <vscale x 32 x half> %dst438}439 440define <vscale x 1 x bfloat> @test_vp_reverse_nxv1bf16_masked(<vscale x 1 x bfloat> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {441; CHECK-LABEL: test_vp_reverse_nxv1bf16_masked:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma444; CHECK-NEXT: vid.v v9, v0.t445; CHECK-NEXT: addi a0, a0, -1446; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t447; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t448; CHECK-NEXT: vmv1r.v v8, v9449; CHECK-NEXT: ret450 %dst = call <vscale x 1 x bfloat> @llvm.experimental.vp.reverse.nxv1bf16(<vscale x 1 x bfloat> %src, <vscale x 1 x i1> %mask, i32 %evl)451 ret <vscale x 1 x bfloat> %dst452}453 454define <vscale x 1 x bfloat> @test_vp_reverse_nxv1bf16(<vscale x 1 x bfloat> %src, i32 zeroext %evl) {455; CHECK-LABEL: test_vp_reverse_nxv1bf16:456; CHECK: # %bb.0:457; CHECK-NEXT: addi a1, a0, -1458; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma459; CHECK-NEXT: vid.v v9460; CHECK-NEXT: vrsub.vx v10, v9, a1461; CHECK-NEXT: vrgather.vv v9, v8, v10462; CHECK-NEXT: vmv1r.v v8, v9463; CHECK-NEXT: ret464 465 %dst = call <vscale x 1 x bfloat> @llvm.experimental.vp.reverse.nxv1bf16(<vscale x 1 x bfloat> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)466 ret <vscale x 1 x bfloat> %dst467}468 469define <vscale x 2 x bfloat> @test_vp_reverse_nxv2bf16_masked(<vscale x 2 x bfloat> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {470; CHECK-LABEL: test_vp_reverse_nxv2bf16_masked:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma473; CHECK-NEXT: vid.v v9, v0.t474; CHECK-NEXT: addi a0, a0, -1475; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t476; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t477; CHECK-NEXT: vmv1r.v v8, v9478; CHECK-NEXT: ret479 %dst = call <vscale x 2 x bfloat> @llvm.experimental.vp.reverse.nxv2bf16(<vscale x 2 x bfloat> %src, <vscale x 2 x i1> %mask, i32 %evl)480 ret <vscale x 2 x bfloat> %dst481}482 483define <vscale x 2 x bfloat> @test_vp_reverse_nxv2bf16(<vscale x 2 x bfloat> %src, i32 zeroext %evl) {484; CHECK-LABEL: test_vp_reverse_nxv2bf16:485; CHECK: # %bb.0:486; CHECK-NEXT: addi a1, a0, -1487; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma488; CHECK-NEXT: vid.v v9489; CHECK-NEXT: vrsub.vx v10, v9, a1490; CHECK-NEXT: vrgather.vv v9, v8, v10491; CHECK-NEXT: vmv1r.v v8, v9492; CHECK-NEXT: ret493 494 %dst = call <vscale x 2 x bfloat> @llvm.experimental.vp.reverse.nxv2bf16(<vscale x 2 x bfloat> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)495 ret <vscale x 2 x bfloat> %dst496}497 498define <vscale x 4 x bfloat> @test_vp_reverse_nxv4bf16_masked(<vscale x 4 x bfloat> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {499; CHECK-LABEL: test_vp_reverse_nxv4bf16_masked:500; CHECK: # %bb.0:501; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma502; CHECK-NEXT: vid.v v9, v0.t503; CHECK-NEXT: addi a0, a0, -1504; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t505; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t506; CHECK-NEXT: vmv.v.v v8, v9507; CHECK-NEXT: ret508 %dst = call <vscale x 4 x bfloat> @llvm.experimental.vp.reverse.nxv4bf16(<vscale x 4 x bfloat> %src, <vscale x 4 x i1> %mask, i32 %evl)509 ret <vscale x 4 x bfloat> %dst510}511 512define <vscale x 4 x bfloat> @test_vp_reverse_nxv4bf16(<vscale x 4 x bfloat> %src, i32 zeroext %evl) {513; CHECK-LABEL: test_vp_reverse_nxv4bf16:514; CHECK: # %bb.0:515; CHECK-NEXT: addi a1, a0, -1516; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma517; CHECK-NEXT: vid.v v9518; CHECK-NEXT: vrsub.vx v10, v9, a1519; CHECK-NEXT: vrgather.vv v9, v8, v10520; CHECK-NEXT: vmv.v.v v8, v9521; CHECK-NEXT: ret522 523 %dst = call <vscale x 4 x bfloat> @llvm.experimental.vp.reverse.nxv4bf16(<vscale x 4 x bfloat> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)524 ret <vscale x 4 x bfloat> %dst525}526 527define <vscale x 8 x bfloat> @test_vp_reverse_nxv8bf16_masked(<vscale x 8 x bfloat> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {528; CHECK-LABEL: test_vp_reverse_nxv8bf16_masked:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma531; CHECK-NEXT: vid.v v10, v0.t532; CHECK-NEXT: addi a0, a0, -1533; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t534; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t535; CHECK-NEXT: vmv.v.v v8, v10536; CHECK-NEXT: ret537 %dst = call <vscale x 8 x bfloat> @llvm.experimental.vp.reverse.nxv8bf16(<vscale x 8 x bfloat> %src, <vscale x 8 x i1> %mask, i32 %evl)538 ret <vscale x 8 x bfloat> %dst539}540 541define <vscale x 8 x bfloat> @test_vp_reverse_nxv8bf16(<vscale x 8 x bfloat> %src, i32 zeroext %evl) {542; CHECK-LABEL: test_vp_reverse_nxv8bf16:543; CHECK: # %bb.0:544; CHECK-NEXT: addi a1, a0, -1545; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma546; CHECK-NEXT: vid.v v10547; CHECK-NEXT: vrsub.vx v12, v10, a1548; CHECK-NEXT: vrgather.vv v10, v8, v12549; CHECK-NEXT: vmv.v.v v8, v10550; CHECK-NEXT: ret551 552 %dst = call <vscale x 8 x bfloat> @llvm.experimental.vp.reverse.nxv8bf16(<vscale x 8 x bfloat> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)553 ret <vscale x 8 x bfloat> %dst554}555 556define <vscale x 16 x bfloat> @test_vp_reverse_nxv16bf16_masked(<vscale x 16 x bfloat> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {557; CHECK-LABEL: test_vp_reverse_nxv16bf16_masked:558; CHECK: # %bb.0:559; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma560; CHECK-NEXT: vid.v v12, v0.t561; CHECK-NEXT: addi a0, a0, -1562; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t563; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t564; CHECK-NEXT: vmv.v.v v8, v12565; CHECK-NEXT: ret566 %dst = call <vscale x 16 x bfloat> @llvm.experimental.vp.reverse.nxv16bf16(<vscale x 16 x bfloat> %src, <vscale x 16 x i1> %mask, i32 %evl)567 ret <vscale x 16 x bfloat> %dst568}569 570define <vscale x 16 x bfloat> @test_vp_reverse_nxv16bf16(<vscale x 16 x bfloat> %src, i32 zeroext %evl) {571; CHECK-LABEL: test_vp_reverse_nxv16bf16:572; CHECK: # %bb.0:573; CHECK-NEXT: addi a1, a0, -1574; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma575; CHECK-NEXT: vid.v v12576; CHECK-NEXT: vrsub.vx v16, v12, a1577; CHECK-NEXT: vrgather.vv v12, v8, v16578; CHECK-NEXT: vmv.v.v v8, v12579; CHECK-NEXT: ret580 581 %dst = call <vscale x 16 x bfloat> @llvm.experimental.vp.reverse.nxv16bf16(<vscale x 16 x bfloat> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)582 ret <vscale x 16 x bfloat> %dst583}584 585define <vscale x 32 x bfloat> @test_vp_reverse_nxv32bf16_masked(<vscale x 32 x bfloat> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {586; CHECK-LABEL: test_vp_reverse_nxv32bf16_masked:587; CHECK: # %bb.0:588; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma589; CHECK-NEXT: vid.v v16, v0.t590; CHECK-NEXT: addi a0, a0, -1591; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t592; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t593; CHECK-NEXT: vmv.v.v v8, v16594; CHECK-NEXT: ret595 %dst = call <vscale x 32 x bfloat> @llvm.experimental.vp.reverse.nxv32bf16(<vscale x 32 x bfloat> %src, <vscale x 32 x i1> %mask, i32 %evl)596 ret <vscale x 32 x bfloat> %dst597}598 599define <vscale x 32 x bfloat> @test_vp_reverse_nxv32bf16(<vscale x 32 x bfloat> %src, i32 zeroext %evl) {600; CHECK-LABEL: test_vp_reverse_nxv32bf16:601; CHECK: # %bb.0:602; CHECK-NEXT: addi a1, a0, -1603; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma604; CHECK-NEXT: vid.v v16605; CHECK-NEXT: vrsub.vx v24, v16, a1606; CHECK-NEXT: vrgather.vv v16, v8, v24607; CHECK-NEXT: vmv.v.v v8, v16608; CHECK-NEXT: ret609 610 %dst = call <vscale x 32 x bfloat> @llvm.experimental.vp.reverse.nxv32bf16(<vscale x 32 x bfloat> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)611 ret <vscale x 32 x bfloat> %dst612}613