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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3 4define <vscale x 1 x i8> @test_vp_reverse_nxv1i8_masked(<vscale x 1 x i8> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {5; CHECK-LABEL: test_vp_reverse_nxv1i8_masked:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma8; CHECK-NEXT: vid.v v9, v0.t9; CHECK-NEXT: addi a0, a0, -110; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t11; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma12; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t13; CHECK-NEXT: vmv1r.v v8, v914; CHECK-NEXT: ret15 %dst = call <vscale x 1 x i8> @llvm.experimental.vp.reverse.nxv1i8(<vscale x 1 x i8> %src, <vscale x 1 x i1> %mask, i32 %evl)16 ret <vscale x 1 x i8> %dst17}18 19define <vscale x 1 x i8> @test_vp_reverse_nxv1i8(<vscale x 1 x i8> %src, i32 zeroext %evl) {20; CHECK-LABEL: test_vp_reverse_nxv1i8:21; CHECK: # %bb.0:22; CHECK-NEXT: addi a1, a0, -123; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma24; CHECK-NEXT: vid.v v925; CHECK-NEXT: vrsub.vx v10, v9, a126; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma27; CHECK-NEXT: vrgatherei16.vv v9, v8, v1028; CHECK-NEXT: vmv1r.v v8, v929; CHECK-NEXT: ret30 31 %dst = call <vscale x 1 x i8> @llvm.experimental.vp.reverse.nxv1i8(<vscale x 1 x i8> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)32 ret <vscale x 1 x i8> %dst33}34 35define <vscale x 1 x i16> @test_vp_reverse_nxv1i16_masked(<vscale x 1 x i16> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {36; CHECK-LABEL: test_vp_reverse_nxv1i16_masked:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma39; CHECK-NEXT: vid.v v9, v0.t40; CHECK-NEXT: addi a0, a0, -141; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t42; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t43; CHECK-NEXT: vmv1r.v v8, v944; CHECK-NEXT: ret45 %dst = call <vscale x 1 x i16> @llvm.experimental.vp.reverse.nxv1i16(<vscale x 1 x i16> %src, <vscale x 1 x i1> %mask, i32 %evl)46 ret <vscale x 1 x i16> %dst47}48 49define <vscale x 1 x i16> @test_vp_reverse_nxv1i16(<vscale x 1 x i16> %src, i32 zeroext %evl) {50; CHECK-LABEL: test_vp_reverse_nxv1i16:51; CHECK: # %bb.0:52; CHECK-NEXT: addi a1, a0, -153; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma54; CHECK-NEXT: vid.v v955; CHECK-NEXT: vrsub.vx v10, v9, a156; CHECK-NEXT: vrgather.vv v9, v8, v1057; CHECK-NEXT: vmv1r.v v8, v958; CHECK-NEXT: ret59 60 %dst = call <vscale x 1 x i16> @llvm.experimental.vp.reverse.nxv1i16(<vscale x 1 x i16> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)61 ret <vscale x 1 x i16> %dst62}63 64define <vscale x 2 x i8> @test_vp_reverse_nxv2i8_masked(<vscale x 2 x i8> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {65; CHECK-LABEL: test_vp_reverse_nxv2i8_masked:66; CHECK: # %bb.0:67; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma68; CHECK-NEXT: vid.v v9, v0.t69; CHECK-NEXT: addi a0, a0, -170; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t71; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma72; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t73; CHECK-NEXT: vmv1r.v v8, v974; CHECK-NEXT: ret75 %dst = call <vscale x 2 x i8> @llvm.experimental.vp.reverse.nxv2i8(<vscale x 2 x i8> %src, <vscale x 2 x i1> %mask, i32 %evl)76 ret <vscale x 2 x i8> %dst77}78 79define <vscale x 2 x i8> @test_vp_reverse_nxv2i8(<vscale x 2 x i8> %src, i32 zeroext %evl) {80; CHECK-LABEL: test_vp_reverse_nxv2i8:81; CHECK: # %bb.0:82; CHECK-NEXT: addi a1, a0, -183; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma84; CHECK-NEXT: vid.v v985; CHECK-NEXT: vrsub.vx v10, v9, a186; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma87; CHECK-NEXT: vrgatherei16.vv v9, v8, v1088; CHECK-NEXT: vmv1r.v v8, v989; CHECK-NEXT: ret90 91 %dst = call <vscale x 2 x i8> @llvm.experimental.vp.reverse.nxv2i8(<vscale x 2 x i8> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)92 ret <vscale x 2 x i8> %dst93}94 95define <vscale x 1 x i32> @test_vp_reverse_nxv1i32_masked(<vscale x 1 x i32> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {96; CHECK-LABEL: test_vp_reverse_nxv1i32_masked:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma99; CHECK-NEXT: vid.v v9, v0.t100; CHECK-NEXT: addi a0, a0, -1101; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t102; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t103; CHECK-NEXT: vmv1r.v v8, v9104; CHECK-NEXT: ret105 %dst = call <vscale x 1 x i32> @llvm.experimental.vp.reverse.nxv1i32(<vscale x 1 x i32> %src, <vscale x 1 x i1> %mask, i32 %evl)106 ret <vscale x 1 x i32> %dst107}108 109define <vscale x 1 x i32> @test_vp_reverse_nxv1i32(<vscale x 1 x i32> %src, i32 zeroext %evl) {110; CHECK-LABEL: test_vp_reverse_nxv1i32:111; CHECK: # %bb.0:112; CHECK-NEXT: addi a1, a0, -1113; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma114; CHECK-NEXT: vid.v v9115; CHECK-NEXT: vrsub.vx v10, v9, a1116; CHECK-NEXT: vrgather.vv v9, v8, v10117; CHECK-NEXT: vmv1r.v v8, v9118; CHECK-NEXT: ret119 120 %dst = call <vscale x 1 x i32> @llvm.experimental.vp.reverse.nxv1i32(<vscale x 1 x i32> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)121 ret <vscale x 1 x i32> %dst122}123 124define <vscale x 2 x i16> @test_vp_reverse_nxv2i16_masked(<vscale x 2 x i16> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {125; CHECK-LABEL: test_vp_reverse_nxv2i16_masked:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma128; CHECK-NEXT: vid.v v9, v0.t129; CHECK-NEXT: addi a0, a0, -1130; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t131; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t132; CHECK-NEXT: vmv1r.v v8, v9133; CHECK-NEXT: ret134 %dst = call <vscale x 2 x i16> @llvm.experimental.vp.reverse.nxv2i16(<vscale x 2 x i16> %src, <vscale x 2 x i1> %mask, i32 %evl)135 ret <vscale x 2 x i16> %dst136}137 138define <vscale x 2 x i16> @test_vp_reverse_nxv2i16(<vscale x 2 x i16> %src, i32 zeroext %evl) {139; CHECK-LABEL: test_vp_reverse_nxv2i16:140; CHECK: # %bb.0:141; CHECK-NEXT: addi a1, a0, -1142; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma143; CHECK-NEXT: vid.v v9144; CHECK-NEXT: vrsub.vx v10, v9, a1145; CHECK-NEXT: vrgather.vv v9, v8, v10146; CHECK-NEXT: vmv1r.v v8, v9147; CHECK-NEXT: ret148 149 %dst = call <vscale x 2 x i16> @llvm.experimental.vp.reverse.nxv2i16(<vscale x 2 x i16> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)150 ret <vscale x 2 x i16> %dst151}152 153define <vscale x 4 x i8> @test_vp_reverse_nxv4i8_masked(<vscale x 4 x i8> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {154; CHECK-LABEL: test_vp_reverse_nxv4i8_masked:155; CHECK: # %bb.0:156; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma157; CHECK-NEXT: vid.v v9, v0.t158; CHECK-NEXT: addi a0, a0, -1159; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t160; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma161; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t162; CHECK-NEXT: vmv1r.v v8, v9163; CHECK-NEXT: ret164 %dst = call <vscale x 4 x i8> @llvm.experimental.vp.reverse.nxv4i8(<vscale x 4 x i8> %src, <vscale x 4 x i1> %mask, i32 %evl)165 ret <vscale x 4 x i8> %dst166}167 168define <vscale x 4 x i8> @test_vp_reverse_nxv4i8(<vscale x 4 x i8> %src, i32 zeroext %evl) {169; CHECK-LABEL: test_vp_reverse_nxv4i8:170; CHECK: # %bb.0:171; CHECK-NEXT: addi a1, a0, -1172; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma173; CHECK-NEXT: vid.v v9174; CHECK-NEXT: vrsub.vx v10, v9, a1175; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma176; CHECK-NEXT: vrgatherei16.vv v9, v8, v10177; CHECK-NEXT: vmv1r.v v8, v9178; CHECK-NEXT: ret179 180 %dst = call <vscale x 4 x i8> @llvm.experimental.vp.reverse.nxv4i8(<vscale x 4 x i8> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)181 ret <vscale x 4 x i8> %dst182}183 184define <vscale x 1 x i64> @test_vp_reverse_nxv1i64_masked(<vscale x 1 x i64> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {185; CHECK-LABEL: test_vp_reverse_nxv1i64_masked:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma188; CHECK-NEXT: vid.v v9, v0.t189; CHECK-NEXT: addi a0, a0, -1190; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t191; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t192; CHECK-NEXT: vmv.v.v v8, v9193; CHECK-NEXT: ret194 %dst = call <vscale x 1 x i64> @llvm.experimental.vp.reverse.nxv1i64(<vscale x 1 x i64> %src, <vscale x 1 x i1> %mask, i32 %evl)195 ret <vscale x 1 x i64> %dst196}197 198define <vscale x 1 x i64> @test_vp_reverse_nxv1i64(<vscale x 1 x i64> %src, i32 zeroext %evl) {199; CHECK-LABEL: test_vp_reverse_nxv1i64:200; CHECK: # %bb.0:201; CHECK-NEXT: addi a1, a0, -1202; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma203; CHECK-NEXT: vid.v v9204; CHECK-NEXT: vrsub.vx v10, v9, a1205; CHECK-NEXT: vrgather.vv v9, v8, v10206; CHECK-NEXT: vmv.v.v v8, v9207; CHECK-NEXT: ret208 209 %dst = call <vscale x 1 x i64> @llvm.experimental.vp.reverse.nxv1i64(<vscale x 1 x i64> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)210 ret <vscale x 1 x i64> %dst211}212 213define <vscale x 2 x i32> @test_vp_reverse_nxv2i32_masked(<vscale x 2 x i32> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {214; CHECK-LABEL: test_vp_reverse_nxv2i32_masked:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma217; CHECK-NEXT: vid.v v9, v0.t218; CHECK-NEXT: addi a0, a0, -1219; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t220; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t221; CHECK-NEXT: vmv.v.v v8, v9222; CHECK-NEXT: ret223 %dst = call <vscale x 2 x i32> @llvm.experimental.vp.reverse.nxv2i32(<vscale x 2 x i32> %src, <vscale x 2 x i1> %mask, i32 %evl)224 ret <vscale x 2 x i32> %dst225}226 227define <vscale x 2 x i32> @test_vp_reverse_nxv2i32(<vscale x 2 x i32> %src, i32 zeroext %evl) {228; CHECK-LABEL: test_vp_reverse_nxv2i32:229; CHECK: # %bb.0:230; CHECK-NEXT: addi a1, a0, -1231; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma232; CHECK-NEXT: vid.v v9233; CHECK-NEXT: vrsub.vx v10, v9, a1234; CHECK-NEXT: vrgather.vv v9, v8, v10235; CHECK-NEXT: vmv.v.v v8, v9236; CHECK-NEXT: ret237 238 %dst = call <vscale x 2 x i32> @llvm.experimental.vp.reverse.nxv2i32(<vscale x 2 x i32> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)239 ret <vscale x 2 x i32> %dst240}241 242define <vscale x 4 x i16> @test_vp_reverse_nxv4i16_masked(<vscale x 4 x i16> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {243; CHECK-LABEL: test_vp_reverse_nxv4i16_masked:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma246; CHECK-NEXT: vid.v v9, v0.t247; CHECK-NEXT: addi a0, a0, -1248; CHECK-NEXT: vrsub.vx v10, v9, a0, v0.t249; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t250; CHECK-NEXT: vmv.v.v v8, v9251; CHECK-NEXT: ret252 %dst = call <vscale x 4 x i16> @llvm.experimental.vp.reverse.nxv4i16(<vscale x 4 x i16> %src, <vscale x 4 x i1> %mask, i32 %evl)253 ret <vscale x 4 x i16> %dst254}255 256define <vscale x 4 x i16> @test_vp_reverse_nxv4i16(<vscale x 4 x i16> %src, i32 zeroext %evl) {257; CHECK-LABEL: test_vp_reverse_nxv4i16:258; CHECK: # %bb.0:259; CHECK-NEXT: addi a1, a0, -1260; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma261; CHECK-NEXT: vid.v v9262; CHECK-NEXT: vrsub.vx v10, v9, a1263; CHECK-NEXT: vrgather.vv v9, v8, v10264; CHECK-NEXT: vmv.v.v v8, v9265; CHECK-NEXT: ret266 267 %dst = call <vscale x 4 x i16> @llvm.experimental.vp.reverse.nxv4i16(<vscale x 4 x i16> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)268 ret <vscale x 4 x i16> %dst269}270 271define <vscale x 8 x i8> @test_vp_reverse_nxv8i8_masked(<vscale x 8 x i8> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {272; CHECK-LABEL: test_vp_reverse_nxv8i8_masked:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma275; CHECK-NEXT: vid.v v10, v0.t276; CHECK-NEXT: addi a0, a0, -1277; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t278; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma279; CHECK-NEXT: vrgatherei16.vv v9, v8, v10, v0.t280; CHECK-NEXT: vmv.v.v v8, v9281; CHECK-NEXT: ret282 %dst = call <vscale x 8 x i8> @llvm.experimental.vp.reverse.nxv8i8(<vscale x 8 x i8> %src, <vscale x 8 x i1> %mask, i32 %evl)283 ret <vscale x 8 x i8> %dst284}285 286define <vscale x 8 x i8> @test_vp_reverse_nxv8i8(<vscale x 8 x i8> %src, i32 zeroext %evl) {287; CHECK-LABEL: test_vp_reverse_nxv8i8:288; CHECK: # %bb.0:289; CHECK-NEXT: addi a1, a0, -1290; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma291; CHECK-NEXT: vid.v v10292; CHECK-NEXT: vrsub.vx v10, v10, a1293; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma294; CHECK-NEXT: vrgatherei16.vv v9, v8, v10295; CHECK-NEXT: vmv.v.v v8, v9296; CHECK-NEXT: ret297 298 %dst = call <vscale x 8 x i8> @llvm.experimental.vp.reverse.nxv8i8(<vscale x 8 x i8> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)299 ret <vscale x 8 x i8> %dst300}301 302define <vscale x 2 x i64> @test_vp_reverse_nxv2i64_masked(<vscale x 2 x i64> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {303; CHECK-LABEL: test_vp_reverse_nxv2i64_masked:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma306; CHECK-NEXT: vid.v v10, v0.t307; CHECK-NEXT: addi a0, a0, -1308; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t309; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t310; CHECK-NEXT: vmv.v.v v8, v10311; CHECK-NEXT: ret312 %dst = call <vscale x 2 x i64> @llvm.experimental.vp.reverse.nxv2i64(<vscale x 2 x i64> %src, <vscale x 2 x i1> %mask, i32 %evl)313 ret <vscale x 2 x i64> %dst314}315 316define <vscale x 2 x i64> @test_vp_reverse_nxv2i64(<vscale x 2 x i64> %src, i32 zeroext %evl) {317; CHECK-LABEL: test_vp_reverse_nxv2i64:318; CHECK: # %bb.0:319; CHECK-NEXT: addi a1, a0, -1320; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma321; CHECK-NEXT: vid.v v10322; CHECK-NEXT: vrsub.vx v12, v10, a1323; CHECK-NEXT: vrgather.vv v10, v8, v12324; CHECK-NEXT: vmv.v.v v8, v10325; CHECK-NEXT: ret326 327 %dst = call <vscale x 2 x i64> @llvm.experimental.vp.reverse.nxv2i64(<vscale x 2 x i64> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)328 ret <vscale x 2 x i64> %dst329}330 331define <vscale x 4 x i32> @test_vp_reverse_nxv4i32_masked(<vscale x 4 x i32> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {332; CHECK-LABEL: test_vp_reverse_nxv4i32_masked:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma335; CHECK-NEXT: vid.v v10, v0.t336; CHECK-NEXT: addi a0, a0, -1337; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t338; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t339; CHECK-NEXT: vmv.v.v v8, v10340; CHECK-NEXT: ret341 %dst = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> %src, <vscale x 4 x i1> %mask, i32 %evl)342 ret <vscale x 4 x i32> %dst343}344 345define <vscale x 4 x i32> @test_vp_reverse_nxv4i32(<vscale x 4 x i32> %src, i32 zeroext %evl) {346; CHECK-LABEL: test_vp_reverse_nxv4i32:347; CHECK: # %bb.0:348; CHECK-NEXT: addi a1, a0, -1349; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma350; CHECK-NEXT: vid.v v10351; CHECK-NEXT: vrsub.vx v12, v10, a1352; CHECK-NEXT: vrgather.vv v10, v8, v12353; CHECK-NEXT: vmv.v.v v8, v10354; CHECK-NEXT: ret355 356 %dst = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)357 ret <vscale x 4 x i32> %dst358}359 360define <vscale x 8 x i16> @test_vp_reverse_nxv8i16_masked(<vscale x 8 x i16> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {361; CHECK-LABEL: test_vp_reverse_nxv8i16_masked:362; CHECK: # %bb.0:363; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma364; CHECK-NEXT: vid.v v10, v0.t365; CHECK-NEXT: addi a0, a0, -1366; CHECK-NEXT: vrsub.vx v12, v10, a0, v0.t367; CHECK-NEXT: vrgather.vv v10, v8, v12, v0.t368; CHECK-NEXT: vmv.v.v v8, v10369; CHECK-NEXT: ret370 %dst = call <vscale x 8 x i16> @llvm.experimental.vp.reverse.nxv8i16(<vscale x 8 x i16> %src, <vscale x 8 x i1> %mask, i32 %evl)371 ret <vscale x 8 x i16> %dst372}373 374define <vscale x 8 x i16> @test_vp_reverse_nxv8i16(<vscale x 8 x i16> %src, i32 zeroext %evl) {375; CHECK-LABEL: test_vp_reverse_nxv8i16:376; CHECK: # %bb.0:377; CHECK-NEXT: addi a1, a0, -1378; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma379; CHECK-NEXT: vid.v v10380; CHECK-NEXT: vrsub.vx v12, v10, a1381; CHECK-NEXT: vrgather.vv v10, v8, v12382; CHECK-NEXT: vmv.v.v v8, v10383; CHECK-NEXT: ret384 385 %dst = call <vscale x 8 x i16> @llvm.experimental.vp.reverse.nxv8i16(<vscale x 8 x i16> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)386 ret <vscale x 8 x i16> %dst387}388 389define <vscale x 16 x i8> @test_vp_reverse_nxv16i8_masked(<vscale x 16 x i8> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {390; CHECK-LABEL: test_vp_reverse_nxv16i8_masked:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma393; CHECK-NEXT: vid.v v12, v0.t394; CHECK-NEXT: addi a0, a0, -1395; CHECK-NEXT: vrsub.vx v12, v12, a0, v0.t396; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma397; CHECK-NEXT: vrgatherei16.vv v10, v8, v12, v0.t398; CHECK-NEXT: vmv.v.v v8, v10399; CHECK-NEXT: ret400 %dst = call <vscale x 16 x i8> @llvm.experimental.vp.reverse.nxv16i8(<vscale x 16 x i8> %src, <vscale x 16 x i1> %mask, i32 %evl)401 ret <vscale x 16 x i8> %dst402}403 404define <vscale x 16 x i8> @test_vp_reverse_nxv16i8(<vscale x 16 x i8> %src, i32 zeroext %evl) {405; CHECK-LABEL: test_vp_reverse_nxv16i8:406; CHECK: # %bb.0:407; CHECK-NEXT: addi a1, a0, -1408; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma409; CHECK-NEXT: vid.v v12410; CHECK-NEXT: vrsub.vx v12, v12, a1411; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma412; CHECK-NEXT: vrgatherei16.vv v10, v8, v12413; CHECK-NEXT: vmv.v.v v8, v10414; CHECK-NEXT: ret415 416 %dst = call <vscale x 16 x i8> @llvm.experimental.vp.reverse.nxv16i8(<vscale x 16 x i8> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)417 ret <vscale x 16 x i8> %dst418}419 420define <vscale x 4 x i64> @test_vp_reverse_nxv4i64_masked(<vscale x 4 x i64> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {421; CHECK-LABEL: test_vp_reverse_nxv4i64_masked:422; CHECK: # %bb.0:423; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma424; CHECK-NEXT: vid.v v12, v0.t425; CHECK-NEXT: addi a0, a0, -1426; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t427; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t428; CHECK-NEXT: vmv.v.v v8, v12429; CHECK-NEXT: ret430 %dst = call <vscale x 4 x i64> @llvm.experimental.vp.reverse.nxv4i64(<vscale x 4 x i64> %src, <vscale x 4 x i1> %mask, i32 %evl)431 ret <vscale x 4 x i64> %dst432}433 434define <vscale x 4 x i64> @test_vp_reverse_nxv4i64(<vscale x 4 x i64> %src, i32 zeroext %evl) {435; CHECK-LABEL: test_vp_reverse_nxv4i64:436; CHECK: # %bb.0:437; CHECK-NEXT: addi a1, a0, -1438; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma439; CHECK-NEXT: vid.v v12440; CHECK-NEXT: vrsub.vx v16, v12, a1441; CHECK-NEXT: vrgather.vv v12, v8, v16442; CHECK-NEXT: vmv.v.v v8, v12443; CHECK-NEXT: ret444 445 %dst = call <vscale x 4 x i64> @llvm.experimental.vp.reverse.nxv4i64(<vscale x 4 x i64> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)446 ret <vscale x 4 x i64> %dst447}448 449define <vscale x 8 x i32> @test_vp_reverse_nxv8i32_masked(<vscale x 8 x i32> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {450; CHECK-LABEL: test_vp_reverse_nxv8i32_masked:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma453; CHECK-NEXT: vid.v v12, v0.t454; CHECK-NEXT: addi a0, a0, -1455; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t456; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t457; CHECK-NEXT: vmv.v.v v8, v12458; CHECK-NEXT: ret459 %dst = call <vscale x 8 x i32> @llvm.experimental.vp.reverse.nxv8i32(<vscale x 8 x i32> %src, <vscale x 8 x i1> %mask, i32 %evl)460 ret <vscale x 8 x i32> %dst461}462 463define <vscale x 8 x i32> @test_vp_reverse_nxv8i32(<vscale x 8 x i32> %src, i32 zeroext %evl) {464; CHECK-LABEL: test_vp_reverse_nxv8i32:465; CHECK: # %bb.0:466; CHECK-NEXT: addi a1, a0, -1467; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma468; CHECK-NEXT: vid.v v12469; CHECK-NEXT: vrsub.vx v16, v12, a1470; CHECK-NEXT: vrgather.vv v12, v8, v16471; CHECK-NEXT: vmv.v.v v8, v12472; CHECK-NEXT: ret473 474 %dst = call <vscale x 8 x i32> @llvm.experimental.vp.reverse.nxv8i32(<vscale x 8 x i32> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)475 ret <vscale x 8 x i32> %dst476}477 478define <vscale x 16 x i16> @test_vp_reverse_nxv16i16_masked(<vscale x 16 x i16> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {479; CHECK-LABEL: test_vp_reverse_nxv16i16_masked:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma482; CHECK-NEXT: vid.v v12, v0.t483; CHECK-NEXT: addi a0, a0, -1484; CHECK-NEXT: vrsub.vx v16, v12, a0, v0.t485; CHECK-NEXT: vrgather.vv v12, v8, v16, v0.t486; CHECK-NEXT: vmv.v.v v8, v12487; CHECK-NEXT: ret488 %dst = call <vscale x 16 x i16> @llvm.experimental.vp.reverse.nxv16i16(<vscale x 16 x i16> %src, <vscale x 16 x i1> %mask, i32 %evl)489 ret <vscale x 16 x i16> %dst490}491 492define <vscale x 16 x i16> @test_vp_reverse_nxv16i16(<vscale x 16 x i16> %src, i32 zeroext %evl) {493; CHECK-LABEL: test_vp_reverse_nxv16i16:494; CHECK: # %bb.0:495; CHECK-NEXT: addi a1, a0, -1496; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma497; CHECK-NEXT: vid.v v12498; CHECK-NEXT: vrsub.vx v16, v12, a1499; CHECK-NEXT: vrgather.vv v12, v8, v16500; CHECK-NEXT: vmv.v.v v8, v12501; CHECK-NEXT: ret502 503 %dst = call <vscale x 16 x i16> @llvm.experimental.vp.reverse.nxv16i16(<vscale x 16 x i16> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)504 ret <vscale x 16 x i16> %dst505}506 507define <vscale x 32 x i8> @test_vp_reverse_nxv32i8_masked(<vscale x 32 x i8> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {508; CHECK-LABEL: test_vp_reverse_nxv32i8_masked:509; CHECK: # %bb.0:510; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma511; CHECK-NEXT: vid.v v16, v0.t512; CHECK-NEXT: addi a0, a0, -1513; CHECK-NEXT: vrsub.vx v16, v16, a0, v0.t514; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma515; CHECK-NEXT: vrgatherei16.vv v12, v8, v16, v0.t516; CHECK-NEXT: vmv.v.v v8, v12517; CHECK-NEXT: ret518 %dst = call <vscale x 32 x i8> @llvm.experimental.vp.reverse.nxv32i8(<vscale x 32 x i8> %src, <vscale x 32 x i1> %mask, i32 %evl)519 ret <vscale x 32 x i8> %dst520}521 522define <vscale x 32 x i8> @test_vp_reverse_nxv32i8(<vscale x 32 x i8> %src, i32 zeroext %evl) {523; CHECK-LABEL: test_vp_reverse_nxv32i8:524; CHECK: # %bb.0:525; CHECK-NEXT: addi a1, a0, -1526; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma527; CHECK-NEXT: vid.v v16528; CHECK-NEXT: vrsub.vx v16, v16, a1529; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma530; CHECK-NEXT: vrgatherei16.vv v12, v8, v16531; CHECK-NEXT: vmv.v.v v8, v12532; CHECK-NEXT: ret533 534 %dst = call <vscale x 32 x i8> @llvm.experimental.vp.reverse.nxv32i8(<vscale x 32 x i8> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)535 ret <vscale x 32 x i8> %dst536}537 538define <vscale x 8 x i64> @test_vp_reverse_nxv8i64_masked(<vscale x 8 x i64> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {539; CHECK-LABEL: test_vp_reverse_nxv8i64_masked:540; CHECK: # %bb.0:541; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma542; CHECK-NEXT: vid.v v16, v0.t543; CHECK-NEXT: addi a0, a0, -1544; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t545; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t546; CHECK-NEXT: vmv.v.v v8, v16547; CHECK-NEXT: ret548 %dst = call <vscale x 8 x i64> @llvm.experimental.vp.reverse.nxv8i64(<vscale x 8 x i64> %src, <vscale x 8 x i1> %mask, i32 %evl)549 ret <vscale x 8 x i64> %dst550}551 552define <vscale x 8 x i64> @test_vp_reverse_nxv8i64(<vscale x 8 x i64> %src, i32 zeroext %evl) {553; CHECK-LABEL: test_vp_reverse_nxv8i64:554; CHECK: # %bb.0:555; CHECK-NEXT: addi a1, a0, -1556; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma557; CHECK-NEXT: vid.v v16558; CHECK-NEXT: vrsub.vx v24, v16, a1559; CHECK-NEXT: vrgather.vv v16, v8, v24560; CHECK-NEXT: vmv.v.v v8, v16561; CHECK-NEXT: ret562 563 %dst = call <vscale x 8 x i64> @llvm.experimental.vp.reverse.nxv8i64(<vscale x 8 x i64> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)564 ret <vscale x 8 x i64> %dst565}566 567define <vscale x 16 x i32> @test_vp_reverse_nxv16i32_masked(<vscale x 16 x i32> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {568; CHECK-LABEL: test_vp_reverse_nxv16i32_masked:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma571; CHECK-NEXT: vid.v v16, v0.t572; CHECK-NEXT: addi a0, a0, -1573; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t574; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t575; CHECK-NEXT: vmv.v.v v8, v16576; CHECK-NEXT: ret577 %dst = call <vscale x 16 x i32> @llvm.experimental.vp.reverse.nxv16i32(<vscale x 16 x i32> %src, <vscale x 16 x i1> %mask, i32 %evl)578 ret <vscale x 16 x i32> %dst579}580 581define <vscale x 16 x i32> @test_vp_reverse_nxv16i32(<vscale x 16 x i32> %src, i32 zeroext %evl) {582; CHECK-LABEL: test_vp_reverse_nxv16i32:583; CHECK: # %bb.0:584; CHECK-NEXT: addi a1, a0, -1585; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma586; CHECK-NEXT: vid.v v16587; CHECK-NEXT: vrsub.vx v24, v16, a1588; CHECK-NEXT: vrgather.vv v16, v8, v24589; CHECK-NEXT: vmv.v.v v8, v16590; CHECK-NEXT: ret591 592 %dst = call <vscale x 16 x i32> @llvm.experimental.vp.reverse.nxv16i32(<vscale x 16 x i32> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)593 ret <vscale x 16 x i32> %dst594}595 596define <vscale x 32 x i16> @test_vp_reverse_nxv32i16_masked(<vscale x 32 x i16> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {597; CHECK-LABEL: test_vp_reverse_nxv32i16_masked:598; CHECK: # %bb.0:599; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma600; CHECK-NEXT: vid.v v16, v0.t601; CHECK-NEXT: addi a0, a0, -1602; CHECK-NEXT: vrsub.vx v24, v16, a0, v0.t603; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t604; CHECK-NEXT: vmv.v.v v8, v16605; CHECK-NEXT: ret606 %dst = call <vscale x 32 x i16> @llvm.experimental.vp.reverse.nxv32i16(<vscale x 32 x i16> %src, <vscale x 32 x i1> %mask, i32 %evl)607 ret <vscale x 32 x i16> %dst608}609 610define <vscale x 32 x i16> @test_vp_reverse_nxv32i16(<vscale x 32 x i16> %src, i32 zeroext %evl) {611; CHECK-LABEL: test_vp_reverse_nxv32i16:612; CHECK: # %bb.0:613; CHECK-NEXT: addi a1, a0, -1614; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma615; CHECK-NEXT: vid.v v16616; CHECK-NEXT: vrsub.vx v24, v16, a1617; CHECK-NEXT: vrgather.vv v16, v8, v24618; CHECK-NEXT: vmv.v.v v8, v16619; CHECK-NEXT: ret620 621 %dst = call <vscale x 32 x i16> @llvm.experimental.vp.reverse.nxv32i16(<vscale x 32 x i16> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)622 ret <vscale x 32 x i16> %dst623}624 625define <vscale x 64 x i8> @test_vp_reverse_nxv64i8_masked(<vscale x 64 x i8> %src, <vscale x 64 x i1> %mask, i32 zeroext %evl) {626; CHECK-LABEL: test_vp_reverse_nxv64i8_masked:627; CHECK: # %bb.0:628; CHECK-NEXT: csrr a1, vlenb629; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma630; CHECK-NEXT: vid.v v16631; CHECK-NEXT: addi a2, a1, -1632; CHECK-NEXT: slli a1, a1, 3633; CHECK-NEXT: vrsub.vx v24, v16, a2634; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma635; CHECK-NEXT: vrgatherei16.vv v23, v8, v24636; CHECK-NEXT: vrgatherei16.vv v22, v9, v24637; CHECK-NEXT: vrgatherei16.vv v21, v10, v24638; CHECK-NEXT: vrgatherei16.vv v20, v11, v24639; CHECK-NEXT: vrgatherei16.vv v19, v12, v24640; CHECK-NEXT: vrgatherei16.vv v18, v13, v24641; CHECK-NEXT: vrgatherei16.vv v17, v14, v24642; CHECK-NEXT: vrgatherei16.vv v16, v15, v24643; CHECK-NEXT: sub a1, a1, a0644; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma645; CHECK-NEXT: vslidedown.vx v8, v16, a1, v0.t646; CHECK-NEXT: ret647 %dst = call <vscale x 64 x i8> @llvm.experimental.vp.reverse.nxv64i8(<vscale x 64 x i8> %src, <vscale x 64 x i1> %mask, i32 %evl)648 ret <vscale x 64 x i8> %dst649}650 651define <vscale x 64 x i8> @test_vp_reverse_nxv64i8(<vscale x 64 x i8> %src, i32 zeroext %evl) {652; CHECK-LABEL: test_vp_reverse_nxv64i8:653; CHECK: # %bb.0:654; CHECK-NEXT: csrr a1, vlenb655; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma656; CHECK-NEXT: vid.v v16657; CHECK-NEXT: addi a2, a1, -1658; CHECK-NEXT: slli a1, a1, 3659; CHECK-NEXT: vrsub.vx v24, v16, a2660; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma661; CHECK-NEXT: vrgatherei16.vv v23, v8, v24662; CHECK-NEXT: vrgatherei16.vv v22, v9, v24663; CHECK-NEXT: vrgatherei16.vv v21, v10, v24664; CHECK-NEXT: vrgatherei16.vv v20, v11, v24665; CHECK-NEXT: vrgatherei16.vv v19, v12, v24666; CHECK-NEXT: vrgatherei16.vv v18, v13, v24667; CHECK-NEXT: vrgatherei16.vv v17, v14, v24668; CHECK-NEXT: vrgatherei16.vv v16, v15, v24669; CHECK-NEXT: sub a1, a1, a0670; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma671; CHECK-NEXT: vslidedown.vx v8, v16, a1672; CHECK-NEXT: ret673 674 %dst = call <vscale x 64 x i8> @llvm.experimental.vp.reverse.nxv64i8(<vscale x 64 x i8> %src, <vscale x 64 x i1> splat (i1 1), i32 %evl)675 ret <vscale x 64 x i8> %dst676}677 678define <vscale x 128 x i8> @test_vp_reverse_nxv128i8(<vscale x 128 x i8> %src, i32 zeroext %evl) {679; CHECK-LABEL: test_vp_reverse_nxv128i8:680; CHECK: # %bb.0:681; CHECK-NEXT: csrr a2, vlenb682; CHECK-NEXT: slli a2, a2, 3683; CHECK-NEXT: mv a1, a0684; CHECK-NEXT: bltu a0, a2, .LBB44_2685; CHECK-NEXT: # %bb.1:686; CHECK-NEXT: mv a1, a2687; CHECK-NEXT: .LBB44_2:688; CHECK-NEXT: addi sp, sp, -80689; CHECK-NEXT: .cfi_def_cfa_offset 80690; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill691; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill692; CHECK-NEXT: .cfi_offset ra, -8693; CHECK-NEXT: .cfi_offset s0, -16694; CHECK-NEXT: addi s0, sp, 80695; CHECK-NEXT: .cfi_def_cfa s0, 0696; CHECK-NEXT: csrr a3, vlenb697; CHECK-NEXT: slli a3, a3, 4698; CHECK-NEXT: sub sp, sp, a3699; CHECK-NEXT: andi sp, sp, -64700; CHECK-NEXT: addi a3, sp, 64701; CHECK-NEXT: li a4, -1702; CHECK-NEXT: sub a5, a0, a2703; CHECK-NEXT: add a6, a0, a3704; CHECK-NEXT: sltu a0, a0, a5705; CHECK-NEXT: add a2, a3, a2706; CHECK-NEXT: addi a6, a6, -1707; CHECK-NEXT: addi a0, a0, -1708; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma709; CHECK-NEXT: vsse8.v v8, (a6), a4710; CHECK-NEXT: sub a6, a6, a1711; CHECK-NEXT: and a0, a0, a5712; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma713; CHECK-NEXT: vsse8.v v16, (a6), a4714; CHECK-NEXT: vle8.v v16, (a2)715; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma716; CHECK-NEXT: vle8.v v8, (a3)717; CHECK-NEXT: addi sp, s0, -80718; CHECK-NEXT: .cfi_def_cfa sp, 80719; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload720; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload721; CHECK-NEXT: .cfi_restore ra722; CHECK-NEXT: .cfi_restore s0723; CHECK-NEXT: addi sp, sp, 80724; CHECK-NEXT: .cfi_def_cfa_offset 0725; CHECK-NEXT: ret726 727 %dst = call <vscale x 128 x i8> @llvm.experimental.vp.reverse.nxv128i8(<vscale x 128 x i8> %src, <vscale x 128 x i1> splat (i1 1), i32 %evl)728 ret <vscale x 128 x i8> %dst729}730