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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 \3; RUN: < %s | FileCheck %s4 5define <2 x i1> @test_vp_reverse_v2i1_masked(<2 x i1> %src, <2 x i1> %mask, i32 zeroext %evl) {6; CHECK-LABEL: test_vp_reverse_v2i1_masked:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma9; CHECK-NEXT: vmv.v.i v9, 010; CHECK-NEXT: addi a0, a0, -111; CHECK-NEXT: vmerge.vim v9, v9, 1, v012; CHECK-NEXT: vmv1r.v v0, v813; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma14; CHECK-NEXT: vid.v v10, v0.t15; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t16; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma17; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t18; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t19; CHECK-NEXT: ret20 %dst = call <2 x i1> @llvm.experimental.vp.reverse.v2i1(<2 x i1> %src, <2 x i1> %mask, i32 %evl)21 ret <2 x i1> %dst22}23 24define <2 x i1> @test_vp_reverse_v2i1(<2 x i1> %src, i32 zeroext %evl) {25; CHECK-LABEL: test_vp_reverse_v2i1:26; CHECK: # %bb.0:27; CHECK-NEXT: addi a1, a0, -128; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma29; CHECK-NEXT: vid.v v830; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma31; CHECK-NEXT: vmv.v.i v9, 032; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma33; CHECK-NEXT: vrsub.vx v8, v8, a134; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma35; CHECK-NEXT: vmerge.vim v9, v9, 1, v036; CHECK-NEXT: vrgatherei16.vv v10, v9, v837; CHECK-NEXT: vmsne.vi v0, v10, 038; CHECK-NEXT: ret39 40 %dst = call <2 x i1> @llvm.experimental.vp.reverse.v2i1(<2 x i1> %src, <2 x i1> splat (i1 1), i32 %evl)41 ret <2 x i1> %dst42}43 44define <4 x i1> @test_vp_reverse_v4i1_masked(<4 x i1> %src, <4 x i1> %mask, i32 zeroext %evl) {45; CHECK-LABEL: test_vp_reverse_v4i1_masked:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma48; CHECK-NEXT: vmv.v.i v9, 049; CHECK-NEXT: addi a0, a0, -150; CHECK-NEXT: vmerge.vim v9, v9, 1, v051; CHECK-NEXT: vmv1r.v v0, v852; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma53; CHECK-NEXT: vid.v v10, v0.t54; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t55; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma56; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t57; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t58; CHECK-NEXT: ret59 %dst = call <4 x i1> @llvm.experimental.vp.reverse.v4i1(<4 x i1> %src, <4 x i1> %mask, i32 %evl)60 ret <4 x i1> %dst61}62 63define <4 x i1> @test_vp_reverse_v4i1(<4 x i1> %src, i32 zeroext %evl) {64; CHECK-LABEL: test_vp_reverse_v4i1:65; CHECK: # %bb.0:66; CHECK-NEXT: addi a1, a0, -167; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma68; CHECK-NEXT: vid.v v869; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma70; CHECK-NEXT: vmv.v.i v9, 071; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma72; CHECK-NEXT: vrsub.vx v8, v8, a173; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma74; CHECK-NEXT: vmerge.vim v9, v9, 1, v075; CHECK-NEXT: vrgatherei16.vv v10, v9, v876; CHECK-NEXT: vmsne.vi v0, v10, 077; CHECK-NEXT: ret78 79 %dst = call <4 x i1> @llvm.experimental.vp.reverse.v4i1(<4 x i1> %src, <4 x i1> splat (i1 1), i32 %evl)80 ret <4 x i1> %dst81}82 83define <8 x i1> @test_vp_reverse_v8i1_masked(<8 x i1> %src, <8 x i1> %mask, i32 zeroext %evl) {84; CHECK-LABEL: test_vp_reverse_v8i1_masked:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma87; CHECK-NEXT: vmv.v.i v9, 088; CHECK-NEXT: addi a0, a0, -189; CHECK-NEXT: vmerge.vim v9, v9, 1, v090; CHECK-NEXT: vmv1r.v v0, v891; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma92; CHECK-NEXT: vid.v v10, v0.t93; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t94; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma95; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t96; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t97; CHECK-NEXT: ret98 %dst = call <8 x i1> @llvm.experimental.vp.reverse.v8i1(<8 x i1> %src, <8 x i1> %mask, i32 %evl)99 ret <8 x i1> %dst100}101 102define <8 x i1> @test_vp_reverse_v8i1(<8 x i1> %src, i32 zeroext %evl) {103; CHECK-LABEL: test_vp_reverse_v8i1:104; CHECK: # %bb.0:105; CHECK-NEXT: addi a1, a0, -1106; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma107; CHECK-NEXT: vid.v v8108; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma109; CHECK-NEXT: vmv.v.i v9, 0110; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma111; CHECK-NEXT: vrsub.vx v8, v8, a1112; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma113; CHECK-NEXT: vmerge.vim v9, v9, 1, v0114; CHECK-NEXT: vrgatherei16.vv v10, v9, v8115; CHECK-NEXT: vmsne.vi v0, v10, 0116; CHECK-NEXT: ret117 118 %dst = call <8 x i1> @llvm.experimental.vp.reverse.v8i1(<8 x i1> %src, <8 x i1> splat (i1 1), i32 %evl)119 ret <8 x i1> %dst120}121 122define <16 x i1> @test_vp_reverse_v16i1_masked(<16 x i1> %src, <16 x i1> %mask, i32 zeroext %evl) {123; CHECK-LABEL: test_vp_reverse_v16i1_masked:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma126; CHECK-NEXT: vmv.v.i v9, 0127; CHECK-NEXT: addi a0, a0, -1128; CHECK-NEXT: vmerge.vim v9, v9, 1, v0129; CHECK-NEXT: vmv1r.v v0, v8130; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma131; CHECK-NEXT: vid.v v10, v0.t132; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t133; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma134; CHECK-NEXT: vrgatherei16.vv v12, v9, v10, v0.t135; CHECK-NEXT: vmsne.vi v0, v12, 0, v0.t136; CHECK-NEXT: ret137 %dst = call <16 x i1> @llvm.experimental.vp.reverse.v16i1(<16 x i1> %src, <16 x i1> %mask, i32 %evl)138 ret <16 x i1> %dst139}140 141define <16 x i1> @test_vp_reverse_v16i1(<16 x i1> %src, i32 zeroext %evl) {142; CHECK-LABEL: test_vp_reverse_v16i1:143; CHECK: # %bb.0:144; CHECK-NEXT: addi a1, a0, -1145; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma146; CHECK-NEXT: vid.v v8147; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma148; CHECK-NEXT: vmv.v.i v10, 0149; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma150; CHECK-NEXT: vrsub.vx v8, v8, a1151; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma152; CHECK-NEXT: vmerge.vim v10, v10, 1, v0153; CHECK-NEXT: vrgatherei16.vv v11, v10, v8154; CHECK-NEXT: vmsne.vi v0, v11, 0155; CHECK-NEXT: ret156 157 %dst = call <16 x i1> @llvm.experimental.vp.reverse.v16i1(<16 x i1> %src, <16 x i1> splat (i1 1), i32 %evl)158 ret <16 x i1> %dst159}160 161