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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3 4define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {5; CHECK-LABEL: test_vp_reverse_nxv1i1_masked:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma8; CHECK-NEXT: vmv.v.i v9, 09; CHECK-NEXT: addi a0, a0, -110; CHECK-NEXT: vmerge.vim v9, v9, 1, v011; CHECK-NEXT: vmv1r.v v0, v812; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma13; CHECK-NEXT: vid.v v10, v0.t14; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t15; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma16; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t17; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t18; CHECK-NEXT: ret19 %dst = call <vscale x 1 x i1> @llvm.experimental.vp.reverse.nxv1i1(<vscale x 1 x i1> %src, <vscale x 1 x i1> %mask, i32 %evl)20 ret <vscale x 1 x i1> %dst21}22 23define <vscale x 1 x i1> @test_vp_reverse_nxv1i1(<vscale x 1 x i1> %src, i32 zeroext %evl) {24; CHECK-LABEL: test_vp_reverse_nxv1i1:25; CHECK: # %bb.0:26; CHECK-NEXT: addi a1, a0, -127; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma28; CHECK-NEXT: vid.v v829; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma30; CHECK-NEXT: vmv.v.i v9, 031; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma32; CHECK-NEXT: vrsub.vx v8, v8, a133; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma34; CHECK-NEXT: vmerge.vim v9, v9, 1, v035; CHECK-NEXT: vrgatherei16.vv v10, v9, v836; CHECK-NEXT: vmsne.vi v0, v10, 037; CHECK-NEXT: ret38 39 %dst = call <vscale x 1 x i1> @llvm.experimental.vp.reverse.nxv1i1(<vscale x 1 x i1> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)40 ret <vscale x 1 x i1> %dst41}42 43define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {44; CHECK-LABEL: test_vp_reverse_nxv2i1_masked:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma47; CHECK-NEXT: vmv.v.i v9, 048; CHECK-NEXT: addi a0, a0, -149; CHECK-NEXT: vmerge.vim v9, v9, 1, v050; CHECK-NEXT: vmv1r.v v0, v851; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma52; CHECK-NEXT: vid.v v10, v0.t53; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t54; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma55; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t56; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t57; CHECK-NEXT: ret58 %dst = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %src, <vscale x 2 x i1> %mask, i32 %evl)59 ret <vscale x 2 x i1> %dst60}61 62define <vscale x 2 x i1> @test_vp_reverse_nxv2i1(<vscale x 2 x i1> %src, i32 zeroext %evl) {63; CHECK-LABEL: test_vp_reverse_nxv2i1:64; CHECK: # %bb.0:65; CHECK-NEXT: addi a1, a0, -166; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma67; CHECK-NEXT: vid.v v868; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma69; CHECK-NEXT: vmv.v.i v9, 070; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma71; CHECK-NEXT: vrsub.vx v8, v8, a172; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma73; CHECK-NEXT: vmerge.vim v9, v9, 1, v074; CHECK-NEXT: vrgatherei16.vv v10, v9, v875; CHECK-NEXT: vmsne.vi v0, v10, 076; CHECK-NEXT: ret77 78 %dst = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)79 ret <vscale x 2 x i1> %dst80}81 82define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {83; CHECK-LABEL: test_vp_reverse_nxv4i1_masked:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma86; CHECK-NEXT: vmv.v.i v9, 087; CHECK-NEXT: addi a0, a0, -188; CHECK-NEXT: vmerge.vim v9, v9, 1, v089; CHECK-NEXT: vmv1r.v v0, v890; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma91; CHECK-NEXT: vid.v v10, v0.t92; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t93; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma94; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t95; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t96; CHECK-NEXT: ret97 %dst = call <vscale x 4 x i1> @llvm.experimental.vp.reverse.nxv4i1(<vscale x 4 x i1> %src, <vscale x 4 x i1> %mask, i32 %evl)98 ret <vscale x 4 x i1> %dst99}100 101define <vscale x 4 x i1> @test_vp_reverse_nxv4i1(<vscale x 4 x i1> %src, i32 zeroext %evl) {102; CHECK-LABEL: test_vp_reverse_nxv4i1:103; CHECK: # %bb.0:104; CHECK-NEXT: addi a1, a0, -1105; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma106; CHECK-NEXT: vid.v v8107; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma108; CHECK-NEXT: vmv.v.i v9, 0109; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma110; CHECK-NEXT: vrsub.vx v8, v8, a1111; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma112; CHECK-NEXT: vmerge.vim v9, v9, 1, v0113; CHECK-NEXT: vrgatherei16.vv v10, v9, v8114; CHECK-NEXT: vmsne.vi v0, v10, 0115; CHECK-NEXT: ret116 117 %dst = call <vscale x 4 x i1> @llvm.experimental.vp.reverse.nxv4i1(<vscale x 4 x i1> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)118 ret <vscale x 4 x i1> %dst119}120 121define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {122; CHECK-LABEL: test_vp_reverse_nxv8i1_masked:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma125; CHECK-NEXT: vmv.v.i v9, 0126; CHECK-NEXT: addi a0, a0, -1127; CHECK-NEXT: vmerge.vim v9, v9, 1, v0128; CHECK-NEXT: vmv1r.v v0, v8129; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma130; CHECK-NEXT: vid.v v10, v0.t131; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t132; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma133; CHECK-NEXT: vrgatherei16.vv v12, v9, v10, v0.t134; CHECK-NEXT: vmsne.vi v0, v12, 0, v0.t135; CHECK-NEXT: ret136 %dst = call <vscale x 8 x i1> @llvm.experimental.vp.reverse.nxv8i1(<vscale x 8 x i1> %src, <vscale x 8 x i1> %mask, i32 %evl)137 ret <vscale x 8 x i1> %dst138}139 140define <vscale x 8 x i1> @test_vp_reverse_nxv8i1(<vscale x 8 x i1> %src, i32 zeroext %evl) {141; CHECK-LABEL: test_vp_reverse_nxv8i1:142; CHECK: # %bb.0:143; CHECK-NEXT: addi a1, a0, -1144; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma145; CHECK-NEXT: vid.v v8146; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma147; CHECK-NEXT: vmv.v.i v10, 0148; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma149; CHECK-NEXT: vrsub.vx v8, v8, a1150; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma151; CHECK-NEXT: vmerge.vim v10, v10, 1, v0152; CHECK-NEXT: vrgatherei16.vv v11, v10, v8153; CHECK-NEXT: vmsne.vi v0, v11, 0154; CHECK-NEXT: ret155 156 %dst = call <vscale x 8 x i1> @llvm.experimental.vp.reverse.nxv8i1(<vscale x 8 x i1> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)157 ret <vscale x 8 x i1> %dst158}159 160define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {161; CHECK-LABEL: test_vp_reverse_nxv16i1_masked:162; CHECK: # %bb.0:163; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma164; CHECK-NEXT: vmv.v.i v10, 0165; CHECK-NEXT: addi a0, a0, -1166; CHECK-NEXT: vmerge.vim v10, v10, 1, v0167; CHECK-NEXT: vmv1r.v v0, v8168; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma169; CHECK-NEXT: vid.v v12, v0.t170; CHECK-NEXT: vrsub.vx v12, v12, a0, v0.t171; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma172; CHECK-NEXT: vrgatherei16.vv v16, v10, v12, v0.t173; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t174; CHECK-NEXT: vmv1r.v v0, v8175; CHECK-NEXT: ret176 %dst = call <vscale x 16 x i1> @llvm.experimental.vp.reverse.nxv16i1(<vscale x 16 x i1> %src, <vscale x 16 x i1> %mask, i32 %evl)177 ret <vscale x 16 x i1> %dst178}179 180define <vscale x 16 x i1> @test_vp_reverse_nxv16i1(<vscale x 16 x i1> %src, i32 zeroext %evl) {181; CHECK-LABEL: test_vp_reverse_nxv16i1:182; CHECK: # %bb.0:183; CHECK-NEXT: addi a1, a0, -1184; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma185; CHECK-NEXT: vid.v v8186; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma187; CHECK-NEXT: vmv.v.i v12, 0188; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma189; CHECK-NEXT: vrsub.vx v8, v8, a1190; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma191; CHECK-NEXT: vmerge.vim v12, v12, 1, v0192; CHECK-NEXT: vrgatherei16.vv v14, v12, v8193; CHECK-NEXT: vmsne.vi v0, v14, 0194; CHECK-NEXT: ret195 196 %dst = call <vscale x 16 x i1> @llvm.experimental.vp.reverse.nxv16i1(<vscale x 16 x i1> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)197 ret <vscale x 16 x i1> %dst198}199 200define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {201; CHECK-LABEL: test_vp_reverse_nxv32i1_masked:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma204; CHECK-NEXT: vmv.v.i v12, 0205; CHECK-NEXT: addi a0, a0, -1206; CHECK-NEXT: vmerge.vim v12, v12, 1, v0207; CHECK-NEXT: vmv1r.v v0, v8208; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma209; CHECK-NEXT: vid.v v16, v0.t210; CHECK-NEXT: vrsub.vx v16, v16, a0, v0.t211; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma212; CHECK-NEXT: vrgatherei16.vv v24, v12, v16, v0.t213; CHECK-NEXT: vmsne.vi v8, v24, 0, v0.t214; CHECK-NEXT: vmv1r.v v0, v8215; CHECK-NEXT: ret216 %dst = call <vscale x 32 x i1> @llvm.experimental.vp.reverse.nxv32i1(<vscale x 32 x i1> %src, <vscale x 32 x i1> %mask, i32 %evl)217 ret <vscale x 32 x i1> %dst218}219 220define <vscale x 32 x i1> @test_vp_reverse_nxv32i1(<vscale x 32 x i1> %src, i32 zeroext %evl) {221; CHECK-LABEL: test_vp_reverse_nxv32i1:222; CHECK: # %bb.0:223; CHECK-NEXT: addi a1, a0, -1224; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma225; CHECK-NEXT: vid.v v8226; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma227; CHECK-NEXT: vmv.v.i v16, 0228; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma229; CHECK-NEXT: vrsub.vx v8, v8, a1230; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma231; CHECK-NEXT: vmerge.vim v16, v16, 1, v0232; CHECK-NEXT: vrgatherei16.vv v20, v16, v8233; CHECK-NEXT: vmsne.vi v0, v20, 0234; CHECK-NEXT: ret235 236 %dst = call <vscale x 32 x i1> @llvm.experimental.vp.reverse.nxv32i1(<vscale x 32 x i1> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)237 ret <vscale x 32 x i1> %dst238}239 240define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %src, <vscale x 64 x i1> %mask, i32 zeroext %evl) {241; CHECK-LABEL: test_vp_reverse_nxv64i1_masked:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma244; CHECK-NEXT: vmv.v.i v16, 0245; CHECK-NEXT: csrr a1, vlenb246; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma247; CHECK-NEXT: vid.v v10248; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma249; CHECK-NEXT: vmerge.vim v16, v16, 1, v0250; CHECK-NEXT: addi a2, a1, -1251; CHECK-NEXT: slli a1, a1, 3252; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma253; CHECK-NEXT: vrsub.vx v10, v10, a2254; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma255; CHECK-NEXT: vrgatherei16.vv v31, v16, v10256; CHECK-NEXT: vrgatherei16.vv v30, v17, v10257; CHECK-NEXT: vrgatherei16.vv v29, v18, v10258; CHECK-NEXT: vrgatherei16.vv v28, v19, v10259; CHECK-NEXT: vrgatherei16.vv v27, v20, v10260; CHECK-NEXT: vrgatherei16.vv v26, v21, v10261; CHECK-NEXT: vrgatherei16.vv v25, v22, v10262; CHECK-NEXT: vrgatherei16.vv v24, v23, v10263; CHECK-NEXT: sub a1, a1, a0264; CHECK-NEXT: vmv1r.v v0, v8265; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma266; CHECK-NEXT: vslidedown.vx v16, v24, a1, v0.t267; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t268; CHECK-NEXT: vmv1r.v v0, v8269; CHECK-NEXT: ret270 %dst = call <vscale x 64 x i1> @llvm.experimental.vp.reverse.nxv64i1(<vscale x 64 x i1> %src, <vscale x 64 x i1> %mask, i32 %evl)271 ret <vscale x 64 x i1> %dst272}273 274define <vscale x 64 x i1> @test_vp_reverse_nxv64i1(<vscale x 64 x i1> %src, i32 zeroext %evl) {275; CHECK-LABEL: test_vp_reverse_nxv64i1:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma278; CHECK-NEXT: vmv.v.i v8, 0279; CHECK-NEXT: csrr a1, vlenb280; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma281; CHECK-NEXT: vid.v v16282; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma283; CHECK-NEXT: vmerge.vim v8, v8, 1, v0284; CHECK-NEXT: addi a2, a1, -1285; CHECK-NEXT: slli a1, a1, 3286; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma287; CHECK-NEXT: vrsub.vx v24, v16, a2288; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma289; CHECK-NEXT: vrgatherei16.vv v23, v8, v24290; CHECK-NEXT: vrgatherei16.vv v22, v9, v24291; CHECK-NEXT: vrgatherei16.vv v21, v10, v24292; CHECK-NEXT: vrgatherei16.vv v20, v11, v24293; CHECK-NEXT: vrgatherei16.vv v19, v12, v24294; CHECK-NEXT: vrgatherei16.vv v18, v13, v24295; CHECK-NEXT: vrgatherei16.vv v17, v14, v24296; CHECK-NEXT: vrgatherei16.vv v16, v15, v24297; CHECK-NEXT: sub a1, a1, a0298; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma299; CHECK-NEXT: vslidedown.vx v8, v16, a1300; CHECK-NEXT: vmsne.vi v0, v8, 0301; CHECK-NEXT: ret302 303 %dst = call <vscale x 64 x i1> @llvm.experimental.vp.reverse.nxv64i1(<vscale x 64 x i1> %src, <vscale x 64 x i1> splat (i1 1), i32 %evl)304 ret <vscale x 64 x i1> %dst305}306 307