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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,NOZFMIN,ZVFH3; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,NOZFMIN,ZVFH4; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,NOZFMIN,ZVFHMIN5; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,NOZFMIN,ZVFHMIN6; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfhmin,+zfbfmin,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZFMIN7; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfhmin,+zfbfmin,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZFMIN8; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfhmin,+zvfhmin,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVFBFA9; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfhmin,+zvfhmin,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVFBFA10 11define <vscale x 1 x i8> @vp_splat_nxv1i8(i8 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vp_splat_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma15; CHECK-NEXT: vmv.v.x v8, a016; CHECK-NEXT: ret17 %splat = call <vscale x 1 x i8> @llvm.experimental.vp.splat.nxv1i8(i8 %val, <vscale x 1 x i1> %m, i32 %evl)18 ret <vscale x 1 x i8> %splat19}20 21define <vscale x 2 x i8> @vp_splat_nxv2i8(i8 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: vp_splat_nxv2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma25; CHECK-NEXT: vmv.v.x v8, a026; CHECK-NEXT: ret27 %splat = call <vscale x 2 x i8> @llvm.experimental.vp.splat.nxv2i8(i8 %val, <vscale x 2 x i1> %m, i32 %evl)28 ret <vscale x 2 x i8> %splat29}30 31define <vscale x 4 x i8> @vp_splat_nxv4i8(i8 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {32; CHECK-LABEL: vp_splat_nxv4i8:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma35; CHECK-NEXT: vmv.v.x v8, a036; CHECK-NEXT: ret37 %splat = call <vscale x 4 x i8> @llvm.experimental.vp.splat.nxv4i8(i8 %val, <vscale x 4 x i1> %m, i32 %evl)38 ret <vscale x 4 x i8> %splat39}40 41define <vscale x 8 x i8> @vp_splat_nxv8i8(i8 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vp_splat_nxv8i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma45; CHECK-NEXT: vmv.v.x v8, a046; CHECK-NEXT: ret47 %splat = call <vscale x 8 x i8> @llvm.experimental.vp.splat.nxv8i8(i8 %val, <vscale x 8 x i1> %m, i32 %evl)48 ret <vscale x 8 x i8> %splat49}50 51define <vscale x 16 x i8> @vp_splat_nxv16i8(i8 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vp_splat_nxv16i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma55; CHECK-NEXT: vmv.v.x v8, a056; CHECK-NEXT: ret57 %splat = call <vscale x 16 x i8> @llvm.experimental.vp.splat.nxv16i8(i8 %val, <vscale x 16 x i1> %m, i32 %evl)58 ret <vscale x 16 x i8> %splat59}60 61define <vscale x 32 x i8> @vp_splat_nxv32i8(i8 %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {62; CHECK-LABEL: vp_splat_nxv32i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma65; CHECK-NEXT: vmv.v.x v8, a066; CHECK-NEXT: ret67 %splat = call <vscale x 32 x i8> @llvm.experimental.vp.splat.nxv32i8(i8 %val, <vscale x 32 x i1> %m, i32 %evl)68 ret <vscale x 32 x i8> %splat69}70 71define <vscale x 64 x i8> @vp_splat_nxv64i8(i8 %val, <vscale x 64 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: vp_splat_nxv64i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma75; CHECK-NEXT: vmv.v.x v8, a076; CHECK-NEXT: ret77 %splat = call <vscale x 64 x i8> @llvm.experimental.vp.splat.nxv64i8(i8 %val, <vscale x 64 x i1> %m, i32 %evl)78 ret <vscale x 64 x i8> %splat79}80 81define <vscale x 1 x i16> @vp_splat_nxv1i16(i16 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {82; CHECK-LABEL: vp_splat_nxv1i16:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma85; CHECK-NEXT: vmv.v.x v8, a086; CHECK-NEXT: ret87 %splat = call <vscale x 1 x i16> @llvm.experimental.vp.splat.nxv1i16(i16 %val, <vscale x 1 x i1> %m, i32 %evl)88 ret <vscale x 1 x i16> %splat89}90 91define <vscale x 2 x i16> @vp_splat_nxv2i16(i16 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: vp_splat_nxv2i16:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma95; CHECK-NEXT: vmv.v.x v8, a096; CHECK-NEXT: ret97 %splat = call <vscale x 2 x i16> @llvm.experimental.vp.splat.nxv2i16(i16 %val, <vscale x 2 x i1> %m, i32 %evl)98 ret <vscale x 2 x i16> %splat99}100 101define <vscale x 4 x i16> @vp_splat_nxv4i16(i16 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: vp_splat_nxv4i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma105; CHECK-NEXT: vmv.v.x v8, a0106; CHECK-NEXT: ret107 %splat = call <vscale x 4 x i16> @llvm.experimental.vp.splat.nxv4i16(i16 %val, <vscale x 4 x i1> %m, i32 %evl)108 ret <vscale x 4 x i16> %splat109}110 111define <vscale x 8 x i16> @vp_splat_nxv8i16(i16 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vp_splat_nxv8i16:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma115; CHECK-NEXT: vmv.v.x v8, a0116; CHECK-NEXT: ret117 %splat = call <vscale x 8 x i16> @llvm.experimental.vp.splat.nxv8i16(i16 %val, <vscale x 8 x i1> %m, i32 %evl)118 ret <vscale x 8 x i16> %splat119}120 121define <vscale x 16 x i16> @vp_splat_nxv16i16(i16 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vp_splat_nxv16i16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma125; CHECK-NEXT: vmv.v.x v8, a0126; CHECK-NEXT: ret127 %splat = call <vscale x 16 x i16> @llvm.experimental.vp.splat.nxv16i16(i16 %val, <vscale x 16 x i1> %m, i32 %evl)128 ret <vscale x 16 x i16> %splat129}130 131define <vscale x 32 x i16> @vp_splat_nxv32i16(i16 %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {132; CHECK-LABEL: vp_splat_nxv32i16:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma135; CHECK-NEXT: vmv.v.x v8, a0136; CHECK-NEXT: ret137 %splat = call <vscale x 32 x i16> @llvm.experimental.vp.splat.nxv32i16(i16 %val, <vscale x 32 x i1> %m, i32 %evl)138 ret <vscale x 32 x i16> %splat139}140 141define <vscale x 1 x i32> @vp_splat_nxv1i32(i32 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {142; CHECK-LABEL: vp_splat_nxv1i32:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma145; CHECK-NEXT: vmv.v.x v8, a0146; CHECK-NEXT: ret147 %splat = call <vscale x 1 x i32> @llvm.experimental.vp.splat.nxv1i32(i32 %val, <vscale x 1 x i1> %m, i32 %evl)148 ret <vscale x 1 x i32> %splat149}150 151define <vscale x 2 x i32> @vp_splat_nxv2i32(i32 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {152; CHECK-LABEL: vp_splat_nxv2i32:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma155; CHECK-NEXT: vmv.v.x v8, a0156; CHECK-NEXT: ret157 %splat = call <vscale x 2 x i32> @llvm.experimental.vp.splat.nxv2i32(i32 %val, <vscale x 2 x i1> %m, i32 %evl)158 ret <vscale x 2 x i32> %splat159}160 161define <vscale x 4 x i32> @vp_splat_nxv4i32(i32 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: vp_splat_nxv4i32:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma165; CHECK-NEXT: vmv.v.x v8, a0166; CHECK-NEXT: ret167 %splat = call <vscale x 4 x i32> @llvm.experimental.vp.splat.nxv4i32(i32 %val, <vscale x 4 x i1> %m, i32 %evl)168 ret <vscale x 4 x i32> %splat169}170 171define <vscale x 8 x i32> @vp_splat_nxv8i32(i32 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: vp_splat_nxv8i32:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma175; CHECK-NEXT: vmv.v.x v8, a0176; CHECK-NEXT: ret177 %splat = call <vscale x 8 x i32> @llvm.experimental.vp.splat.nxv8i32(i32 %val, <vscale x 8 x i1> %m, i32 %evl)178 ret <vscale x 8 x i32> %splat179}180 181define <vscale x 16 x i32> @vp_splat_nxv16i32(i32 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {182; CHECK-LABEL: vp_splat_nxv16i32:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma185; CHECK-NEXT: vmv.v.x v8, a0186; CHECK-NEXT: ret187 %splat = call <vscale x 16 x i32> @llvm.experimental.vp.splat.nxv16i32(i32 %val, <vscale x 16 x i1> %m, i32 %evl)188 ret <vscale x 16 x i32> %splat189}190 191define <vscale x 1 x i64> @vp_splat_nxv1i64(i64 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {192; RV32-LABEL: vp_splat_nxv1i64:193; RV32: # %bb.0:194; RV32-NEXT: addi sp, sp, -16195; RV32-NEXT: .cfi_def_cfa_offset 16196; RV32-NEXT: sw a0, 8(sp)197; RV32-NEXT: sw a1, 12(sp)198; RV32-NEXT: addi a0, sp, 8199; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma200; RV32-NEXT: vlse64.v v8, (a0), zero201; RV32-NEXT: addi sp, sp, 16202; RV32-NEXT: .cfi_def_cfa_offset 0203; RV32-NEXT: ret204;205; RV64-LABEL: vp_splat_nxv1i64:206; RV64: # %bb.0:207; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma208; RV64-NEXT: vmv.v.x v8, a0209; RV64-NEXT: ret210 %splat = call <vscale x 1 x i64> @llvm.experimental.vp.splat.nxv1i64(i64 %val, <vscale x 1 x i1> %m, i32 %evl)211 ret <vscale x 1 x i64> %splat212}213 214define <vscale x 2 x i64> @vp_splat_nxv2i64(i64 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {215; RV32-LABEL: vp_splat_nxv2i64:216; RV32: # %bb.0:217; RV32-NEXT: addi sp, sp, -16218; RV32-NEXT: .cfi_def_cfa_offset 16219; RV32-NEXT: sw a0, 8(sp)220; RV32-NEXT: sw a1, 12(sp)221; RV32-NEXT: addi a0, sp, 8222; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma223; RV32-NEXT: vlse64.v v8, (a0), zero224; RV32-NEXT: addi sp, sp, 16225; RV32-NEXT: .cfi_def_cfa_offset 0226; RV32-NEXT: ret227;228; RV64-LABEL: vp_splat_nxv2i64:229; RV64: # %bb.0:230; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma231; RV64-NEXT: vmv.v.x v8, a0232; RV64-NEXT: ret233 %splat = call <vscale x 2 x i64> @llvm.experimental.vp.splat.nxv2i64(i64 %val, <vscale x 2 x i1> %m, i32 %evl)234 ret <vscale x 2 x i64> %splat235}236 237define <vscale x 4 x i64> @vp_splat_nxv4i64(i64 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {238; RV32-LABEL: vp_splat_nxv4i64:239; RV32: # %bb.0:240; RV32-NEXT: addi sp, sp, -16241; RV32-NEXT: .cfi_def_cfa_offset 16242; RV32-NEXT: sw a0, 8(sp)243; RV32-NEXT: sw a1, 12(sp)244; RV32-NEXT: addi a0, sp, 8245; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma246; RV32-NEXT: vlse64.v v8, (a0), zero247; RV32-NEXT: addi sp, sp, 16248; RV32-NEXT: .cfi_def_cfa_offset 0249; RV32-NEXT: ret250;251; RV64-LABEL: vp_splat_nxv4i64:252; RV64: # %bb.0:253; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma254; RV64-NEXT: vmv.v.x v8, a0255; RV64-NEXT: ret256 %splat = call <vscale x 4 x i64> @llvm.experimental.vp.splat.nxv4i64(i64 %val, <vscale x 4 x i1> %m, i32 %evl)257 ret <vscale x 4 x i64> %splat258}259 260define <vscale x 8 x i64> @vp_splat_nxv8i64(i64 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {261; RV32-LABEL: vp_splat_nxv8i64:262; RV32: # %bb.0:263; RV32-NEXT: addi sp, sp, -16264; RV32-NEXT: .cfi_def_cfa_offset 16265; RV32-NEXT: sw a0, 8(sp)266; RV32-NEXT: sw a1, 12(sp)267; RV32-NEXT: addi a0, sp, 8268; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma269; RV32-NEXT: vlse64.v v8, (a0), zero270; RV32-NEXT: addi sp, sp, 16271; RV32-NEXT: .cfi_def_cfa_offset 0272; RV32-NEXT: ret273;274; RV64-LABEL: vp_splat_nxv8i64:275; RV64: # %bb.0:276; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma277; RV64-NEXT: vmv.v.x v8, a0278; RV64-NEXT: ret279 %splat = call <vscale x 8 x i64> @llvm.experimental.vp.splat.nxv8i64(i64 %val, <vscale x 8 x i1> %m, i32 %evl)280 ret <vscale x 8 x i64> %splat281}282 283define <vscale x 1 x bfloat> @vp_splat_nxv1bf16(bfloat %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {284; NOZFMIN-LABEL: vp_splat_nxv1bf16:285; NOZFMIN: # %bb.0:286; NOZFMIN-NEXT: fmv.x.w a1, fa0287; NOZFMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma288; NOZFMIN-NEXT: vmv.v.x v8, a1289; NOZFMIN-NEXT: ret290;291; ZFMIN-LABEL: vp_splat_nxv1bf16:292; ZFMIN: # %bb.0:293; ZFMIN-NEXT: fmv.x.h a1, fa0294; ZFMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma295; ZFMIN-NEXT: vmv.v.x v8, a1296; ZFMIN-NEXT: ret297;298; ZVFBFA-LABEL: vp_splat_nxv1bf16:299; ZVFBFA: # %bb.0:300; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma301; ZVFBFA-NEXT: vfmv.v.f v8, fa0302; ZVFBFA-NEXT: ret303 %splat = call <vscale x 1 x bfloat> @llvm.experimental.vp.splat.nxv1bf16(bfloat %val, <vscale x 1 x i1> %m, i32 %evl)304 ret <vscale x 1 x bfloat> %splat305}306 307define <vscale x 2 x bfloat> @vp_splat_nxv2bf16(bfloat %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {308; NOZFMIN-LABEL: vp_splat_nxv2bf16:309; NOZFMIN: # %bb.0:310; NOZFMIN-NEXT: fmv.x.w a1, fa0311; NOZFMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma312; NOZFMIN-NEXT: vmv.v.x v8, a1313; NOZFMIN-NEXT: ret314;315; ZFMIN-LABEL: vp_splat_nxv2bf16:316; ZFMIN: # %bb.0:317; ZFMIN-NEXT: fmv.x.h a1, fa0318; ZFMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma319; ZFMIN-NEXT: vmv.v.x v8, a1320; ZFMIN-NEXT: ret321;322; ZVFBFA-LABEL: vp_splat_nxv2bf16:323; ZVFBFA: # %bb.0:324; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma325; ZVFBFA-NEXT: vfmv.v.f v8, fa0326; ZVFBFA-NEXT: ret327 %splat = call <vscale x 2 x bfloat> @llvm.experimental.vp.splat.nxv2bf16(bfloat %val, <vscale x 2 x i1> %m, i32 %evl)328 ret <vscale x 2 x bfloat> %splat329}330 331define <vscale x 4 x bfloat> @vp_splat_nxv4bf16(bfloat %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {332; NOZFMIN-LABEL: vp_splat_nxv4bf16:333; NOZFMIN: # %bb.0:334; NOZFMIN-NEXT: fmv.x.w a1, fa0335; NOZFMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma336; NOZFMIN-NEXT: vmv.v.x v8, a1337; NOZFMIN-NEXT: ret338;339; ZFMIN-LABEL: vp_splat_nxv4bf16:340; ZFMIN: # %bb.0:341; ZFMIN-NEXT: fmv.x.h a1, fa0342; ZFMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma343; ZFMIN-NEXT: vmv.v.x v8, a1344; ZFMIN-NEXT: ret345;346; ZVFBFA-LABEL: vp_splat_nxv4bf16:347; ZVFBFA: # %bb.0:348; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma349; ZVFBFA-NEXT: vfmv.v.f v8, fa0350; ZVFBFA-NEXT: ret351 %splat = call <vscale x 4 x bfloat> @llvm.experimental.vp.splat.nxv4bf16(bfloat %val, <vscale x 4 x i1> %m, i32 %evl)352 ret <vscale x 4 x bfloat> %splat353}354 355define <vscale x 8 x bfloat> @vp_splat_nxv8bf16(bfloat %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {356; NOZFMIN-LABEL: vp_splat_nxv8bf16:357; NOZFMIN: # %bb.0:358; NOZFMIN-NEXT: fmv.x.w a1, fa0359; NOZFMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma360; NOZFMIN-NEXT: vmv.v.x v8, a1361; NOZFMIN-NEXT: ret362;363; ZFMIN-LABEL: vp_splat_nxv8bf16:364; ZFMIN: # %bb.0:365; ZFMIN-NEXT: fmv.x.h a1, fa0366; ZFMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma367; ZFMIN-NEXT: vmv.v.x v8, a1368; ZFMIN-NEXT: ret369;370; ZVFBFA-LABEL: vp_splat_nxv8bf16:371; ZVFBFA: # %bb.0:372; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma373; ZVFBFA-NEXT: vfmv.v.f v8, fa0374; ZVFBFA-NEXT: ret375 %splat = call <vscale x 8 x bfloat> @llvm.experimental.vp.splat.nxv8bf16(bfloat %val, <vscale x 8 x i1> %m, i32 %evl)376 ret <vscale x 8 x bfloat> %splat377}378 379define <vscale x 16 x bfloat> @vp_splat_nxv16bf16(bfloat %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {380; NOZFMIN-LABEL: vp_splat_nxv16bf16:381; NOZFMIN: # %bb.0:382; NOZFMIN-NEXT: fmv.x.w a1, fa0383; NOZFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma384; NOZFMIN-NEXT: vmv.v.x v8, a1385; NOZFMIN-NEXT: ret386;387; ZFMIN-LABEL: vp_splat_nxv16bf16:388; ZFMIN: # %bb.0:389; ZFMIN-NEXT: fmv.x.h a1, fa0390; ZFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma391; ZFMIN-NEXT: vmv.v.x v8, a1392; ZFMIN-NEXT: ret393;394; ZVFBFA-LABEL: vp_splat_nxv16bf16:395; ZVFBFA: # %bb.0:396; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma397; ZVFBFA-NEXT: vfmv.v.f v8, fa0398; ZVFBFA-NEXT: ret399 %splat = call <vscale x 16 x bfloat> @llvm.experimental.vp.splat.nxv16bf16(bfloat %val, <vscale x 16 x i1> %m, i32 %evl)400 ret <vscale x 16 x bfloat> %splat401}402 403define <vscale x 32 x bfloat> @vp_splat_nxv32bf16(bfloat %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {404; NOZFMIN-LABEL: vp_splat_nxv32bf16:405; NOZFMIN: # %bb.0:406; NOZFMIN-NEXT: fmv.x.w a1, fa0407; NOZFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma408; NOZFMIN-NEXT: vmv.v.x v8, a1409; NOZFMIN-NEXT: ret410;411; ZFMIN-LABEL: vp_splat_nxv32bf16:412; ZFMIN: # %bb.0:413; ZFMIN-NEXT: fmv.x.h a1, fa0414; ZFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma415; ZFMIN-NEXT: vmv.v.x v8, a1416; ZFMIN-NEXT: ret417;418; ZVFBFA-LABEL: vp_splat_nxv32bf16:419; ZVFBFA: # %bb.0:420; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma421; ZVFBFA-NEXT: vfmv.v.f v8, fa0422; ZVFBFA-NEXT: ret423 %splat = call <vscale x 32 x bfloat> @llvm.experimental.vp.splat.nxv32bf16(bfloat %val, <vscale x 32 x i1> %m, i32 %evl)424 ret <vscale x 32 x bfloat> %splat425}426 427define <vscale x 1 x half> @vp_splat_nxv1f16(half %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {428; ZVFH-LABEL: vp_splat_nxv1f16:429; ZVFH: # %bb.0:430; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma431; ZVFH-NEXT: vfmv.v.f v8, fa0432; ZVFH-NEXT: ret433;434; ZVFHMIN-LABEL: vp_splat_nxv1f16:435; ZVFHMIN: # %bb.0:436; ZVFHMIN-NEXT: fmv.x.w a1, fa0437; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma438; ZVFHMIN-NEXT: vmv.v.x v8, a1439; ZVFHMIN-NEXT: ret440;441; ZFMIN-LABEL: vp_splat_nxv1f16:442; ZFMIN: # %bb.0:443; ZFMIN-NEXT: fmv.x.h a1, fa0444; ZFMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma445; ZFMIN-NEXT: vmv.v.x v8, a1446; ZFMIN-NEXT: ret447;448; ZVFBFA-LABEL: vp_splat_nxv1f16:449; ZVFBFA: # %bb.0:450; ZVFBFA-NEXT: fmv.x.h a1, fa0451; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma452; ZVFBFA-NEXT: vmv.v.x v8, a1453; ZVFBFA-NEXT: ret454 %splat = call <vscale x 1 x half> @llvm.experimental.vp.splat.nxv1f16(half %val, <vscale x 1 x i1> %m, i32 %evl)455 ret <vscale x 1 x half> %splat456}457 458define <vscale x 2 x half> @vp_splat_nxv2f16(half %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {459; ZVFH-LABEL: vp_splat_nxv2f16:460; ZVFH: # %bb.0:461; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma462; ZVFH-NEXT: vfmv.v.f v8, fa0463; ZVFH-NEXT: ret464;465; ZVFHMIN-LABEL: vp_splat_nxv2f16:466; ZVFHMIN: # %bb.0:467; ZVFHMIN-NEXT: fmv.x.w a1, fa0468; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma469; ZVFHMIN-NEXT: vmv.v.x v8, a1470; ZVFHMIN-NEXT: ret471;472; ZFMIN-LABEL: vp_splat_nxv2f16:473; ZFMIN: # %bb.0:474; ZFMIN-NEXT: fmv.x.h a1, fa0475; ZFMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma476; ZFMIN-NEXT: vmv.v.x v8, a1477; ZFMIN-NEXT: ret478;479; ZVFBFA-LABEL: vp_splat_nxv2f16:480; ZVFBFA: # %bb.0:481; ZVFBFA-NEXT: fmv.x.h a1, fa0482; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma483; ZVFBFA-NEXT: vmv.v.x v8, a1484; ZVFBFA-NEXT: ret485 %splat = call <vscale x 2 x half> @llvm.experimental.vp.splat.nxv2f16(half %val, <vscale x 2 x i1> %m, i32 %evl)486 ret <vscale x 2 x half> %splat487}488 489define <vscale x 4 x half> @vp_splat_nxv4f16(half %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {490; ZVFH-LABEL: vp_splat_nxv4f16:491; ZVFH: # %bb.0:492; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma493; ZVFH-NEXT: vfmv.v.f v8, fa0494; ZVFH-NEXT: ret495;496; ZVFHMIN-LABEL: vp_splat_nxv4f16:497; ZVFHMIN: # %bb.0:498; ZVFHMIN-NEXT: fmv.x.w a1, fa0499; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma500; ZVFHMIN-NEXT: vmv.v.x v8, a1501; ZVFHMIN-NEXT: ret502;503; ZFMIN-LABEL: vp_splat_nxv4f16:504; ZFMIN: # %bb.0:505; ZFMIN-NEXT: fmv.x.h a1, fa0506; ZFMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma507; ZFMIN-NEXT: vmv.v.x v8, a1508; ZFMIN-NEXT: ret509;510; ZVFBFA-LABEL: vp_splat_nxv4f16:511; ZVFBFA: # %bb.0:512; ZVFBFA-NEXT: fmv.x.h a1, fa0513; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma514; ZVFBFA-NEXT: vmv.v.x v8, a1515; ZVFBFA-NEXT: ret516 %splat = call <vscale x 4 x half> @llvm.experimental.vp.splat.nxv4f16(half %val, <vscale x 4 x i1> %m, i32 %evl)517 ret <vscale x 4 x half> %splat518}519 520define <vscale x 8 x half> @vp_splat_nxv8f16(half %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {521; ZVFH-LABEL: vp_splat_nxv8f16:522; ZVFH: # %bb.0:523; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma524; ZVFH-NEXT: vfmv.v.f v8, fa0525; ZVFH-NEXT: ret526;527; ZVFHMIN-LABEL: vp_splat_nxv8f16:528; ZVFHMIN: # %bb.0:529; ZVFHMIN-NEXT: fmv.x.w a1, fa0530; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma531; ZVFHMIN-NEXT: vmv.v.x v8, a1532; ZVFHMIN-NEXT: ret533;534; ZFMIN-LABEL: vp_splat_nxv8f16:535; ZFMIN: # %bb.0:536; ZFMIN-NEXT: fmv.x.h a1, fa0537; ZFMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma538; ZFMIN-NEXT: vmv.v.x v8, a1539; ZFMIN-NEXT: ret540;541; ZVFBFA-LABEL: vp_splat_nxv8f16:542; ZVFBFA: # %bb.0:543; ZVFBFA-NEXT: fmv.x.h a1, fa0544; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma545; ZVFBFA-NEXT: vmv.v.x v8, a1546; ZVFBFA-NEXT: ret547 %splat = call <vscale x 8 x half> @llvm.experimental.vp.splat.nxv8f16(half %val, <vscale x 8 x i1> %m, i32 %evl)548 ret <vscale x 8 x half> %splat549}550 551define <vscale x 16 x half> @vp_splat_nxv16f16(half %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {552; ZVFH-LABEL: vp_splat_nxv16f16:553; ZVFH: # %bb.0:554; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma555; ZVFH-NEXT: vfmv.v.f v8, fa0556; ZVFH-NEXT: ret557;558; ZVFHMIN-LABEL: vp_splat_nxv16f16:559; ZVFHMIN: # %bb.0:560; ZVFHMIN-NEXT: fmv.x.w a1, fa0561; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma562; ZVFHMIN-NEXT: vmv.v.x v8, a1563; ZVFHMIN-NEXT: ret564;565; ZFMIN-LABEL: vp_splat_nxv16f16:566; ZFMIN: # %bb.0:567; ZFMIN-NEXT: fmv.x.h a1, fa0568; ZFMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma569; ZFMIN-NEXT: vmv.v.x v8, a1570; ZFMIN-NEXT: ret571;572; ZVFBFA-LABEL: vp_splat_nxv16f16:573; ZVFBFA: # %bb.0:574; ZVFBFA-NEXT: fmv.x.h a1, fa0575; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma576; ZVFBFA-NEXT: vmv.v.x v8, a1577; ZVFBFA-NEXT: ret578 %splat = call <vscale x 16 x half> @llvm.experimental.vp.splat.nxv16f16(half %val, <vscale x 16 x i1> %m, i32 %evl)579 ret <vscale x 16 x half> %splat580}581 582define <vscale x 32 x half> @vp_splat_nxv32f16(half %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {583; ZVFH-LABEL: vp_splat_nxv32f16:584; ZVFH: # %bb.0:585; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma586; ZVFH-NEXT: vfmv.v.f v8, fa0587; ZVFH-NEXT: ret588;589; ZVFHMIN-LABEL: vp_splat_nxv32f16:590; ZVFHMIN: # %bb.0:591; ZVFHMIN-NEXT: fmv.x.w a1, fa0592; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma593; ZVFHMIN-NEXT: vmv.v.x v8, a1594; ZVFHMIN-NEXT: ret595;596; ZFMIN-LABEL: vp_splat_nxv32f16:597; ZFMIN: # %bb.0:598; ZFMIN-NEXT: fmv.x.h a1, fa0599; ZFMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma600; ZFMIN-NEXT: vmv.v.x v8, a1601; ZFMIN-NEXT: ret602;603; ZVFBFA-LABEL: vp_splat_nxv32f16:604; ZVFBFA: # %bb.0:605; ZVFBFA-NEXT: fmv.x.h a1, fa0606; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma607; ZVFBFA-NEXT: vmv.v.x v8, a1608; ZVFBFA-NEXT: ret609 %splat = call <vscale x 32 x half> @llvm.experimental.vp.splat.nxv32f16(half %val, <vscale x 32 x i1> %m, i32 %evl)610 ret <vscale x 32 x half> %splat611}612 613define <vscale x 1 x float> @vp_splat_nxv1f32(float %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {614; CHECK-LABEL: vp_splat_nxv1f32:615; CHECK: # %bb.0:616; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma617; CHECK-NEXT: vfmv.v.f v8, fa0618; CHECK-NEXT: ret619 %splat = call <vscale x 1 x float> @llvm.experimental.vp.splat.nxv1f32(float %val, <vscale x 1 x i1> %m, i32 %evl)620 ret <vscale x 1 x float> %splat621}622 623define <vscale x 2 x float> @vp_splat_nxv2f32(float %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {624; CHECK-LABEL: vp_splat_nxv2f32:625; CHECK: # %bb.0:626; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma627; CHECK-NEXT: vfmv.v.f v8, fa0628; CHECK-NEXT: ret629 %splat = call <vscale x 2 x float> @llvm.experimental.vp.splat.nxv2f32(float %val, <vscale x 2 x i1> %m, i32 %evl)630 ret <vscale x 2 x float> %splat631}632 633define <vscale x 4 x float> @vp_splat_nxv4f32(float %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {634; CHECK-LABEL: vp_splat_nxv4f32:635; CHECK: # %bb.0:636; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma637; CHECK-NEXT: vfmv.v.f v8, fa0638; CHECK-NEXT: ret639 %splat = call <vscale x 4 x float> @llvm.experimental.vp.splat.nxv4f32(float %val, <vscale x 4 x i1> %m, i32 %evl)640 ret <vscale x 4 x float> %splat641}642 643define <vscale x 8 x float> @vp_splat_nxv8f32(float %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {644; CHECK-LABEL: vp_splat_nxv8f32:645; CHECK: # %bb.0:646; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma647; CHECK-NEXT: vfmv.v.f v8, fa0648; CHECK-NEXT: ret649 %splat = call <vscale x 8 x float> @llvm.experimental.vp.splat.nxv8f32(float %val, <vscale x 8 x i1> %m, i32 %evl)650 ret <vscale x 8 x float> %splat651}652 653define <vscale x 16 x float> @vp_splat_nxv16f32(float %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {654; CHECK-LABEL: vp_splat_nxv16f32:655; CHECK: # %bb.0:656; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma657; CHECK-NEXT: vfmv.v.f v8, fa0658; CHECK-NEXT: ret659 %splat = call <vscale x 16 x float> @llvm.experimental.vp.splat.nxv16f32(float %val, <vscale x 16 x i1> %m, i32 %evl)660 ret <vscale x 16 x float> %splat661}662 663define <vscale x 1 x double> @vp_splat_nxv1f64(double %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {664; CHECK-LABEL: vp_splat_nxv1f64:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma667; CHECK-NEXT: vfmv.v.f v8, fa0668; CHECK-NEXT: ret669 %splat = call <vscale x 1 x double> @llvm.experimental.vp.splat.nxv1f64(double %val, <vscale x 1 x i1> %m, i32 %evl)670 ret <vscale x 1 x double> %splat671}672 673define <vscale x 2 x double> @vp_splat_nxv2f64(double %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {674; CHECK-LABEL: vp_splat_nxv2f64:675; CHECK: # %bb.0:676; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma677; CHECK-NEXT: vfmv.v.f v8, fa0678; CHECK-NEXT: ret679 %splat = call <vscale x 2 x double> @llvm.experimental.vp.splat.nxv2f64(double %val, <vscale x 2 x i1> %m, i32 %evl)680 ret <vscale x 2 x double> %splat681}682 683define <vscale x 4 x double> @vp_splat_nxv4f64(double %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {684; CHECK-LABEL: vp_splat_nxv4f64:685; CHECK: # %bb.0:686; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma687; CHECK-NEXT: vfmv.v.f v8, fa0688; CHECK-NEXT: ret689 %splat = call <vscale x 4 x double> @llvm.experimental.vp.splat.nxv4f64(double %val, <vscale x 4 x i1> %m, i32 %evl)690 ret <vscale x 4 x double> %splat691}692 693define <vscale x 8 x double> @vp_splat_nxv8f64(double %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {694; CHECK-LABEL: vp_splat_nxv8f64:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma697; CHECK-NEXT: vfmv.v.f v8, fa0698; CHECK-NEXT: ret699 %splat = call <vscale x 8 x double> @llvm.experimental.vp.splat.nxv8f64(double %val, <vscale x 8 x i1> %m, i32 %evl)700 ret <vscale x 8 x double> %splat701}702 703define <vscale x 16 x i31> @vp_splat_nxv16i31(i31 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {704; CHECK-LABEL: vp_splat_nxv16i31:705; CHECK: # %bb.0:706; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma707; CHECK-NEXT: vmv.v.x v8, a0708; CHECK-NEXT: ret709 %splat = call <vscale x 16 x i31> @llvm.experimental.vp.splat.nxv16i31(i31 %val, <vscale x 16 x i1> %m, i32 %evl)710 ret <vscale x 16 x i31> %splat711}712 713define <vscale x 15 x i32> @vp_splat_nxv15i32(i32 %val, <vscale x 15 x i1> %m, i32 zeroext %evl) {714; CHECK-LABEL: vp_splat_nxv15i32:715; CHECK: # %bb.0:716; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma717; CHECK-NEXT: vmv.v.x v8, a0718; CHECK-NEXT: ret719 %splat = call <vscale x 15 x i32> @llvm.experimental.vp.splat.nxv15i32(i32 %val, <vscale x 15 x i1> %m, i32 %evl)720 ret <vscale x 15 x i32> %splat721}722 723; Split case.724define <vscale x 32 x i32> @vp_splat_nxv32i32(i32 %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {725; CHECK-LABEL: vp_splat_nxv32i32:726; CHECK: # %bb.0:727; CHECK-NEXT: csrr a2, vlenb728; CHECK-NEXT: slli a2, a2, 1729; CHECK-NEXT: sub a3, a1, a2730; CHECK-NEXT: sltu a4, a1, a3731; CHECK-NEXT: addi a4, a4, -1732; CHECK-NEXT: and a3, a4, a3733; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma734; CHECK-NEXT: vmv.v.x v16, a0735; CHECK-NEXT: bltu a1, a2, .LBB45_2736; CHECK-NEXT: # %bb.1:737; CHECK-NEXT: mv a1, a2738; CHECK-NEXT: .LBB45_2:739; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma740; CHECK-NEXT: vmv.v.x v8, a0741; CHECK-NEXT: ret742 %splat = call <vscale x 32 x i32> @llvm.experimental.vp.splat.nxv32i32(i32 %val, <vscale x 32 x i1> %m, i32 %evl)743 ret <vscale x 32 x i32> %splat744}745