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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfh,+zvfbfmin \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFH4; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFHMIN6; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfh,+zvfbfmin,+vl-dependent-latency \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFH8; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin,+vl-dependent-latency \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFHMIN10 11define <vscale x 2 x i64> @test_vp_splice_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {12; NOVLDEP-LABEL: test_vp_splice_nxv2i64:13; NOVLDEP: # %bb.0:14; NOVLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, ma15; NOVLDEP-NEXT: vslidedown.vi v8, v8, 316; NOVLDEP-NEXT: addi a0, a0, -317; NOVLDEP-NEXT: vslideup.vx v8, v10, a018; NOVLDEP-NEXT: ret19;20; VLDEP-LABEL: test_vp_splice_nxv2i64:21; VLDEP: # %bb.0:22; VLDEP-NEXT: addi a0, a0, -323; VLDEP-NEXT: vsetvli zero, a0, e64, m2, ta, ma24; VLDEP-NEXT: vslidedown.vi v8, v8, 325; VLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, ma26; VLDEP-NEXT: vslideup.vx v8, v10, a027; VLDEP-NEXT: ret28 %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)29 ret <vscale x 2 x i64> %v30}31 32define <vscale x 2 x i64> @test_vp_splice_nxv2i64_negative_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {33; NOVLDEP-LABEL: test_vp_splice_nxv2i64_negative_offset:34; NOVLDEP: # %bb.0:35; NOVLDEP-NEXT: addi a0, a0, -336; NOVLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, ma37; NOVLDEP-NEXT: vslidedown.vx v8, v8, a038; NOVLDEP-NEXT: vslideup.vi v8, v10, 339; NOVLDEP-NEXT: ret40;41; VLDEP-LABEL: test_vp_splice_nxv2i64_negative_offset:42; VLDEP: # %bb.0:43; VLDEP-NEXT: addi a0, a0, -344; VLDEP-NEXT: vsetivli zero, 3, e64, m2, ta, ma45; VLDEP-NEXT: vslidedown.vx v8, v8, a046; VLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, ma47; VLDEP-NEXT: vslideup.vi v8, v10, 348; VLDEP-NEXT: ret49 %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)50 ret <vscale x 2 x i64> %v51}52 53define <vscale x 2 x i64> @test_vp_splice_nxv2i64_zero_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {54; CHECK-LABEL: test_vp_splice_nxv2i64_zero_offset:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma57; CHECK-NEXT: vslideup.vx v8, v10, a058; CHECK-NEXT: ret59 %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 0, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)60 ret <vscale x 2 x i64> %v61}62 63define <vscale x 2 x i64> @test_vp_splice_nxv2i64_masked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {64; NOVLDEP-LABEL: test_vp_splice_nxv2i64_masked:65; NOVLDEP: # %bb.0:66; NOVLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, ma67; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t68; NOVLDEP-NEXT: addi a0, a0, -369; NOVLDEP-NEXT: vsetvli zero, zero, e64, m2, ta, mu70; NOVLDEP-NEXT: vslideup.vx v8, v10, a0, v0.t71; NOVLDEP-NEXT: ret72;73; VLDEP-LABEL: test_vp_splice_nxv2i64_masked:74; VLDEP: # %bb.0:75; VLDEP-NEXT: addi a0, a0, -376; VLDEP-NEXT: vsetvli zero, a0, e64, m2, ta, ma77; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t78; VLDEP-NEXT: vsetvli zero, a1, e64, m2, ta, mu79; VLDEP-NEXT: vslideup.vx v8, v10, a0, v0.t80; VLDEP-NEXT: ret81 %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)82 ret <vscale x 2 x i64> %v83}84 85define <vscale x 1 x i64> @test_vp_splice_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {86; NOVLDEP-LABEL: test_vp_splice_nxv1i64:87; NOVLDEP: # %bb.0:88; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma89; NOVLDEP-NEXT: vslidedown.vi v8, v8, 190; NOVLDEP-NEXT: addi a0, a0, -191; NOVLDEP-NEXT: vslideup.vx v8, v9, a092; NOVLDEP-NEXT: ret93;94; VLDEP-LABEL: test_vp_splice_nxv1i64:95; VLDEP: # %bb.0:96; VLDEP-NEXT: addi a0, a0, -197; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma98; VLDEP-NEXT: vslidedown.vi v8, v8, 199; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma100; VLDEP-NEXT: vslideup.vx v8, v9, a0101; VLDEP-NEXT: ret102 %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 1, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)103 ret <vscale x 1 x i64> %v104}105 106define <vscale x 1 x i64> @test_vp_splice_nxv1i64_negative_offset(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {107; NOVLDEP-LABEL: test_vp_splice_nxv1i64_negative_offset:108; NOVLDEP: # %bb.0:109; NOVLDEP-NEXT: addi a0, a0, -2110; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma111; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0112; NOVLDEP-NEXT: vslideup.vi v8, v9, 2113; NOVLDEP-NEXT: ret114;115; VLDEP-LABEL: test_vp_splice_nxv1i64_negative_offset:116; VLDEP: # %bb.0:117; VLDEP-NEXT: addi a0, a0, -2118; VLDEP-NEXT: vsetivli zero, 2, e64, m1, ta, ma119; VLDEP-NEXT: vslidedown.vx v8, v8, a0120; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma121; VLDEP-NEXT: vslideup.vi v8, v9, 2122; VLDEP-NEXT: ret123 %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 -2, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)124 ret <vscale x 1 x i64> %v125}126 127define <vscale x 1 x i64> @test_vp_splice_nxv1i64_masked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {128; NOVLDEP-LABEL: test_vp_splice_nxv1i64_masked:129; NOVLDEP: # %bb.0:130; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma131; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t132; NOVLDEP-NEXT: addi a0, a0, -1133; NOVLDEP-NEXT: vsetvli zero, zero, e64, m1, ta, mu134; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t135; NOVLDEP-NEXT: ret136;137; VLDEP-LABEL: test_vp_splice_nxv1i64_masked:138; VLDEP: # %bb.0:139; VLDEP-NEXT: addi a0, a0, -1140; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma141; VLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t142; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, mu143; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t144; VLDEP-NEXT: ret145 %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)146 ret <vscale x 1 x i64> %v147}148 149define <vscale x 2 x i32> @test_vp_splice_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {150; NOVLDEP-LABEL: test_vp_splice_nxv2i32:151; NOVLDEP: # %bb.0:152; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma153; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3154; NOVLDEP-NEXT: addi a0, a0, -3155; NOVLDEP-NEXT: vslideup.vx v8, v9, a0156; NOVLDEP-NEXT: ret157;158; VLDEP-LABEL: test_vp_splice_nxv2i32:159; VLDEP: # %bb.0:160; VLDEP-NEXT: addi a0, a0, -3161; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma162; VLDEP-NEXT: vslidedown.vi v8, v8, 3163; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma164; VLDEP-NEXT: vslideup.vx v8, v9, a0165; VLDEP-NEXT: ret166 %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)167 ret <vscale x 2 x i32> %v168}169 170define <vscale x 2 x i32> @test_vp_splice_nxv2i32_negative_offset(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {171; NOVLDEP-LABEL: test_vp_splice_nxv2i32_negative_offset:172; NOVLDEP: # %bb.0:173; NOVLDEP-NEXT: addi a0, a0, -4174; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma175; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0176; NOVLDEP-NEXT: vslideup.vi v8, v9, 4177; NOVLDEP-NEXT: ret178;179; VLDEP-LABEL: test_vp_splice_nxv2i32_negative_offset:180; VLDEP: # %bb.0:181; VLDEP-NEXT: addi a0, a0, -4182; VLDEP-NEXT: vsetivli zero, 4, e32, m1, ta, ma183; VLDEP-NEXT: vslidedown.vx v8, v8, a0184; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma185; VLDEP-NEXT: vslideup.vi v8, v9, 4186; VLDEP-NEXT: ret187 %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 -4, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)188 ret <vscale x 2 x i32> %v189}190 191define <vscale x 2 x i32> @test_vp_splice_nxv2i32_masked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {192; NOVLDEP-LABEL: test_vp_splice_nxv2i32_masked:193; NOVLDEP: # %bb.0:194; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma195; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t196; NOVLDEP-NEXT: addi a0, a0, -3197; NOVLDEP-NEXT: vsetvli zero, zero, e32, m1, ta, mu198; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t199; NOVLDEP-NEXT: ret200;201; VLDEP-LABEL: test_vp_splice_nxv2i32_masked:202; VLDEP: # %bb.0:203; VLDEP-NEXT: addi a0, a0, -3204; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma205; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t206; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, mu207; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t208; VLDEP-NEXT: ret209 %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)210 ret <vscale x 2 x i32> %v211}212 213define <vscale x 4 x i16> @test_vp_splice_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {214; NOVLDEP-LABEL: test_vp_splice_nxv4i16:215; NOVLDEP: # %bb.0:216; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma217; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5218; NOVLDEP-NEXT: addi a0, a0, -5219; NOVLDEP-NEXT: vslideup.vx v8, v9, a0220; NOVLDEP-NEXT: ret221;222; VLDEP-LABEL: test_vp_splice_nxv4i16:223; VLDEP: # %bb.0:224; VLDEP-NEXT: addi a0, a0, -5225; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma226; VLDEP-NEXT: vslidedown.vi v8, v8, 5227; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma228; VLDEP-NEXT: vslideup.vx v8, v9, a0229; VLDEP-NEXT: ret230 %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 5, <vscale x 4 x i1> splat (i1 1), i32 %evla, i32 %evlb)231 ret <vscale x 4 x i16> %v232}233 234define <vscale x 4 x i16> @test_vp_splice_nxv4i16_negative_offset(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {235; NOVLDEP-LABEL: test_vp_splice_nxv4i16_negative_offset:236; NOVLDEP: # %bb.0:237; NOVLDEP-NEXT: addi a0, a0, -5238; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma239; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0240; NOVLDEP-NEXT: vslideup.vi v8, v9, 5241; NOVLDEP-NEXT: ret242;243; VLDEP-LABEL: test_vp_splice_nxv4i16_negative_offset:244; VLDEP: # %bb.0:245; VLDEP-NEXT: addi a0, a0, -5246; VLDEP-NEXT: vsetivli zero, 5, e16, m1, ta, ma247; VLDEP-NEXT: vslidedown.vx v8, v8, a0248; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma249; VLDEP-NEXT: vslideup.vi v8, v9, 5250; VLDEP-NEXT: ret251 %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 -5, <vscale x 4 x i1> splat (i1 1), i32 %evla, i32 %evlb)252 ret <vscale x 4 x i16> %v253}254 255define <vscale x 4 x i16> @test_vp_splice_nxv4i16_masked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {256; NOVLDEP-LABEL: test_vp_splice_nxv4i16_masked:257; NOVLDEP: # %bb.0:258; NOVLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, ma259; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t260; NOVLDEP-NEXT: addi a0, a0, -5261; NOVLDEP-NEXT: vsetvli zero, zero, e16, m1, ta, mu262; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t263; NOVLDEP-NEXT: ret264;265; VLDEP-LABEL: test_vp_splice_nxv4i16_masked:266; VLDEP: # %bb.0:267; VLDEP-NEXT: addi a0, a0, -5268; VLDEP-NEXT: vsetvli zero, a0, e16, m1, ta, ma269; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t270; VLDEP-NEXT: vsetvli zero, a1, e16, m1, ta, mu271; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t272; VLDEP-NEXT: ret273 %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 5, <vscale x 4 x i1> %mask, i32 %evla, i32 %evlb)274 ret <vscale x 4 x i16> %v275}276 277define <vscale x 8 x i8> @test_vp_splice_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {278; NOVLDEP-LABEL: test_vp_splice_nxv8i8:279; NOVLDEP: # %bb.0:280; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma281; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5282; NOVLDEP-NEXT: addi a0, a0, -5283; NOVLDEP-NEXT: vslideup.vx v8, v9, a0284; NOVLDEP-NEXT: ret285;286; VLDEP-LABEL: test_vp_splice_nxv8i8:287; VLDEP: # %bb.0:288; VLDEP-NEXT: addi a0, a0, -5289; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma290; VLDEP-NEXT: vslidedown.vi v8, v8, 5291; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma292; VLDEP-NEXT: vslideup.vx v8, v9, a0293; VLDEP-NEXT: ret294 %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 5, <vscale x 8 x i1> splat (i1 1), i32 %evla, i32 %evlb)295 ret <vscale x 8 x i8> %v296}297 298define <vscale x 8 x i8> @test_vp_splice_nxv8i8_negative_offset(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {299; NOVLDEP-LABEL: test_vp_splice_nxv8i8_negative_offset:300; NOVLDEP: # %bb.0:301; NOVLDEP-NEXT: addi a0, a0, -5302; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma303; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0304; NOVLDEP-NEXT: vslideup.vi v8, v9, 5305; NOVLDEP-NEXT: ret306;307; VLDEP-LABEL: test_vp_splice_nxv8i8_negative_offset:308; VLDEP: # %bb.0:309; VLDEP-NEXT: addi a0, a0, -5310; VLDEP-NEXT: vsetivli zero, 5, e8, m1, ta, ma311; VLDEP-NEXT: vslidedown.vx v8, v8, a0312; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma313; VLDEP-NEXT: vslideup.vi v8, v9, 5314; VLDEP-NEXT: ret315 %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 -5, <vscale x 8 x i1> splat (i1 1), i32 %evla, i32 %evlb)316 ret <vscale x 8 x i8> %v317}318 319define <vscale x 8 x i8> @test_vp_splice_nxv8i8_masked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {320; NOVLDEP-LABEL: test_vp_splice_nxv8i8_masked:321; NOVLDEP: # %bb.0:322; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma323; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t324; NOVLDEP-NEXT: addi a0, a0, -5325; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, mu326; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t327; NOVLDEP-NEXT: ret328;329; VLDEP-LABEL: test_vp_splice_nxv8i8_masked:330; VLDEP: # %bb.0:331; VLDEP-NEXT: addi a0, a0, -5332; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma333; VLDEP-NEXT: vslidedown.vi v8, v8, 5, v0.t334; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, mu335; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t336; VLDEP-NEXT: ret337 %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 5, <vscale x 8 x i1> %mask, i32 %evla, i32 %evlb)338 ret <vscale x 8 x i8> %v339}340 341define <vscale x 1 x double> @test_vp_splice_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {342; NOVLDEP-LABEL: test_vp_splice_nxv1f64:343; NOVLDEP: # %bb.0:344; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma345; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1346; NOVLDEP-NEXT: addi a0, a0, -1347; NOVLDEP-NEXT: vslideup.vx v8, v9, a0348; NOVLDEP-NEXT: ret349;350; VLDEP-LABEL: test_vp_splice_nxv1f64:351; VLDEP: # %bb.0:352; VLDEP-NEXT: addi a0, a0, -1353; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma354; VLDEP-NEXT: vslidedown.vi v8, v8, 1355; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma356; VLDEP-NEXT: vslideup.vx v8, v9, a0357; VLDEP-NEXT: ret358 %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 1, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)359 ret <vscale x 1 x double> %v360}361 362define <vscale x 1 x double> @test_vp_splice_nxv1f64_negative_offset(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {363; NOVLDEP-LABEL: test_vp_splice_nxv1f64_negative_offset:364; NOVLDEP: # %bb.0:365; NOVLDEP-NEXT: addi a0, a0, -2366; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma367; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0368; NOVLDEP-NEXT: vslideup.vi v8, v9, 2369; NOVLDEP-NEXT: ret370;371; VLDEP-LABEL: test_vp_splice_nxv1f64_negative_offset:372; VLDEP: # %bb.0:373; VLDEP-NEXT: addi a0, a0, -2374; VLDEP-NEXT: vsetivli zero, 2, e64, m1, ta, ma375; VLDEP-NEXT: vslidedown.vx v8, v8, a0376; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma377; VLDEP-NEXT: vslideup.vi v8, v9, 2378; VLDEP-NEXT: ret379 %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 -2, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)380 ret <vscale x 1 x double> %v381}382 383define <vscale x 1 x double> @test_vp_splice_nxv1f64_masked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {384; NOVLDEP-LABEL: test_vp_splice_nxv1f64_masked:385; NOVLDEP: # %bb.0:386; NOVLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, ma387; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t388; NOVLDEP-NEXT: addi a0, a0, -1389; NOVLDEP-NEXT: vsetvli zero, zero, e64, m1, ta, mu390; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t391; NOVLDEP-NEXT: ret392;393; VLDEP-LABEL: test_vp_splice_nxv1f64_masked:394; VLDEP: # %bb.0:395; VLDEP-NEXT: addi a0, a0, -1396; VLDEP-NEXT: vsetvli zero, a0, e64, m1, ta, ma397; VLDEP-NEXT: vslidedown.vi v8, v8, 1, v0.t398; VLDEP-NEXT: vsetvli zero, a1, e64, m1, ta, mu399; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t400; VLDEP-NEXT: ret401 %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)402 ret <vscale x 1 x double> %v403}404 405define <vscale x 2 x float> @test_vp_splice_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {406; NOVLDEP-LABEL: test_vp_splice_nxv2f32:407; NOVLDEP: # %bb.0:408; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma409; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3410; NOVLDEP-NEXT: addi a0, a0, -3411; NOVLDEP-NEXT: vslideup.vx v8, v9, a0412; NOVLDEP-NEXT: ret413;414; VLDEP-LABEL: test_vp_splice_nxv2f32:415; VLDEP: # %bb.0:416; VLDEP-NEXT: addi a0, a0, -3417; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma418; VLDEP-NEXT: vslidedown.vi v8, v8, 3419; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma420; VLDEP-NEXT: vslideup.vx v8, v9, a0421; VLDEP-NEXT: ret422 %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)423 ret <vscale x 2 x float> %v424}425 426define <vscale x 2 x float> @test_vp_splice_nxv2f32_negative_offset(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {427; NOVLDEP-LABEL: test_vp_splice_nxv2f32_negative_offset:428; NOVLDEP: # %bb.0:429; NOVLDEP-NEXT: addi a0, a0, -3430; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma431; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0432; NOVLDEP-NEXT: vslideup.vi v8, v9, 3433; NOVLDEP-NEXT: ret434;435; VLDEP-LABEL: test_vp_splice_nxv2f32_negative_offset:436; VLDEP: # %bb.0:437; VLDEP-NEXT: addi a0, a0, -3438; VLDEP-NEXT: vsetivli zero, 3, e32, m1, ta, ma439; VLDEP-NEXT: vslidedown.vx v8, v8, a0440; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma441; VLDEP-NEXT: vslideup.vi v8, v9, 3442; VLDEP-NEXT: ret443 %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)444 ret <vscale x 2 x float> %v445}446 447define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {448; NOVLDEP-LABEL: test_vp_splice_nxv2f32_masked:449; NOVLDEP: # %bb.0:450; NOVLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, ma451; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t452; NOVLDEP-NEXT: addi a0, a0, -3453; NOVLDEP-NEXT: vsetvli zero, zero, e32, m1, ta, mu454; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t455; NOVLDEP-NEXT: ret456;457; VLDEP-LABEL: test_vp_splice_nxv2f32_masked:458; VLDEP: # %bb.0:459; VLDEP-NEXT: addi a0, a0, -3460; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma461; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t462; VLDEP-NEXT: vsetvli zero, a1, e32, m1, ta, mu463; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t464; VLDEP-NEXT: ret465 %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)466 ret <vscale x 2 x float> %v467}468 469define <vscale x 16 x i64> @test_vp_splice_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {470; CHECK-LABEL: test_vp_splice_nxv16i64:471; CHECK: # %bb.0:472; CHECK-NEXT: csrr a4, vlenb473; CHECK-NEXT: slli a1, a4, 3474; CHECK-NEXT: slli a7, a4, 1475; CHECK-NEXT: addi a7, a7, -1476; CHECK-NEXT: add a5, a0, a1477; CHECK-NEXT: mv a6, a2478; CHECK-NEXT: bltu a2, a7, .LBB22_2479; CHECK-NEXT: # %bb.1:480; CHECK-NEXT: mv a6, a7481; CHECK-NEXT: .LBB22_2:482; CHECK-NEXT: addi sp, sp, -80483; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill484; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill485; CHECK-NEXT: addi s0, sp, 80486; CHECK-NEXT: csrr a7, vlenb487; CHECK-NEXT: slli a7, a7, 5488; CHECK-NEXT: sub sp, sp, a7489; CHECK-NEXT: andi sp, sp, -64490; CHECK-NEXT: vl8re64.v v24, (a5)491; CHECK-NEXT: slli a5, a6, 3492; CHECK-NEXT: addi a6, sp, 64493; CHECK-NEXT: add a5, a6, a5494; CHECK-NEXT: mv a7, a2495; CHECK-NEXT: bltu a2, a4, .LBB22_4496; CHECK-NEXT: # %bb.3:497; CHECK-NEXT: mv a7, a4498; CHECK-NEXT: .LBB22_4:499; CHECK-NEXT: vl8re64.v v0, (a0)500; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, ma501; CHECK-NEXT: vse64.v v8, (a6)502; CHECK-NEXT: sub a0, a2, a4503; CHECK-NEXT: add a6, a6, a1504; CHECK-NEXT: sub a7, a3, a4505; CHECK-NEXT: sltu a2, a2, a0506; CHECK-NEXT: addi a2, a2, -1507; CHECK-NEXT: and a2, a2, a0508; CHECK-NEXT: sltu a0, a3, a7509; CHECK-NEXT: addi a0, a0, -1510; CHECK-NEXT: and a0, a0, a7511; CHECK-NEXT: add a7, a5, a1512; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma513; CHECK-NEXT: vse64.v v16, (a6)514; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma515; CHECK-NEXT: vse64.v v24, (a7)516; CHECK-NEXT: bltu a3, a4, .LBB22_6517; CHECK-NEXT: # %bb.5:518; CHECK-NEXT: mv a3, a4519; CHECK-NEXT: .LBB22_6:520; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma521; CHECK-NEXT: vse64.v v0, (a5)522; CHECK-NEXT: addi a2, sp, 104523; CHECK-NEXT: add a1, a2, a1524; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma525; CHECK-NEXT: vle64.v v16, (a1)526; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma527; CHECK-NEXT: vle64.v v8, (a2)528; CHECK-NEXT: addi sp, s0, -80529; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload530; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload531; CHECK-NEXT: addi sp, sp, 80532; CHECK-NEXT: ret533 %v = call <vscale x 16 x i64> @llvm.experimental.vp.splice.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 5, <vscale x 16 x i1> splat (i1 1), i32 %evla, i32 %evlb)534 ret <vscale x 16 x i64> %v535}536 537define <vscale x 16 x i64> @test_vp_splice_nxv16i64_negative_offset(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {538; CHECK-LABEL: test_vp_splice_nxv16i64_negative_offset:539; CHECK: # %bb.0:540; CHECK-NEXT: csrr a4, vlenb541; CHECK-NEXT: slli a1, a4, 3542; CHECK-NEXT: slli a7, a4, 1543; CHECK-NEXT: addi a7, a7, -1544; CHECK-NEXT: add a5, a0, a1545; CHECK-NEXT: mv a6, a2546; CHECK-NEXT: bltu a2, a7, .LBB23_2547; CHECK-NEXT: # %bb.1:548; CHECK-NEXT: mv a6, a7549; CHECK-NEXT: .LBB23_2:550; CHECK-NEXT: addi sp, sp, -80551; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill552; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill553; CHECK-NEXT: addi s0, sp, 80554; CHECK-NEXT: csrr a7, vlenb555; CHECK-NEXT: slli a7, a7, 5556; CHECK-NEXT: sub sp, sp, a7557; CHECK-NEXT: andi sp, sp, -64558; CHECK-NEXT: vl8re64.v v24, (a5)559; CHECK-NEXT: slli a5, a6, 3560; CHECK-NEXT: addi a7, sp, 64561; CHECK-NEXT: add a6, a7, a5562; CHECK-NEXT: mv t0, a2563; CHECK-NEXT: bltu a2, a4, .LBB23_4564; CHECK-NEXT: # %bb.3:565; CHECK-NEXT: mv t0, a4566; CHECK-NEXT: .LBB23_4:567; CHECK-NEXT: vl8re64.v v0, (a0)568; CHECK-NEXT: vsetvli zero, t0, e64, m8, ta, ma569; CHECK-NEXT: vse64.v v8, (a7)570; CHECK-NEXT: sub a0, a2, a4571; CHECK-NEXT: add a7, a7, a1572; CHECK-NEXT: sub t0, a3, a4573; CHECK-NEXT: sltu a2, a2, a0574; CHECK-NEXT: addi a2, a2, -1575; CHECK-NEXT: and a2, a2, a0576; CHECK-NEXT: sltu a0, a3, t0577; CHECK-NEXT: addi a0, a0, -1578; CHECK-NEXT: and a0, a0, t0579; CHECK-NEXT: add t0, a6, a1580; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma581; CHECK-NEXT: vse64.v v16, (a7)582; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma583; CHECK-NEXT: vse64.v v24, (t0)584; CHECK-NEXT: bltu a3, a4, .LBB23_6585; CHECK-NEXT: # %bb.5:586; CHECK-NEXT: mv a3, a4587; CHECK-NEXT: .LBB23_6:588; CHECK-NEXT: li a2, 8589; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma590; CHECK-NEXT: vse64.v v0, (a6)591; CHECK-NEXT: bltu a5, a2, .LBB23_8592; CHECK-NEXT: # %bb.7:593; CHECK-NEXT: li a5, 8594; CHECK-NEXT: .LBB23_8:595; CHECK-NEXT: sub a2, a6, a5596; CHECK-NEXT: add a1, a2, a1597; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma598; CHECK-NEXT: vle64.v v16, (a1)599; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma600; CHECK-NEXT: vle64.v v8, (a2)601; CHECK-NEXT: addi sp, s0, -80602; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload603; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload604; CHECK-NEXT: addi sp, sp, 80605; CHECK-NEXT: ret606 %v = call <vscale x 16 x i64> @llvm.experimental.vp.splice.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 -1, <vscale x 16 x i1> splat (i1 1), i32 %evla, i32 %evlb)607 ret <vscale x 16 x i64> %v608}609 610define <vscale x 2 x half> @test_vp_splice_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {611; NOVLDEP-LABEL: test_vp_splice_nxv2f16:612; NOVLDEP: # %bb.0:613; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma614; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3615; NOVLDEP-NEXT: addi a0, a0, -3616; NOVLDEP-NEXT: vslideup.vx v8, v9, a0617; NOVLDEP-NEXT: ret618;619; VLDEP-LABEL: test_vp_splice_nxv2f16:620; VLDEP: # %bb.0:621; VLDEP-NEXT: addi a0, a0, -3622; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma623; VLDEP-NEXT: vslidedown.vi v8, v8, 3624; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma625; VLDEP-NEXT: vslideup.vx v8, v9, a0626; VLDEP-NEXT: ret627 %v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)628 ret <vscale x 2 x half> %v629}630 631define <vscale x 2 x half> @test_vp_splice_nxv2f16_negative_offset(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {632; NOVLDEP-LABEL: test_vp_splice_nxv2f16_negative_offset:633; NOVLDEP: # %bb.0:634; NOVLDEP-NEXT: addi a0, a0, -3635; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma636; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0637; NOVLDEP-NEXT: vslideup.vi v8, v9, 3638; NOVLDEP-NEXT: ret639;640; VLDEP-LABEL: test_vp_splice_nxv2f16_negative_offset:641; VLDEP: # %bb.0:642; VLDEP-NEXT: addi a0, a0, -3643; VLDEP-NEXT: vsetivli zero, 3, e16, mf2, ta, ma644; VLDEP-NEXT: vslidedown.vx v8, v8, a0645; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma646; VLDEP-NEXT: vslideup.vi v8, v9, 3647; VLDEP-NEXT: ret648 %v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)649 ret <vscale x 2 x half> %v650}651 652define <vscale x 2 x half> @test_vp_splice_nxv2f16_masked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {653; NOVLDEP-LABEL: test_vp_splice_nxv2f16_masked:654; NOVLDEP: # %bb.0:655; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma656; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t657; NOVLDEP-NEXT: addi a0, a0, -3658; NOVLDEP-NEXT: vsetvli zero, zero, e16, mf2, ta, mu659; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t660; NOVLDEP-NEXT: ret661;662; VLDEP-LABEL: test_vp_splice_nxv2f16_masked:663; VLDEP: # %bb.0:664; VLDEP-NEXT: addi a0, a0, -3665; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma666; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t667; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, mu668; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t669; VLDEP-NEXT: ret670 %v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)671 ret <vscale x 2 x half> %v672}673 674define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {675; NOVLDEP-LABEL: test_vp_splice_nxv2bf16:676; NOVLDEP: # %bb.0:677; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma678; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3679; NOVLDEP-NEXT: addi a0, a0, -3680; NOVLDEP-NEXT: vslideup.vx v8, v9, a0681; NOVLDEP-NEXT: ret682;683; VLDEP-LABEL: test_vp_splice_nxv2bf16:684; VLDEP: # %bb.0:685; VLDEP-NEXT: addi a0, a0, -3686; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma687; VLDEP-NEXT: vslidedown.vi v8, v8, 3688; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma689; VLDEP-NEXT: vslideup.vx v8, v9, a0690; VLDEP-NEXT: ret691 %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)692 ret <vscale x 2 x bfloat> %v693}694 695define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_negative_offset(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {696; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:697; NOVLDEP: # %bb.0:698; NOVLDEP-NEXT: addi a0, a0, -3699; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma700; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0701; NOVLDEP-NEXT: vslideup.vi v8, v9, 3702; NOVLDEP-NEXT: ret703;704; VLDEP-LABEL: test_vp_splice_nxv2bf16_negative_offset:705; VLDEP: # %bb.0:706; VLDEP-NEXT: addi a0, a0, -3707; VLDEP-NEXT: vsetivli zero, 3, e16, mf2, ta, ma708; VLDEP-NEXT: vslidedown.vx v8, v8, a0709; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma710; VLDEP-NEXT: vslideup.vi v8, v9, 3711; VLDEP-NEXT: ret712 %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)713 ret <vscale x 2 x bfloat> %v714}715 716define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {717; NOVLDEP-LABEL: test_vp_splice_nxv2bf16_masked:718; NOVLDEP: # %bb.0:719; NOVLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, ma720; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t721; NOVLDEP-NEXT: addi a0, a0, -3722; NOVLDEP-NEXT: vsetvli zero, zero, e16, mf2, ta, mu723; NOVLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t724; NOVLDEP-NEXT: ret725;726; VLDEP-LABEL: test_vp_splice_nxv2bf16_masked:727; VLDEP: # %bb.0:728; VLDEP-NEXT: addi a0, a0, -3729; VLDEP-NEXT: vsetvli zero, a0, e16, mf2, ta, ma730; VLDEP-NEXT: vslidedown.vi v8, v8, 3, v0.t731; VLDEP-NEXT: vsetvli zero, a1, e16, mf2, ta, mu732; VLDEP-NEXT: vslideup.vx v8, v9, a0, v0.t733; VLDEP-NEXT: ret734 %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)735 ret <vscale x 2 x bfloat> %v736}737 738define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {739; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:740; CHECK: # %bb.0:741; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma742; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t743; CHECK-NEXT: vmv.v.v v8, v9744; CHECK-NEXT: ret745 %va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0746 %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)747 ret <vscale x 2 x i32> %v748}749 750define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {751; CHECK-LABEL: test_vp_splice_nxv2i32_with_splat_firstelt:752; CHECK: # %bb.0:753; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma754; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t755; CHECK-NEXT: vmv.v.v v8, v9756; CHECK-NEXT: ret757 %ins = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0758 %splat = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer759 %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %splat, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)760 ret <vscale x 2 x i32> %v761}762 763define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {764; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:765; CHECK: # %bb.0:766; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma767; CHECK-NEXT: vfslide1up.vf v9, v8, fa0, v0.t768; CHECK-NEXT: vmv.v.v v8, v9769; CHECK-NEXT: ret770 %va = insertelement <vscale x 2 x float> poison, float %first, i32 0771 %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)772 ret <vscale x 2 x float> %v773}774 775define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {776; ZVFH-LABEL: test_vp_splice_nxv2f16_with_firstelt:777; ZVFH: # %bb.0:778; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma779; ZVFH-NEXT: vfslide1up.vf v9, v8, fa0, v0.t780; ZVFH-NEXT: vmv1r.v v8, v9781; ZVFH-NEXT: ret782;783; ZVFHMIN-LABEL: test_vp_splice_nxv2f16_with_firstelt:784; ZVFHMIN: # %bb.0:785; ZVFHMIN-NEXT: fmv.x.h a1, fa0786; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma787; ZVFHMIN-NEXT: vslide1up.vx v9, v8, a1, v0.t788; ZVFHMIN-NEXT: vmv1r.v v8, v9789; ZVFHMIN-NEXT: ret790 %va = insertelement <vscale x 2 x half> poison, half %first, i32 0791 %v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)792 ret <vscale x 2 x half> %v793}794 795define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {796; CHECK-LABEL: test_vp_splice_nxv2bf16_with_firstelt:797; CHECK: # %bb.0:798; CHECK-NEXT: fmv.x.h a1, fa0799; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma800; CHECK-NEXT: vslide1up.vx v9, v8, a1, v0.t801; CHECK-NEXT: vmv1r.v v8, v9802; CHECK-NEXT: ret803 %va = insertelement <vscale x 2 x bfloat> poison, bfloat %first, i32 0804 %v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)805 ret <vscale x 2 x bfloat> %v806}807 808attributes #0 = { nounwind vscale_range(2,0) }809