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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=riscv32 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV32 %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,m -O2 | FileCheck -check-prefixes=CHECK,RV64 %s4 5define {<vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor2_v2(ptr %ptr, i32 zeroext %evl) {6; CHECK-LABEL: load_factor2_v2:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9; CHECK-NEXT: vlseg2e32.v v8, (a0)10; CHECK-NEXT: ret11 %rvl = mul nuw i32 %evl, 212 %wide.masked.load = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %rvl)13 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %wide.masked.load)14 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 015 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 116 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 017 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 118 ret { <vscale x 2 x i32>, <vscale x 2 x i32> } %res119}20 21define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor3_v2(ptr %ptr, i32 zeroext %evl) {22; CHECK-LABEL: load_factor3_v2:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma25; CHECK-NEXT: vlseg3e32.v v8, (a0)26; CHECK-NEXT: ret27 %rvl = mul nuw i32 %evl, 328 %wide.masked.load = call <vscale x 6 x i32> @llvm.vp.load(ptr %ptr, <vscale x 6 x i1> splat (i1 true), i32 %rvl)29 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3(<vscale x 6 x i32> %wide.masked.load)30 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 031 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 132 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 233 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 034 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 135 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 236 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res137}38 39define {<vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor3_partial(ptr %ptr, i32 zeroext %evl) {40; CHECK-LABEL: load_factor3_partial:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma43; CHECK-NEXT: vlseg3e32.v v7, (a0)44; CHECK-NEXT: vmv1r.v v8, v745; CHECK-NEXT: ret46 %rvl = mul nuw i32 %evl, 347 %wide.masked.load = call <vscale x 6 x i32> @llvm.vp.load(ptr %ptr, <vscale x 6 x i1> splat (i1 true), i32 %rvl)48 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3(<vscale x 6 x i32> %wide.masked.load)49 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 050 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 251 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 052 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t2, 153 ret { <vscale x 2 x i32>, <vscale x 2 x i32> } %res154}55 56; InterleavedAccess should kick in even if the users of deinterleave intrinsic are not extractvalue.57define {<vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor3_no_extract(ptr %ptr, i32 zeroext %evl) {58; CHECK-LABEL: load_factor3_no_extract:59; CHECK: # %bb.0:60; CHECK-NEXT: li a2, 1261; CHECK-NEXT: beq a1, a2, .LBB3_262; CHECK-NEXT: # %bb.1: # %bb063; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma64; CHECK-NEXT: vlseg3e32.v v7, (a0)65; CHECK-NEXT: j .LBB3_366; CHECK-NEXT: .LBB3_2: # %bb167; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma68; CHECK-NEXT: vlseg3e32.v v7, (a0)69; CHECK-NEXT: .LBB3_3: # %merge70; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma71; CHECK-NEXT: vmv1r.v v8, v772; CHECK-NEXT: ret73 %p = icmp ne i32 %evl, 1274 br i1 %p, label %bb0, label %bb175 76bb0:77 %rvl.0 = mul nuw i32 %evl, 378 %wide.load.0 = call <vscale x 6 x i32> @llvm.vp.load(ptr %ptr, <vscale x 6 x i1> splat (i1 true), i32 %rvl.0)79 %deinterleaved.results.0 = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3(<vscale x 6 x i32> %wide.load.0)80 br label %merge81 82bb1:83 %wide.load.1 = call <vscale x 6 x i32> @llvm.vp.load(ptr %ptr, <vscale x 6 x i1> splat (i1 true), i32 12)84 %deinterleaved.results.1 = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3(<vscale x 6 x i32> %wide.load.1)85 br label %merge86 87merge:88 %deinterleaved.results = phi { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } [%deinterleaved.results.0, %bb0], [%deinterleaved.results.1, %bb1]89 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 090 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 291 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 092 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t2, 193 ret { <vscale x 2 x i32>, <vscale x 2 x i32> } %res194}95 96define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor4_v2(ptr %ptr, i32 zeroext %evl) {97; CHECK-LABEL: load_factor4_v2:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma100; CHECK-NEXT: vlseg4e32.v v8, (a0)101; CHECK-NEXT: ret102 %rvl = mul nuw i32 %evl, 4103 %wide.masked.load = call <vscale x 8 x i32> @llvm.vp.load.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %rvl)104 %d = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave4.nxv8i32(<vscale x 8 x i32> %wide.masked.load)105 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 0106 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 1107 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 2108 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 3109 110 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0111 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1112 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2113 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3114 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3115}116 117define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor5_v2(ptr %ptr, i32 zeroext %evl) {118; CHECK-LABEL: load_factor5_v2:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma121; CHECK-NEXT: vlseg5e32.v v8, (a0)122; CHECK-NEXT: ret123 %rvl = mul nuw i32 %evl, 5124 %wide.masked.load = call <vscale x 10 x i32> @llvm.vp.load(ptr %ptr, <vscale x 10 x i1> splat (i1 true), i32 %rvl)125 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave5(<vscale x 10 x i32> %wide.masked.load)126 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0127 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1128 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 2129 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 3130 %t4 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 4131 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0132 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1133 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2134 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3135 %res4 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3, <vscale x 2 x i32> %t4, 4136 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res4137}138 139define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor7_v2(ptr %ptr, i32 zeroext %evl) {140; CHECK-LABEL: load_factor7_v2:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma143; CHECK-NEXT: vlseg7e32.v v8, (a0)144; CHECK-NEXT: ret145 %rvl = mul nuw i32 %evl, 7146 %wide.masked.load = call <vscale x 14 x i32> @llvm.vp.load(ptr %ptr, <vscale x 14 x i1> splat (i1 true), i32 %rvl)147 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave7(<vscale x 14 x i32> %wide.masked.load)148 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0149 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1150 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 2151 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 3152 %t4 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 4153 %t5 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 5154 %t6 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 6155 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0156 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1157 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2158 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3159 %res4 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3, <vscale x 2 x i32> %t4, 4160 %res5 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res4, <vscale x 2 x i32> %t5, 5161 %res6 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res5, <vscale x 2 x i32> %t6, 6162 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res6163}164 165define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @load_factor8_v2(ptr %ptr, i32 zeroext %evl) {166; CHECK-LABEL: load_factor8_v2:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma169; CHECK-NEXT: vlseg8e32.v v8, (a0)170; CHECK-NEXT: ret171 %rvl = mul nuw i32 %evl, 8172 %wide.masked.load = call <vscale x 16 x i32> @llvm.vp.load.nxv16i32.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %rvl)173 %d = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave8.nxv16i32(<vscale x 16 x i32> %wide.masked.load)174 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 0175 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 1176 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 2177 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 3178 %t4 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 4179 %t5 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 5180 %t6 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 6181 %t7 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 7182 183 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0184 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1185 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2186 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3187 %res4 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3, <vscale x 2 x i32> %t4, 4188 %res5 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res4, <vscale x 2 x i32> %t5, 5189 %res6 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res5, <vscale x 2 x i32> %t6, 6190 %res7 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res6, <vscale x 2 x i32> %t7, 7191 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res7192}193 194define void @store_factor2_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 zeroext %evl) {195; CHECK-LABEL: store_factor2_v2:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma198; CHECK-NEXT: vsseg2e32.v v8, (a0)199; CHECK-NEXT: ret200 %rvl = mul nuw i32 %evl, 2201 %interleaved.vec = call <vscale x 2 x i32> @llvm.vector.interleave2.nxv2i32(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1)202 call void @llvm.vp.store.nxv2i32.p0(<vscale x 2 x i32> %interleaved.vec, ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %rvl)203 ret void204}205 206define void @store_factor3_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2, ptr %ptr, i32 zeroext %evl) {207; CHECK-LABEL: store_factor3_v2:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma210; CHECK-NEXT: vsseg3e32.v v8, (a0)211; CHECK-NEXT: ret212 %rvl = mul nuw i32 %evl, 3213 %interleaved.vec = call <vscale x 3 x i32> @llvm.vector.interleave3(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2)214 call void @llvm.vp.store(<vscale x 3 x i32> %interleaved.vec, ptr %ptr, <vscale x 3 x i1> splat (i1 true), i32 %rvl)215 ret void216}217 218define void @store_factor4_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 zeroext %evl) {219; RV32-LABEL: store_factor4_v2:220; RV32: # %bb.0:221; RV32-NEXT: slli a1, a1, 3222; RV32-NEXT: srli a1, a1, 2223; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma224; RV32-NEXT: vmv1r.v v10, v8225; RV32-NEXT: vmv1r.v v11, v9226; RV32-NEXT: vsseg4e32.v v8, (a0)227; RV32-NEXT: ret228;229; RV64-LABEL: store_factor4_v2:230; RV64: # %bb.0:231; RV64-NEXT: slli a1, a1, 35232; RV64-NEXT: srli a1, a1, 34233; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma234; RV64-NEXT: vmv1r.v v10, v8235; RV64-NEXT: vmv1r.v v11, v9236; RV64-NEXT: vsseg4e32.v v8, (a0)237; RV64-NEXT: ret238 %rvl = mul nuw i32 %evl, 8239 %interleaved.vec = call <vscale x 4 x i32> @llvm.vector.interleave4.nxv4i32(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1)240 call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %interleaved.vec, ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %rvl)241 ret void242}243 244define void @store_factor5_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2, <vscale x 1 x i32> %v3, <vscale x 1 x i32> %v4, ptr %ptr, i32 zeroext %evl) {245; CHECK-LABEL: store_factor5_v2:246; CHECK: # %bb.0:247; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma248; CHECK-NEXT: vsseg5e32.v v8, (a0)249; CHECK-NEXT: ret250 %rvl = mul nuw i32 %evl, 5251 %interleaved.vec = call <vscale x 5 x i32> @llvm.vector.interleave5(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2, <vscale x 1 x i32> %v3, <vscale x 1 x i32> %v4)252 call void @llvm.vp.store(<vscale x 5 x i32> %interleaved.vec, ptr %ptr, <vscale x 5 x i1> splat (i1 true), i32 %rvl)253 ret void254}255 256define void @store_factor7_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2, <vscale x 1 x i32> %v3, <vscale x 1 x i32> %v4, <vscale x 1 x i32> %v5, <vscale x 1 x i32> %v6, ptr %ptr, i32 zeroext %evl) {257; CHECK-LABEL: store_factor7_v2:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma260; CHECK-NEXT: vsseg7e32.v v8, (a0)261; CHECK-NEXT: ret262 %rvl = mul nuw i32 %evl, 7263 %interleaved.vec = call <vscale x 7 x i32> @llvm.vector.interleave7(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v2, <vscale x 1 x i32> %v3, <vscale x 1 x i32> %v4, <vscale x 1 x i32> %v5, <vscale x 1 x i32> %v6)264 call void @llvm.vp.store(<vscale x 7 x i32> %interleaved.vec, ptr %ptr, <vscale x 7 x i1> splat (i1 true), i32 %rvl)265 ret void266}267 268define void @store_factor8_v2(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 zeroext %evl) {269; CHECK-LABEL: store_factor8_v2:270; CHECK: # %bb.0:271; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma272; CHECK-NEXT: vmv1r.v v10, v8273; CHECK-NEXT: vmv1r.v v11, v9274; CHECK-NEXT: vmv1r.v v12, v8275; CHECK-NEXT: vmv1r.v v13, v9276; CHECK-NEXT: vmv1r.v v14, v8277; CHECK-NEXT: vmv1r.v v15, v9278; CHECK-NEXT: vsseg8e32.v v8, (a0)279; CHECK-NEXT: ret280 %rvl = mul nuw i32 %evl, 8281 %interleaved.vec = call <vscale x 8 x i32> @llvm.vector.interleave8.nxv8i32(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1)282 call void @llvm.vp.store.nxv8i32.p0(<vscale x 8 x i32> %interleaved.vec, ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %rvl)283 ret void284}285 286define {<vscale x 2 x i32>, <vscale x 2 x i32>} @masked_load_factor2_v2(<vscale x 2 x i1> %mask, ptr %ptr, i32 zeroext %evl) {287; CHECK-LABEL: masked_load_factor2_v2:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma290; CHECK-NEXT: vlseg2e32.v v8, (a0), v0.t291; CHECK-NEXT: ret292 %rvl = mul nuw i32 %evl, 2293 %interleaved.mask = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)294 %wide.masked.load = tail call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)295 %deinterleaved.results = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 4 x i32> %wide.masked.load)296 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0297 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1298 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0299 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1300 ret { <vscale x 2 x i32>, <vscale x 2 x i32> } %res1301}302 303define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @masked_load_factor4_v2(<vscale x 2 x i1> %mask, ptr %ptr, i32 zeroext %evl) {304; CHECK-LABEL: masked_load_factor4_v2:305; CHECK: # %bb.0:306; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma307; CHECK-NEXT: vlseg4e32.v v8, (a0), v0.t308; CHECK-NEXT: ret309 %rvl = mul nuw i32 %evl, 4310 %interleaved.mask = call <vscale x 8 x i1> @llvm.vector.interleave4.nxv8i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)311 %wide.masked.load = call <vscale x 8 x i32> @llvm.vp.load.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> %interleaved.mask, i32 %rvl)312 %d = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave4.nxv8i32(<vscale x 8 x i32> %wide.masked.load)313 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 0314 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 1315 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 2316 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 3317 318 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0319 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1320 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2321 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3322 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3323}324 325define void @masked_store_factor2_v2(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 zeroext %evl) {326; CHECK-LABEL: masked_store_factor2_v2:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma329; CHECK-NEXT: vmv1r.v v9, v8330; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t331; CHECK-NEXT: ret332 %rvl = mul nuw i32 %evl, 2333 %interleaved.mask = tail call <vscale x 2 x i1> @llvm.vector.interleave2.nxv2i1(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask)334 %interleaved.vec = tail call <vscale x 2 x i32> @llvm.vector.interleave2.nxv2i32(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v0)335 tail call void @llvm.vp.store.nxv2i32.p0(<vscale x 2 x i32> %interleaved.vec, ptr %ptr, <vscale x 2 x i1> %interleaved.mask, i32 %rvl)336 ret void337}338 339define void @masked_load_store_factor2_v2_shared_mask(<vscale x 2 x i1> %mask, ptr %ptr, i32 zeroext %evl) {340; CHECK-LABEL: masked_load_store_factor2_v2_shared_mask:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma343; CHECK-NEXT: vlseg2e32.v v8, (a0), v0.t344; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t345; CHECK-NEXT: ret346 %rvl = mul nuw i32 %evl, 2347 %interleaved.mask = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)348 %wide.masked.load = tail call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)349 %deinterleaved.results = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 4 x i32> %wide.masked.load)350 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0351 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1352 %interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %t0, <vscale x 2 x i32> %t1)353 tail call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %interleaved.vec, ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)354 ret void355}356 357define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %mask, ptr %ptr, i32 zeroext %evl) {358; RV32-LABEL: masked_load_store_factor2_v2_shared_mask_extract:359; RV32: # %bb.0:360; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma361; RV32-NEXT: vmv1r.v v8, v0362; RV32-NEXT: slli a2, a1, 1363; RV32-NEXT: vmv.v.i v9, 0364; RV32-NEXT: li a3, -1365; RV32-NEXT: vmerge.vim v10, v9, 1, v0366; RV32-NEXT: vwaddu.vv v11, v10, v10367; RV32-NEXT: vwmaccu.vx v11, a3, v10368; RV32-NEXT: csrr a3, vlenb369; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma370; RV32-NEXT: vmv.v.i v10, 0371; RV32-NEXT: srli a3, a3, 2372; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma373; RV32-NEXT: vmsne.vi v0, v11, 0374; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma375; RV32-NEXT: vslidedown.vx v11, v11, a3376; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma377; RV32-NEXT: vmerge.vim v10, v10, 1, v0378; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma379; RV32-NEXT: vmsne.vi v0, v11, 0380; RV32-NEXT: vmerge.vim v9, v9, 1, v0381; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma382; RV32-NEXT: vslideup.vx v10, v9, a3383; RV32-NEXT: vmsne.vi v0, v10, 0384; RV32-NEXT: vle32.v v10, (a0), v0.t385; RV32-NEXT: li a2, 32386; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma387; RV32-NEXT: vnsrl.wx v13, v10, a2388; RV32-NEXT: vnsrl.wi v12, v10, 0389; RV32-NEXT: vmv.x.s a1, v10390; RV32-NEXT: vmv1r.v v0, v8391; RV32-NEXT: vsseg2e32.v v12, (a0), v0.t392; RV32-NEXT: mv a0, a1393; RV32-NEXT: ret394;395; RV64-LABEL: masked_load_store_factor2_v2_shared_mask_extract:396; RV64: # %bb.0:397; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma398; RV64-NEXT: vmv1r.v v8, v0399; RV64-NEXT: vmv.v.i v9, 0400; RV64-NEXT: li a2, -1401; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma402; RV64-NEXT: vmv.v.i v10, 0403; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma404; RV64-NEXT: vmerge.vim v11, v9, 1, v0405; RV64-NEXT: vwaddu.vv v12, v11, v11406; RV64-NEXT: vwmaccu.vx v12, a2, v11407; RV64-NEXT: csrr a2, vlenb408; RV64-NEXT: srli a2, a2, 2409; RV64-NEXT: vmsne.vi v0, v12, 0410; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma411; RV64-NEXT: vslidedown.vx v11, v12, a2412; RV64-NEXT: vmerge.vim v10, v10, 1, v0413; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma414; RV64-NEXT: vmsne.vi v0, v11, 0415; RV64-NEXT: vmerge.vim v9, v9, 1, v0416; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma417; RV64-NEXT: vslideup.vx v10, v9, a2418; RV64-NEXT: slli a2, a1, 33419; RV64-NEXT: vmsne.vi v0, v10, 0420; RV64-NEXT: srli a2, a2, 32421; RV64-NEXT: vsetvli zero, a2, e32, m2, ta, ma422; RV64-NEXT: vle32.v v10, (a0), v0.t423; RV64-NEXT: li a2, 32424; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma425; RV64-NEXT: vnsrl.wx v13, v10, a2426; RV64-NEXT: vnsrl.wi v12, v10, 0427; RV64-NEXT: vmv.x.s a1, v10428; RV64-NEXT: vmv1r.v v0, v8429; RV64-NEXT: vsseg2e32.v v12, (a0), v0.t430; RV64-NEXT: mv a0, a1431; RV64-NEXT: ret432 %rvl = mul nuw i32 %evl, 2433 %interleaved.mask = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)434 %wide.masked.load = tail call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)435 %deinterleaved.results = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 4 x i32> %wide.masked.load)436 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0437 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1438 %r0 = extractelement <vscale x 4 x i32> %wide.masked.load, i32 0439 %interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %t0, <vscale x 2 x i32> %t1)440 tail call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %interleaved.vec, ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)441 ret i32 %r0442}443 444define void @masked_store_factor4_v2(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, ptr %ptr, i32 zeroext %evl) {445; CHECK-LABEL: masked_store_factor4_v2:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma448; CHECK-NEXT: vmv1r.v v10, v8449; CHECK-NEXT: vmv1r.v v11, v9450; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t451; CHECK-NEXT: ret452 %rvl = mul nuw i32 %evl, 4453 %interleaved.mask = call <vscale x 4 x i1> @llvm.vector.interleave4.nxv4i1(<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask)454 %interleaved.vec = call <vscale x 4 x i32> @llvm.vector.interleave4.nxv2i32(<vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1, <vscale x 1 x i32> %v0, <vscale x 1 x i32> %v1)455 call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %interleaved.vec, ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)456 ret void457}458 459define <vscale x 2 x i32> @load_factor2_oneactive(ptr %ptr, i32 zeroext %evl) {460; RV32-LABEL: load_factor2_oneactive:461; RV32: # %bb.0:462; RV32-NEXT: slli a1, a1, 2463; RV32-NEXT: srli a1, a1, 1464; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma465; RV32-NEXT: vlseg2e32.v v7, (a0)466; RV32-NEXT: ret467;468; RV64-LABEL: load_factor2_oneactive:469; RV64: # %bb.0:470; RV64-NEXT: slli a1, a1, 34471; RV64-NEXT: srli a1, a1, 33472; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma473; RV64-NEXT: vlseg2e32.v v7, (a0)474; RV64-NEXT: ret475 %rvl = mul nuw i32 %evl, 4476 %wide.masked.load = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %rvl)477 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %wide.masked.load)478 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1479 ret <vscale x 2 x i32> %t0480}481 482define <vscale x 2 x i32> @load_factor5_oneactive(ptr %ptr, i32 zeroext %evl) {483; CHECK-LABEL: load_factor5_oneactive:484; CHECK: # %bb.0:485; CHECK-NEXT: addi a0, a0, 12486; CHECK-NEXT: li a2, 20487; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma488; CHECK-NEXT: vlse32.v v8, (a0), a2489; CHECK-NEXT: ret490 %rvl = mul nuw i32 %evl, 5491 %wide.masked.load = call <vscale x 10 x i32> @llvm.vp.load(ptr %ptr, <vscale x 10 x i1> splat (i1 true), i32 %rvl)492 %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave5(<vscale x 10 x i32> %wide.masked.load)493 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 3494 ret <vscale x 2 x i32> %t3495}496 497 498; Negative tests499 500define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1> %mask0, <vscale x 2 x i1> %mask1, ptr %ptr, i32 zeroext %evl) {501; RV32-LABEL: not_same_mask:502; RV32: # %bb.0:503; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma504; RV32-NEXT: vmv1r.v v9, v0505; RV32-NEXT: vmv1r.v v0, v8506; RV32-NEXT: slli a1, a1, 1507; RV32-NEXT: vmv.v.i v8, 0508; RV32-NEXT: li a2, -1509; RV32-NEXT: vmerge.vim v10, v8, 1, v0510; RV32-NEXT: vmv1r.v v0, v9511; RV32-NEXT: vmerge.vim v9, v8, 1, v0512; RV32-NEXT: vwaddu.vv v11, v9, v10513; RV32-NEXT: vwmaccu.vx v11, a2, v10514; RV32-NEXT: csrr a2, vlenb515; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma516; RV32-NEXT: vmv.v.i v9, 0517; RV32-NEXT: srli a2, a2, 2518; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma519; RV32-NEXT: vmsne.vi v0, v11, 0520; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma521; RV32-NEXT: vslidedown.vx v10, v11, a2522; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma523; RV32-NEXT: vmerge.vim v9, v9, 1, v0524; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma525; RV32-NEXT: vmsne.vi v0, v10, 0526; RV32-NEXT: vmerge.vim v8, v8, 1, v0527; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma528; RV32-NEXT: vslideup.vx v9, v8, a2529; RV32-NEXT: vmsne.vi v0, v9, 0530; RV32-NEXT: vle32.v v10, (a0), v0.t531; RV32-NEXT: li a0, 32532; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma533; RV32-NEXT: vnsrl.wx v9, v10, a0534; RV32-NEXT: vnsrl.wi v8, v10, 0535; RV32-NEXT: ret536;537; RV64-LABEL: not_same_mask:538; RV64: # %bb.0:539; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma540; RV64-NEXT: vmv1r.v v9, v0541; RV64-NEXT: vmv1r.v v0, v8542; RV64-NEXT: vmv.v.i v8, 0543; RV64-NEXT: li a2, -1544; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma545; RV64-NEXT: vmv.v.i v10, 0546; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma547; RV64-NEXT: vmerge.vim v11, v8, 1, v0548; RV64-NEXT: vmv1r.v v0, v9549; RV64-NEXT: vmerge.vim v9, v8, 1, v0550; RV64-NEXT: vwaddu.vv v12, v9, v11551; RV64-NEXT: vwmaccu.vx v12, a2, v11552; RV64-NEXT: csrr a2, vlenb553; RV64-NEXT: srli a2, a2, 2554; RV64-NEXT: vmsne.vi v0, v12, 0555; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma556; RV64-NEXT: vslidedown.vx v9, v12, a2557; RV64-NEXT: vmerge.vim v10, v10, 1, v0558; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma559; RV64-NEXT: vmsne.vi v0, v9, 0560; RV64-NEXT: slli a1, a1, 33561; RV64-NEXT: vmerge.vim v8, v8, 1, v0562; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma563; RV64-NEXT: vslideup.vx v10, v8, a2564; RV64-NEXT: vmsne.vi v0, v10, 0565; RV64-NEXT: srli a1, a1, 32566; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma567; RV64-NEXT: vle32.v v10, (a0), v0.t568; RV64-NEXT: li a0, 32569; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma570; RV64-NEXT: vnsrl.wx v9, v10, a0571; RV64-NEXT: vnsrl.wi v8, v10, 0572; RV64-NEXT: ret573 %rvl = mul nuw i32 %evl, 2574 %interleaved.mask = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %mask0, <vscale x 2 x i1> %mask1)575 %wide.masked.load = tail call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %interleaved.mask, i32 %rvl)576 %deinterleaved.results = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 4 x i32> %wide.masked.load)577 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 0578 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1579 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0580 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1581 ret { <vscale x 2 x i32>, <vscale x 2 x i32> } %res1582}583 584; EVL should be a multiple of factor585define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @invalid_evl(ptr %ptr, i32 zeroext %evl) nounwind {586; CHECK-LABEL: invalid_evl:587; CHECK: # %bb.0:588; CHECK-NEXT: addi sp, sp, -16589; CHECK-NEXT: csrr a2, vlenb590; CHECK-NEXT: slli a2, a2, 2591; CHECK-NEXT: sub sp, sp, a2592; CHECK-NEXT: ori a1, a1, 1593; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma594; CHECK-NEXT: vle32.v v8, (a0)595; CHECK-NEXT: addi a0, sp, 16596; CHECK-NEXT: vs4r.v v8, (a0)597; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma598; CHECK-NEXT: vlseg4e32.v v8, (a0)599; CHECK-NEXT: csrr a0, vlenb600; CHECK-NEXT: slli a0, a0, 2601; CHECK-NEXT: add sp, sp, a0602; CHECK-NEXT: addi sp, sp, 16603; CHECK-NEXT: ret604 %rvl = or i32 %evl, 1605 %wide.masked.load = call <vscale x 8 x i32> @llvm.vp.load.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %rvl)606 %d = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave4.nxv8i32(<vscale x 8 x i32> %wide.masked.load)607 %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 0608 %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 1609 %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 2610 %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %d, 3611 612 %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> %t0, 0613 %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1614 %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2615 %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3616 ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3617}618 619