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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define <vscale x 1 x i8> @vpload_nxv1i8(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vpload_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma15; CHECK-NEXT: vle8.v v8, (a0), v0.t16; CHECK-NEXT: ret17 %load = call <vscale x 1 x i8> @llvm.vp.load.nxv1i8.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)18 ret <vscale x 1 x i8> %load19}20 21define <vscale x 1 x i8> @vpload_nxv1i8_allones_mask(ptr %ptr, i32 zeroext %evl) {22; CHECK-LABEL: vpload_nxv1i8_allones_mask:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma25; CHECK-NEXT: vle8.v v8, (a0)26; CHECK-NEXT: ret27 %load = call <vscale x 1 x i8> @llvm.vp.load.nxv1i8.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)28 ret <vscale x 1 x i8> %load29}30 31define <vscale x 1 x i8> @vpload_nxv1i8_passthru(ptr %ptr, <vscale x 1 x i1> %m, <vscale x 1 x i8> %passthru, i32 zeroext %evl) {32; CHECK-LABEL: vpload_nxv1i8_passthru:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu35; CHECK-NEXT: vle8.v v8, (a0), v0.t36; CHECK-NEXT: ret37 %load = call <vscale x 1 x i8> @llvm.vp.load.nxv1i8.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)38 %merge = call <vscale x 1 x i8> @llvm.vp.merge.nxv1i8(<vscale x 1 x i1> %m, <vscale x 1 x i8> %load, <vscale x 1 x i8> %passthru, i32 %evl)39 ret <vscale x 1 x i8> %merge40}41 42define <vscale x 2 x i8> @vpload_nxv2i8(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {43; CHECK-LABEL: vpload_nxv2i8:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma46; CHECK-NEXT: vle8.v v8, (a0), v0.t47; CHECK-NEXT: ret48 %load = call <vscale x 2 x i8> @llvm.vp.load.nxv2i8.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)49 ret <vscale x 2 x i8> %load50}51 52define <vscale x 3 x i8> @vpload_nxv3i8(ptr %ptr, <vscale x 3 x i1> %m, i32 zeroext %evl) {53; CHECK-LABEL: vpload_nxv3i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma56; CHECK-NEXT: vle8.v v8, (a0), v0.t57; CHECK-NEXT: ret58 %load = call <vscale x 3 x i8> @llvm.vp.load.nxv3i8.p0(ptr %ptr, <vscale x 3 x i1> %m, i32 %evl)59 ret <vscale x 3 x i8> %load60}61 62define <vscale x 4 x i6> @vpload_nxv4i6(<vscale x 4 x i6>* %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {63; CHECK-LABEL: vpload_nxv4i6:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma66; CHECK-NEXT: vle8.v v8, (a0), v0.t67; CHECK-NEXT: ret68 %load = call <vscale x 4 x i6> @llvm.vp.load.nxv4i6.nxv4i6.p0(<vscale x 4 x i6>* %ptr, <vscale x 4 x i1> %m, i32 %evl)69 ret <vscale x 4 x i6> %load70}71 72define <vscale x 4 x i8> @vpload_nxv4i8(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {73; CHECK-LABEL: vpload_nxv4i8:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma76; CHECK-NEXT: vle8.v v8, (a0), v0.t77; CHECK-NEXT: ret78 %load = call <vscale x 4 x i8> @llvm.vp.load.nxv4i8.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)79 ret <vscale x 4 x i8> %load80}81 82define <vscale x 8 x i8> @vpload_nxv8i8(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {83; CHECK-LABEL: vpload_nxv8i8:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma86; CHECK-NEXT: vle8.v v8, (a0), v0.t87; CHECK-NEXT: ret88 %load = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)89 ret <vscale x 8 x i8> %load90}91 92define <vscale x 8 x i8> @vpload_nxv8i8_allones_mask(ptr %ptr, i32 zeroext %evl) {93; CHECK-LABEL: vpload_nxv8i8_allones_mask:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma96; CHECK-NEXT: vle8.v v8, (a0)97; CHECK-NEXT: ret98 %load = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)99 ret <vscale x 8 x i8> %load100}101 102define <vscale x 1 x i16> @vpload_nxv1i16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {103; CHECK-LABEL: vpload_nxv1i16:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma106; CHECK-NEXT: vle16.v v8, (a0), v0.t107; CHECK-NEXT: ret108 %load = call <vscale x 1 x i16> @llvm.vp.load.nxv1i16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)109 ret <vscale x 1 x i16> %load110}111 112define <vscale x 2 x i16> @vpload_nxv2i16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {113; CHECK-LABEL: vpload_nxv2i16:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma116; CHECK-NEXT: vle16.v v8, (a0), v0.t117; CHECK-NEXT: ret118 %load = call <vscale x 2 x i16> @llvm.vp.load.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)119 ret <vscale x 2 x i16> %load120}121 122define <vscale x 2 x i16> @vpload_nxv2i16_allones_mask(ptr %ptr, i32 zeroext %evl) {123; CHECK-LABEL: vpload_nxv2i16_allones_mask:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma126; CHECK-NEXT: vle16.v v8, (a0)127; CHECK-NEXT: ret128 %load = call <vscale x 2 x i16> @llvm.vp.load.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)129 ret <vscale x 2 x i16> %load130}131 132define <vscale x 4 x i16> @vpload_nxv4i16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {133; CHECK-LABEL: vpload_nxv4i16:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma136; CHECK-NEXT: vle16.v v8, (a0), v0.t137; CHECK-NEXT: ret138 %load = call <vscale x 4 x i16> @llvm.vp.load.nxv4i16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)139 ret <vscale x 4 x i16> %load140}141 142define <vscale x 8 x i16> @vpload_nxv8i16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {143; CHECK-LABEL: vpload_nxv8i16:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma146; CHECK-NEXT: vle16.v v8, (a0), v0.t147; CHECK-NEXT: ret148 %load = call <vscale x 8 x i16> @llvm.vp.load.nxv8i16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)149 ret <vscale x 8 x i16> %load150}151 152define <vscale x 1 x i32> @vpload_nxv1i32(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {153; CHECK-LABEL: vpload_nxv1i32:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma156; CHECK-NEXT: vle32.v v8, (a0), v0.t157; CHECK-NEXT: ret158 %load = call <vscale x 1 x i32> @llvm.vp.load.nxv1i32.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)159 ret <vscale x 1 x i32> %load160}161 162define <vscale x 2 x i32> @vpload_nxv2i32(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {163; CHECK-LABEL: vpload_nxv2i32:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma166; CHECK-NEXT: vle32.v v8, (a0), v0.t167; CHECK-NEXT: ret168 %load = call <vscale x 2 x i32> @llvm.vp.load.nxv2i32.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)169 ret <vscale x 2 x i32> %load170}171 172define <vscale x 4 x i32> @vpload_nxv4i32(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {173; CHECK-LABEL: vpload_nxv4i32:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma176; CHECK-NEXT: vle32.v v8, (a0), v0.t177; CHECK-NEXT: ret178 %load = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)179 ret <vscale x 4 x i32> %load180}181 182define <vscale x 4 x i32> @vpload_nxv4i32_allones_mask(ptr %ptr, i32 zeroext %evl) {183; CHECK-LABEL: vpload_nxv4i32_allones_mask:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma186; CHECK-NEXT: vle32.v v8, (a0)187; CHECK-NEXT: ret188 %load = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)189 ret <vscale x 4 x i32> %load190}191 192define <vscale x 8 x i32> @vpload_nxv8i32(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {193; CHECK-LABEL: vpload_nxv8i32:194; CHECK: # %bb.0:195; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma196; CHECK-NEXT: vle32.v v8, (a0), v0.t197; CHECK-NEXT: ret198 %load = call <vscale x 8 x i32> @llvm.vp.load.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)199 ret <vscale x 8 x i32> %load200}201 202define <vscale x 1 x i64> @vpload_nxv1i64(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {203; CHECK-LABEL: vpload_nxv1i64:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma206; CHECK-NEXT: vle64.v v8, (a0), v0.t207; CHECK-NEXT: ret208 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)209 ret <vscale x 1 x i64> %load210}211 212define <vscale x 1 x i64> @vpload_nxv1i64_allones_mask(ptr %ptr, i32 zeroext %evl) {213; CHECK-LABEL: vpload_nxv1i64_allones_mask:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma216; CHECK-NEXT: vle64.v v8, (a0)217; CHECK-NEXT: ret218 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)219 ret <vscale x 1 x i64> %load220}221 222define <vscale x 2 x i64> @vpload_nxv2i64(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {223; CHECK-LABEL: vpload_nxv2i64:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma226; CHECK-NEXT: vle64.v v8, (a0), v0.t227; CHECK-NEXT: ret228 %load = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)229 ret <vscale x 2 x i64> %load230}231 232define <vscale x 4 x i64> @vpload_nxv4i64(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {233; CHECK-LABEL: vpload_nxv4i64:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma236; CHECK-NEXT: vle64.v v8, (a0), v0.t237; CHECK-NEXT: ret238 %load = call <vscale x 4 x i64> @llvm.vp.load.nxv4i64.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)239 ret <vscale x 4 x i64> %load240}241 242define <vscale x 8 x i64> @vpload_nxv8i64(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {243; CHECK-LABEL: vpload_nxv8i64:244; CHECK: # %bb.0:245; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma246; CHECK-NEXT: vle64.v v8, (a0), v0.t247; CHECK-NEXT: ret248 %load = call <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)249 ret <vscale x 8 x i64> %load250}251 252define <vscale x 1 x bfloat> @vpload_nxv1bf16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {253; CHECK-LABEL: vpload_nxv1bf16:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma256; CHECK-NEXT: vle16.v v8, (a0), v0.t257; CHECK-NEXT: ret258 %load = call <vscale x 1 x bfloat> @llvm.vp.load.nxv1bf16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)259 ret <vscale x 1 x bfloat> %load260}261 262define <vscale x 2 x bfloat> @vpload_nxv2bf16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {263; CHECK-LABEL: vpload_nxv2bf16:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma266; CHECK-NEXT: vle16.v v8, (a0), v0.t267; CHECK-NEXT: ret268 %load = call <vscale x 2 x bfloat> @llvm.vp.load.nxv2bf16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)269 ret <vscale x 2 x bfloat> %load270}271 272define <vscale x 2 x bfloat> @vpload_nxv2bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {273; CHECK-LABEL: vpload_nxv2bf16_allones_mask:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma276; CHECK-NEXT: vle16.v v8, (a0)277; CHECK-NEXT: ret278 %load = call <vscale x 2 x bfloat> @llvm.vp.load.nxv2bf16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)279 ret <vscale x 2 x bfloat> %load280}281 282define <vscale x 4 x bfloat> @vpload_nxv4bf16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {283; CHECK-LABEL: vpload_nxv4bf16:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma286; CHECK-NEXT: vle16.v v8, (a0), v0.t287; CHECK-NEXT: ret288 %load = call <vscale x 4 x bfloat> @llvm.vp.load.nxv4bf16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)289 ret <vscale x 4 x bfloat> %load290}291 292define <vscale x 8 x bfloat> @vpload_nxv8bf16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {293; CHECK-LABEL: vpload_nxv8bf16:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma296; CHECK-NEXT: vle16.v v8, (a0), v0.t297; CHECK-NEXT: ret298 %load = call <vscale x 8 x bfloat> @llvm.vp.load.nxv8bf16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)299 ret <vscale x 8 x bfloat> %load300}301 302define <vscale x 1 x half> @vpload_nxv1f16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {303; CHECK-LABEL: vpload_nxv1f16:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma306; CHECK-NEXT: vle16.v v8, (a0), v0.t307; CHECK-NEXT: ret308 %load = call <vscale x 1 x half> @llvm.vp.load.nxv1f16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)309 ret <vscale x 1 x half> %load310}311 312define <vscale x 2 x half> @vpload_nxv2f16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {313; CHECK-LABEL: vpload_nxv2f16:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma316; CHECK-NEXT: vle16.v v8, (a0), v0.t317; CHECK-NEXT: ret318 %load = call <vscale x 2 x half> @llvm.vp.load.nxv2f16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)319 ret <vscale x 2 x half> %load320}321 322define <vscale x 2 x half> @vpload_nxv2f16_allones_mask(ptr %ptr, i32 zeroext %evl) {323; CHECK-LABEL: vpload_nxv2f16_allones_mask:324; CHECK: # %bb.0:325; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma326; CHECK-NEXT: vle16.v v8, (a0)327; CHECK-NEXT: ret328 %load = call <vscale x 2 x half> @llvm.vp.load.nxv2f16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)329 ret <vscale x 2 x half> %load330}331 332define <vscale x 4 x half> @vpload_nxv4f16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {333; CHECK-LABEL: vpload_nxv4f16:334; CHECK: # %bb.0:335; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma336; CHECK-NEXT: vle16.v v8, (a0), v0.t337; CHECK-NEXT: ret338 %load = call <vscale x 4 x half> @llvm.vp.load.nxv4f16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)339 ret <vscale x 4 x half> %load340}341 342define <vscale x 8 x half> @vpload_nxv8f16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {343; CHECK-LABEL: vpload_nxv8f16:344; CHECK: # %bb.0:345; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma346; CHECK-NEXT: vle16.v v8, (a0), v0.t347; CHECK-NEXT: ret348 %load = call <vscale x 8 x half> @llvm.vp.load.nxv8f16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)349 ret <vscale x 8 x half> %load350}351 352define <vscale x 1 x float> @vpload_nxv1f32(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {353; CHECK-LABEL: vpload_nxv1f32:354; CHECK: # %bb.0:355; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma356; CHECK-NEXT: vle32.v v8, (a0), v0.t357; CHECK-NEXT: ret358 %load = call <vscale x 1 x float> @llvm.vp.load.nxv1f32.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)359 ret <vscale x 1 x float> %load360}361 362define <vscale x 2 x float> @vpload_nxv2f32(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {363; CHECK-LABEL: vpload_nxv2f32:364; CHECK: # %bb.0:365; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma366; CHECK-NEXT: vle32.v v8, (a0), v0.t367; CHECK-NEXT: ret368 %load = call <vscale x 2 x float> @llvm.vp.load.nxv2f32.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)369 ret <vscale x 2 x float> %load370}371 372define <vscale x 4 x float> @vpload_nxv4f32(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {373; CHECK-LABEL: vpload_nxv4f32:374; CHECK: # %bb.0:375; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma376; CHECK-NEXT: vle32.v v8, (a0), v0.t377; CHECK-NEXT: ret378 %load = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)379 ret <vscale x 4 x float> %load380}381 382define <vscale x 8 x float> @vpload_nxv8f32(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {383; CHECK-LABEL: vpload_nxv8f32:384; CHECK: # %bb.0:385; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma386; CHECK-NEXT: vle32.v v8, (a0), v0.t387; CHECK-NEXT: ret388 %load = call <vscale x 8 x float> @llvm.vp.load.nxv8f32.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)389 ret <vscale x 8 x float> %load390}391 392define <vscale x 8 x float> @vpload_nxv8f32_allones_mask(ptr %ptr, i32 zeroext %evl) {393; CHECK-LABEL: vpload_nxv8f32_allones_mask:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma396; CHECK-NEXT: vle32.v v8, (a0)397; CHECK-NEXT: ret398 %load = call <vscale x 8 x float> @llvm.vp.load.nxv8f32.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)399 ret <vscale x 8 x float> %load400}401 402define <vscale x 1 x double> @vpload_nxv1f64(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {403; CHECK-LABEL: vpload_nxv1f64:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma406; CHECK-NEXT: vle64.v v8, (a0), v0.t407; CHECK-NEXT: ret408 %load = call <vscale x 1 x double> @llvm.vp.load.nxv1f64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)409 ret <vscale x 1 x double> %load410}411 412define <vscale x 2 x double> @vpload_nxv2f64(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {413; CHECK-LABEL: vpload_nxv2f64:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma416; CHECK-NEXT: vle64.v v8, (a0), v0.t417; CHECK-NEXT: ret418 %load = call <vscale x 2 x double> @llvm.vp.load.nxv2f64.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)419 ret <vscale x 2 x double> %load420}421 422define <vscale x 4 x double> @vpload_nxv4f64(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {423; CHECK-LABEL: vpload_nxv4f64:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma426; CHECK-NEXT: vle64.v v8, (a0), v0.t427; CHECK-NEXT: ret428 %load = call <vscale x 4 x double> @llvm.vp.load.nxv4f64.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)429 ret <vscale x 4 x double> %load430}431 432define <vscale x 4 x double> @vpload_nxv4f64_allones_mask(ptr %ptr, i32 zeroext %evl) {433; CHECK-LABEL: vpload_nxv4f64_allones_mask:434; CHECK: # %bb.0:435; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma436; CHECK-NEXT: vle64.v v8, (a0)437; CHECK-NEXT: ret438 %load = call <vscale x 4 x double> @llvm.vp.load.nxv4f64.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)439 ret <vscale x 4 x double> %load440}441 442define <vscale x 8 x double> @vpload_nxv8f64(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {443; CHECK-LABEL: vpload_nxv8f64:444; CHECK: # %bb.0:445; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma446; CHECK-NEXT: vle64.v v8, (a0), v0.t447; CHECK-NEXT: ret448 %load = call <vscale x 8 x double> @llvm.vp.load.nxv8f64.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)449 ret <vscale x 8 x double> %load450}451 452define <vscale x 16 x double> @vpload_nxv16f64(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {453; CHECK-LABEL: vpload_nxv16f64:454; CHECK: # %bb.0:455; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma456; CHECK-NEXT: vmv1r.v v8, v0457; CHECK-NEXT: csrr a2, vlenb458; CHECK-NEXT: sub a3, a1, a2459; CHECK-NEXT: slli a4, a2, 3460; CHECK-NEXT: srli a5, a2, 3461; CHECK-NEXT: vslidedown.vx v0, v0, a5462; CHECK-NEXT: sltu a5, a1, a3463; CHECK-NEXT: addi a5, a5, -1464; CHECK-NEXT: and a3, a5, a3465; CHECK-NEXT: add a4, a0, a4466; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma467; CHECK-NEXT: vle64.v v16, (a4), v0.t468; CHECK-NEXT: bltu a1, a2, .LBB44_2469; CHECK-NEXT: # %bb.1:470; CHECK-NEXT: mv a1, a2471; CHECK-NEXT: .LBB44_2:472; CHECK-NEXT: vmv1r.v v0, v8473; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma474; CHECK-NEXT: vle64.v v8, (a0), v0.t475; CHECK-NEXT: ret476 %load = call <vscale x 16 x double> @llvm.vp.load.nxv16f64.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)477 ret <vscale x 16 x double> %load478}479 480; Note: We can't return <vscale x 17 x double> as that introduces a vector481; store can't yet be legalized through widening. In order to test purely the482; vp.load legalization, manually split it.483 484; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty.485 486define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17 x i1> %m, i32 zeroext %evl) {487; CHECK-LABEL: vpload_nxv17f64:488; CHECK: # %bb.0:489; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma490; CHECK-NEXT: vmv1r.v v8, v0491; CHECK-NEXT: csrr a3, vlenb492; CHECK-NEXT: slli a5, a3, 1493; CHECK-NEXT: mv a4, a2494; CHECK-NEXT: bltu a2, a5, .LBB45_2495; CHECK-NEXT: # %bb.1:496; CHECK-NEXT: mv a4, a5497; CHECK-NEXT: .LBB45_2:498; CHECK-NEXT: sub a6, a4, a3499; CHECK-NEXT: slli a7, a3, 3500; CHECK-NEXT: sltu t0, a4, a6501; CHECK-NEXT: addi t0, t0, -1502; CHECK-NEXT: and a6, t0, a6503; CHECK-NEXT: srli t0, a3, 3504; CHECK-NEXT: sub t1, a2, a5505; CHECK-NEXT: add a5, a0, a7506; CHECK-NEXT: sltu a2, a2, t1507; CHECK-NEXT: addi a2, a2, -1508; CHECK-NEXT: and a2, a2, t1509; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma510; CHECK-NEXT: vslidedown.vx v0, v8, t0511; CHECK-NEXT: bltu a2, a3, .LBB45_4512; CHECK-NEXT: # %bb.3:513; CHECK-NEXT: mv a2, a3514; CHECK-NEXT: .LBB45_4:515; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma516; CHECK-NEXT: vle64.v v16, (a5), v0.t517; CHECK-NEXT: slli a5, a3, 4518; CHECK-NEXT: srli a6, a3, 2519; CHECK-NEXT: vsetvli a7, zero, e8, mf2, ta, ma520; CHECK-NEXT: vslidedown.vx v0, v8, a6521; CHECK-NEXT: add a5, a0, a5522; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma523; CHECK-NEXT: vle64.v v24, (a5), v0.t524; CHECK-NEXT: bltu a4, a3, .LBB45_6525; CHECK-NEXT: # %bb.5:526; CHECK-NEXT: mv a4, a3527; CHECK-NEXT: .LBB45_6:528; CHECK-NEXT: vmv1r.v v0, v8529; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma530; CHECK-NEXT: vle64.v v8, (a0), v0.t531; CHECK-NEXT: vs1r.v v24, (a1)532; CHECK-NEXT: ret533 %load = call <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0(ptr %ptr, <vscale x 17 x i1> %m, i32 %evl)534 %lo = call <vscale x 16 x double> @llvm.vector.extract.nxv16f64(<vscale x 17 x double> %load, i64 0)535 %hi = call <vscale x 1 x double> @llvm.vector.extract.nxv1f64(<vscale x 17 x double> %load, i64 16)536 store <vscale x 1 x double> %hi, ptr %out537 ret <vscale x 16 x double> %lo538}539 540define <vscale x 1 x i64> @unaligned_vpload_nxv1i64_allones_mask(<vscale x 1 x i64>* %ptr, i32 zeroext %evl) {541; CHECK-LABEL: unaligned_vpload_nxv1i64_allones_mask:542; CHECK: # %bb.0:543; CHECK-NEXT: slli a1, a1, 3544; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma545; CHECK-NEXT: vle8.v v8, (a0)546; CHECK-NEXT: ret547 %a = insertelement <vscale x 1 x i1> poison, i1 true, i32 0548 %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer549 %load = call <vscale x 1 x i64> @llvm.vp.load.nxv1i64.p0(<vscale x 1 x i64>* align 1 %ptr, <vscale x 1 x i1> %b, i32 %evl)550 ret <vscale x 1 x i64> %load551}552 553define <vscale x 8 x i8> @vpload_all_active_nxv8i8(ptr %ptr) {554; CHECK-LABEL: vpload_all_active_nxv8i8:555; CHECK: # %bb.0:556; CHECK-NEXT: vl1r.v v8, (a0)557; CHECK-NEXT: ret558 %vscale = call i32 @llvm.vscale()559 %evl = mul i32 %vscale, 8560 %load = call <vscale x 8 x i8> @llvm.vp.load.nxv8i8.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)561 ret <vscale x 8 x i8> %load562}563