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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define { <vscale x 1 x i8>, i32 } @vploadff_nxv1i8(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vploadff_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma15; CHECK-NEXT: vle8ff.v v8, (a0), v0.t16; CHECK-NEXT: csrr a0, vl17; CHECK-NEXT: ret18 %load = call { <vscale x 1 x i8>, i32 } @llvm.vp.load.ff.nxv1i8.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)19 ret { <vscale x 1 x i8>, i32 } %load20}21 22define { <vscale x 1 x i8>, i32 } @vploadff_nxv1i8_allones_mask(ptr %ptr, i32 zeroext %evl) {23; CHECK-LABEL: vploadff_nxv1i8_allones_mask:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma26; CHECK-NEXT: vle8ff.v v8, (a0)27; CHECK-NEXT: csrr a0, vl28; CHECK-NEXT: ret29 %load = call { <vscale x 1 x i8>, i32 } @llvm.vp.load.ff.nxv1i8.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)30 ret { <vscale x 1 x i8>, i32 } %load31}32 33define { <vscale x 2 x i8>, i32 } @vploadff_nxv2i8(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vploadff_nxv2i8:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma37; CHECK-NEXT: vle8ff.v v8, (a0), v0.t38; CHECK-NEXT: csrr a0, vl39; CHECK-NEXT: ret40 %load = call { <vscale x 2 x i8>, i32 } @llvm.vp.load.ff.nxv2i8.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)41 ret { <vscale x 2 x i8>, i32 } %load42}43 44define { <vscale x 2 x i8>, i32 } @vploadff_nxv2i8_allones_mask(ptr %ptr, i32 zeroext %evl) {45; CHECK-LABEL: vploadff_nxv2i8_allones_mask:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma48; CHECK-NEXT: vle8ff.v v8, (a0)49; CHECK-NEXT: csrr a0, vl50; CHECK-NEXT: ret51 %load = call { <vscale x 2 x i8>, i32 } @llvm.vp.load.ff.nxv2i8.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)52 ret { <vscale x 2 x i8>, i32 } %load53}54 55define { <vscale x 4 x i8>, i32 } @vploadff_nxv4i8(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {56; CHECK-LABEL: vploadff_nxv4i8:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma59; CHECK-NEXT: vle8ff.v v8, (a0), v0.t60; CHECK-NEXT: csrr a0, vl61; CHECK-NEXT: ret62 %load = call { <vscale x 4 x i8>, i32 } @llvm.vp.load.ff.nxv4i8.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)63 ret { <vscale x 4 x i8>, i32 } %load64}65 66define { <vscale x 4 x i8>, i32 } @vploadff_nxv4i8_allones_mask(ptr %ptr, i32 zeroext %evl) {67; CHECK-LABEL: vploadff_nxv4i8_allones_mask:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma70; CHECK-NEXT: vle8ff.v v8, (a0)71; CHECK-NEXT: csrr a0, vl72; CHECK-NEXT: ret73 %load = call { <vscale x 4 x i8>, i32 } @llvm.vp.load.ff.nxv4i8.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)74 ret { <vscale x 4 x i8>, i32 } %load75}76 77define { <vscale x 8 x i8>, i32 } @vploadff_nxv8i8(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {78; CHECK-LABEL: vploadff_nxv8i8:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma81; CHECK-NEXT: vle8ff.v v8, (a0), v0.t82; CHECK-NEXT: csrr a0, vl83; CHECK-NEXT: ret84 %load = call { <vscale x 8 x i8>, i32 } @llvm.vp.load.ff.nxv8i8.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)85 ret { <vscale x 8 x i8>, i32 } %load86}87 88define { <vscale x 8 x i8>, i32 } @vploadff_nxv8i8_allones_mask(ptr %ptr, i32 zeroext %evl) {89; CHECK-LABEL: vploadff_nxv8i8_allones_mask:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma92; CHECK-NEXT: vle8ff.v v8, (a0)93; CHECK-NEXT: csrr a0, vl94; CHECK-NEXT: ret95 %load = call { <vscale x 8 x i8>, i32 } @llvm.vp.load.ff.nxv8i8.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)96 ret { <vscale x 8 x i8>, i32 } %load97}98 99define { <vscale x 16 x i8>, i32 } @vploadff_nxv16i8(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {100; CHECK-LABEL: vploadff_nxv16i8:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma103; CHECK-NEXT: vle8ff.v v8, (a0), v0.t104; CHECK-NEXT: csrr a0, vl105; CHECK-NEXT: ret106 %load = call { <vscale x 16 x i8>, i32 } @llvm.vp.load.ff.nxv16i8.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)107 ret { <vscale x 16 x i8>, i32 } %load108}109 110define { <vscale x 16 x i8>, i32 } @vploadff_nxv16i8_allones_mask(ptr %ptr, i32 zeroext %evl) {111; CHECK-LABEL: vploadff_nxv16i8_allones_mask:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma114; CHECK-NEXT: vle8ff.v v8, (a0)115; CHECK-NEXT: csrr a0, vl116; CHECK-NEXT: ret117 %load = call { <vscale x 16 x i8>, i32 } @llvm.vp.load.ff.nxv16i8.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)118 ret { <vscale x 16 x i8>, i32 } %load119}120 121define { <vscale x 32 x i8>, i32 } @vploadff_nxv32i8(ptr %ptr, <vscale x 32 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vploadff_nxv32i8:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma125; CHECK-NEXT: vle8ff.v v8, (a0), v0.t126; CHECK-NEXT: csrr a0, vl127; CHECK-NEXT: ret128 %load = call { <vscale x 32 x i8>, i32 } @llvm.vp.load.ff.nxv32i8.p0(ptr %ptr, <vscale x 32 x i1> %m, i32 %evl)129 ret { <vscale x 32 x i8>, i32 } %load130}131 132define { <vscale x 32 x i8>, i32 } @vploadff_nxv32i8_allones_mask(ptr %ptr, i32 zeroext %evl) {133; CHECK-LABEL: vploadff_nxv32i8_allones_mask:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma136; CHECK-NEXT: vle8ff.v v8, (a0)137; CHECK-NEXT: csrr a0, vl138; CHECK-NEXT: ret139 %load = call { <vscale x 32 x i8>, i32 } @llvm.vp.load.ff.nxv32i8.p0(ptr %ptr, <vscale x 32 x i1> splat (i1 true), i32 %evl)140 ret { <vscale x 32 x i8>, i32 } %load141}142 143define { <vscale x 64 x i8>, i32 } @vploadff_nxv64i8(ptr %ptr, <vscale x 64 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: vploadff_nxv64i8:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma147; CHECK-NEXT: vle8ff.v v8, (a0), v0.t148; CHECK-NEXT: csrr a0, vl149; CHECK-NEXT: ret150 %load = call { <vscale x 64 x i8>, i32 } @llvm.vp.load.ff.nxv64i8.p0(ptr %ptr, <vscale x 64 x i1> %m, i32 %evl)151 ret { <vscale x 64 x i8>, i32 } %load152}153 154define { <vscale x 64 x i8>, i32 } @vploadff_nxv64i8_allones_mask(ptr %ptr, i32 zeroext %evl) {155; CHECK-LABEL: vploadff_nxv64i8_allones_mask:156; CHECK: # %bb.0:157; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma158; CHECK-NEXT: vle8ff.v v8, (a0)159; CHECK-NEXT: csrr a0, vl160; CHECK-NEXT: ret161 %load = call { <vscale x 64 x i8>, i32 } @llvm.vp.load.ff.nxv64i8.p0(ptr %ptr, <vscale x 64 x i1> splat (i1 true), i32 %evl)162 ret { <vscale x 64 x i8>, i32 } %load163}164 165define <vscale x 128 x i8> @vploadff_nxv128i8(ptr %ptr, ptr %evl_out, <vscale x 128 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: vploadff_nxv128i8:167; CHECK: # %bb.0:168; CHECK-NEXT: csrr a3, vlenb169; CHECK-NEXT: slli a3, a3, 3170; CHECK-NEXT: bltu a2, a3, .LBB14_2171; CHECK-NEXT: # %bb.1:172; CHECK-NEXT: mv a2, a3173; CHECK-NEXT: .LBB14_2:174; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma175; CHECK-NEXT: vle8ff.v v8, (a0), v0.t176; CHECK-NEXT: csrr a0, vl177; CHECK-NEXT: sw a0, 0(a1)178; CHECK-NEXT: ret179 %load = call { <vscale x 128 x i8>, i32 } @llvm.vp.load.ff.nxv128i8.p0(ptr %ptr, <vscale x 128 x i1> %m, i32 %evl)180 %result0 = extractvalue { <vscale x 128 x i8>, i32 } %load, 0181 %result1 = extractvalue { <vscale x 128 x i8>, i32 } %load, 1182 store i32 %result1, ptr %evl_out183 ret <vscale x 128 x i8> %result0184}185 186define <vscale x 128 x i8> @vploadff_nxv128i8_allones_mask(ptr %ptr, ptr %evl_out, i32 zeroext %evl) {187; CHECK-LABEL: vploadff_nxv128i8_allones_mask:188; CHECK: # %bb.0:189; CHECK-NEXT: csrr a3, vlenb190; CHECK-NEXT: slli a3, a3, 3191; CHECK-NEXT: bltu a2, a3, .LBB15_2192; CHECK-NEXT: # %bb.1:193; CHECK-NEXT: mv a2, a3194; CHECK-NEXT: .LBB15_2:195; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma196; CHECK-NEXT: vle8ff.v v8, (a0)197; CHECK-NEXT: csrr a0, vl198; CHECK-NEXT: sw a0, 0(a1)199; CHECK-NEXT: ret200 %load = call { <vscale x 128 x i8>, i32 } @llvm.vp.load.ff.nxv128i8.p0(ptr %ptr, <vscale x 128 x i1> splat (i1 true), i32 %evl)201 %result0 = extractvalue { <vscale x 128 x i8>, i32 } %load, 0202 %result1 = extractvalue { <vscale x 128 x i8>, i32 } %load, 1203 store i32 %result1, ptr %evl_out204 ret <vscale x 128 x i8> %result0205}206 207define { <vscale x 1 x i16>, i32 } @vploadff_nxv1i16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {208; CHECK-LABEL: vploadff_nxv1i16:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma211; CHECK-NEXT: vle16ff.v v8, (a0), v0.t212; CHECK-NEXT: csrr a0, vl213; CHECK-NEXT: ret214 %load = call { <vscale x 1 x i16>, i32 } @llvm.vp.load.ff.nxv1i16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)215 ret { <vscale x 1 x i16>, i32 } %load216}217 218define { <vscale x 1 x i16>, i32 } @vploadff_nxv1i16_allones_mask(ptr %ptr, i32 zeroext %evl) {219; CHECK-LABEL: vploadff_nxv1i16_allones_mask:220; CHECK: # %bb.0:221; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma222; CHECK-NEXT: vle16ff.v v8, (a0)223; CHECK-NEXT: csrr a0, vl224; CHECK-NEXT: ret225 %load = call { <vscale x 1 x i16>, i32 } @llvm.vp.load.ff.nxv1i16.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)226 ret { <vscale x 1 x i16>, i32 } %load227}228 229define { <vscale x 2 x i16>, i32 } @vploadff_nxv2i16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {230; CHECK-LABEL: vploadff_nxv2i16:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma233; CHECK-NEXT: vle16ff.v v8, (a0), v0.t234; CHECK-NEXT: csrr a0, vl235; CHECK-NEXT: ret236 %load = call { <vscale x 2 x i16>, i32 } @llvm.vp.load.ff.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)237 ret { <vscale x 2 x i16>, i32 } %load238}239 240define { <vscale x 2 x i16>, i32 } @vploadff_nxv2i16_allones_mask(ptr %ptr, i32 zeroext %evl) {241; CHECK-LABEL: vploadff_nxv2i16_allones_mask:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma244; CHECK-NEXT: vle16ff.v v8, (a0)245; CHECK-NEXT: csrr a0, vl246; CHECK-NEXT: ret247 %load = call { <vscale x 2 x i16>, i32 } @llvm.vp.load.ff.nxv2i16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)248 ret { <vscale x 2 x i16>, i32 } %load249}250 251define { <vscale x 4 x i16>, i32 } @vploadff_nxv4i16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vploadff_nxv4i16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma255; CHECK-NEXT: vle16ff.v v8, (a0), v0.t256; CHECK-NEXT: csrr a0, vl257; CHECK-NEXT: ret258 %load = call { <vscale x 4 x i16>, i32 } @llvm.vp.load.ff.nxv4i16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)259 ret { <vscale x 4 x i16>, i32 } %load260}261 262define { <vscale x 4 x i16>, i32 } @vploadff_nxv4i16_allones_mask(ptr %ptr, i32 zeroext %evl) {263; CHECK-LABEL: vploadff_nxv4i16_allones_mask:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma266; CHECK-NEXT: vle16ff.v v8, (a0)267; CHECK-NEXT: csrr a0, vl268; CHECK-NEXT: ret269 %load = call { <vscale x 4 x i16>, i32 } @llvm.vp.load.ff.nxv4i16.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)270 ret { <vscale x 4 x i16>, i32 } %load271}272 273define { <vscale x 8 x i16>, i32 } @vploadff_nxv8i16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {274; CHECK-LABEL: vploadff_nxv8i16:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma277; CHECK-NEXT: vle16ff.v v8, (a0), v0.t278; CHECK-NEXT: csrr a0, vl279; CHECK-NEXT: ret280 %load = call { <vscale x 8 x i16>, i32 } @llvm.vp.load.ff.nxv8i16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)281 ret { <vscale x 8 x i16>, i32 } %load282}283 284define { <vscale x 8 x i16>, i32 } @vploadff_nxv8i16_allones_mask(ptr %ptr, i32 zeroext %evl) {285; CHECK-LABEL: vploadff_nxv8i16_allones_mask:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma288; CHECK-NEXT: vle16ff.v v8, (a0)289; CHECK-NEXT: csrr a0, vl290; CHECK-NEXT: ret291 %load = call { <vscale x 8 x i16>, i32 } @llvm.vp.load.ff.nxv8i16.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)292 ret { <vscale x 8 x i16>, i32 } %load293}294 295define { <vscale x 16 x i16>, i32 } @vploadff_nxv16i16(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {296; CHECK-LABEL: vploadff_nxv16i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma299; CHECK-NEXT: vle16ff.v v8, (a0), v0.t300; CHECK-NEXT: csrr a0, vl301; CHECK-NEXT: ret302 %load = call { <vscale x 16 x i16>, i32 } @llvm.vp.load.ff.nxv16i16.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)303 ret { <vscale x 16 x i16>, i32 } %load304}305 306define { <vscale x 16 x i16>, i32 } @vploadff_nxv16i16_allones_mask(ptr %ptr, i32 zeroext %evl) {307; CHECK-LABEL: vploadff_nxv16i16_allones_mask:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma310; CHECK-NEXT: vle16ff.v v8, (a0)311; CHECK-NEXT: csrr a0, vl312; CHECK-NEXT: ret313 %load = call { <vscale x 16 x i16>, i32 } @llvm.vp.load.ff.nxv16i16.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)314 ret { <vscale x 16 x i16>, i32 } %load315}316 317define { <vscale x 32 x i16>, i32 } @vploadff_nxv32i16(ptr %ptr, <vscale x 32 x i1> %m, i32 zeroext %evl) {318; CHECK-LABEL: vploadff_nxv32i16:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma321; CHECK-NEXT: vle16ff.v v8, (a0), v0.t322; CHECK-NEXT: csrr a0, vl323; CHECK-NEXT: ret324 %load = call { <vscale x 32 x i16>, i32 } @llvm.vp.load.ff.nxv32i16.p0(ptr %ptr, <vscale x 32 x i1> %m, i32 %evl)325 ret { <vscale x 32 x i16>, i32 } %load326}327 328define { <vscale x 32 x i16>, i32 } @vploadff_nxv32i16_allones_mask(ptr %ptr, i32 zeroext %evl) {329; CHECK-LABEL: vploadff_nxv32i16_allones_mask:330; CHECK: # %bb.0:331; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma332; CHECK-NEXT: vle16ff.v v8, (a0)333; CHECK-NEXT: csrr a0, vl334; CHECK-NEXT: ret335 %load = call { <vscale x 32 x i16>, i32 } @llvm.vp.load.ff.nxv32i16.p0(ptr %ptr, <vscale x 32 x i1> splat (i1 true), i32 %evl)336 ret { <vscale x 32 x i16>, i32 } %load337}338 339define { <vscale x 1 x i32>, i32 } @vploadff_nxv1i32(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {340; CHECK-LABEL: vploadff_nxv1i32:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma343; CHECK-NEXT: vle32ff.v v8, (a0), v0.t344; CHECK-NEXT: csrr a0, vl345; CHECK-NEXT: ret346 %load = call { <vscale x 1 x i32>, i32 } @llvm.vp.load.ff.nxv1i32.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)347 ret { <vscale x 1 x i32>, i32 } %load348}349 350define { <vscale x 1 x i32>, i32 } @vploadff_nxv1i32_allones_mask(ptr %ptr, i32 zeroext %evl) {351; CHECK-LABEL: vploadff_nxv1i32_allones_mask:352; CHECK: # %bb.0:353; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma354; CHECK-NEXT: vle32ff.v v8, (a0)355; CHECK-NEXT: csrr a0, vl356; CHECK-NEXT: ret357 %load = call { <vscale x 1 x i32>, i32 } @llvm.vp.load.ff.nxv1i32.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)358 ret { <vscale x 1 x i32>, i32 } %load359}360 361define { <vscale x 2 x i32>, i32 } @vploadff_nxv2i32(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {362; CHECK-LABEL: vploadff_nxv2i32:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma365; CHECK-NEXT: vle32ff.v v8, (a0), v0.t366; CHECK-NEXT: csrr a0, vl367; CHECK-NEXT: ret368 %load = call { <vscale x 2 x i32>, i32 } @llvm.vp.load.ff.nxv2i32.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)369 ret { <vscale x 2 x i32>, i32 } %load370}371 372define { <vscale x 2 x i32>, i32 } @vploadff_nxv2i32_allones_mask(ptr %ptr, i32 zeroext %evl) {373; CHECK-LABEL: vploadff_nxv2i32_allones_mask:374; CHECK: # %bb.0:375; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma376; CHECK-NEXT: vle32ff.v v8, (a0)377; CHECK-NEXT: csrr a0, vl378; CHECK-NEXT: ret379 %load = call { <vscale x 2 x i32>, i32 } @llvm.vp.load.ff.nxv2i32.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)380 ret { <vscale x 2 x i32>, i32 } %load381}382 383define { <vscale x 4 x i32>, i32 } @vploadff_nxv4i32(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {384; CHECK-LABEL: vploadff_nxv4i32:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma387; CHECK-NEXT: vle32ff.v v8, (a0), v0.t388; CHECK-NEXT: csrr a0, vl389; CHECK-NEXT: ret390 %load = call { <vscale x 4 x i32>, i32 } @llvm.vp.load.ff.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)391 ret { <vscale x 4 x i32>, i32 } %load392}393 394define { <vscale x 4 x i32>, i32 } @vploadff_nxv4i32_allones_mask(ptr %ptr, i32 zeroext %evl) {395; CHECK-LABEL: vploadff_nxv4i32_allones_mask:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma398; CHECK-NEXT: vle32ff.v v8, (a0)399; CHECK-NEXT: csrr a0, vl400; CHECK-NEXT: ret401 %load = call { <vscale x 4 x i32>, i32 } @llvm.vp.load.ff.nxv4i32.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)402 ret { <vscale x 4 x i32>, i32 } %load403}404 405define { <vscale x 8 x i32>, i32 } @vploadff_nxv8i32(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {406; CHECK-LABEL: vploadff_nxv8i32:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma409; CHECK-NEXT: vle32ff.v v8, (a0), v0.t410; CHECK-NEXT: csrr a0, vl411; CHECK-NEXT: ret412 %load = call { <vscale x 8 x i32>, i32 } @llvm.vp.load.ff.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)413 ret { <vscale x 8 x i32>, i32 } %load414}415 416define { <vscale x 8 x i32>, i32 } @vploadff_nxv8i32_allones_mask(ptr %ptr, i32 zeroext %evl) {417; CHECK-LABEL: vploadff_nxv8i32_allones_mask:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma420; CHECK-NEXT: vle32ff.v v8, (a0)421; CHECK-NEXT: csrr a0, vl422; CHECK-NEXT: ret423 %load = call { <vscale x 8 x i32>, i32 } @llvm.vp.load.ff.nxv8i32.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)424 ret { <vscale x 8 x i32>, i32 } %load425}426 427define { <vscale x 16 x i32>, i32 } @vploadff_nxv16i32(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {428; CHECK-LABEL: vploadff_nxv16i32:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma431; CHECK-NEXT: vle32ff.v v8, (a0), v0.t432; CHECK-NEXT: csrr a0, vl433; CHECK-NEXT: ret434 %load = call { <vscale x 16 x i32>, i32 } @llvm.vp.load.ff.nxv16i32.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)435 ret { <vscale x 16 x i32>, i32 } %load436}437 438define { <vscale x 16 x i32>, i32 } @vploadff_nxv16i32_allones_mask(ptr %ptr, i32 zeroext %evl) {439; CHECK-LABEL: vploadff_nxv16i32_allones_mask:440; CHECK: # %bb.0:441; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma442; CHECK-NEXT: vle32ff.v v8, (a0)443; CHECK-NEXT: csrr a0, vl444; CHECK-NEXT: ret445 %load = call { <vscale x 16 x i32>, i32 } @llvm.vp.load.ff.nxv16i32.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)446 ret { <vscale x 16 x i32>, i32 } %load447}448 449define { <vscale x 1 x i64>, i32 } @vploadff_nxv1i64(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {450; CHECK-LABEL: vploadff_nxv1i64:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma453; CHECK-NEXT: vle64ff.v v8, (a0), v0.t454; CHECK-NEXT: csrr a0, vl455; CHECK-NEXT: ret456 %load = call { <vscale x 1 x i64>, i32 } @llvm.vp.load.ff.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)457 ret { <vscale x 1 x i64>, i32 } %load458}459 460define { <vscale x 1 x i64>, i32 } @vploadff_nxv1i64_allones_mask(ptr %ptr, i32 zeroext %evl) {461; CHECK-LABEL: vploadff_nxv1i64_allones_mask:462; CHECK: # %bb.0:463; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma464; CHECK-NEXT: vle64ff.v v8, (a0)465; CHECK-NEXT: csrr a0, vl466; CHECK-NEXT: ret467 %load = call { <vscale x 1 x i64>, i32 } @llvm.vp.load.ff.nxv1i64.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)468 ret { <vscale x 1 x i64>, i32 } %load469}470 471define { <vscale x 2 x i64>, i32 } @vploadff_nxv2i64(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {472; CHECK-LABEL: vploadff_nxv2i64:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma475; CHECK-NEXT: vle64ff.v v8, (a0), v0.t476; CHECK-NEXT: csrr a0, vl477; CHECK-NEXT: ret478 %load = call { <vscale x 2 x i64>, i32 } @llvm.vp.load.ff.nxv2i64.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)479 ret { <vscale x 2 x i64>, i32 } %load480}481 482define { <vscale x 2 x i64>, i32 } @vploadff_nxv2i64_allones_mask(ptr %ptr, i32 zeroext %evl) {483; CHECK-LABEL: vploadff_nxv2i64_allones_mask:484; CHECK: # %bb.0:485; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma486; CHECK-NEXT: vle64ff.v v8, (a0)487; CHECK-NEXT: csrr a0, vl488; CHECK-NEXT: ret489 %load = call { <vscale x 2 x i64>, i32 } @llvm.vp.load.ff.nxv2i64.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)490 ret { <vscale x 2 x i64>, i32 } %load491}492 493define { <vscale x 4 x i64>, i32 } @vploadff_nxv4i64(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {494; CHECK-LABEL: vploadff_nxv4i64:495; CHECK: # %bb.0:496; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma497; CHECK-NEXT: vle64ff.v v8, (a0), v0.t498; CHECK-NEXT: csrr a0, vl499; CHECK-NEXT: ret500 %load = call { <vscale x 4 x i64>, i32 } @llvm.vp.load.ff.nxv4i64.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)501 ret { <vscale x 4 x i64>, i32 } %load502}503 504define { <vscale x 4 x i64>, i32 } @vploadff_nxv4i64_allones_mask(ptr %ptr, i32 zeroext %evl) {505; CHECK-LABEL: vploadff_nxv4i64_allones_mask:506; CHECK: # %bb.0:507; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma508; CHECK-NEXT: vle64ff.v v8, (a0)509; CHECK-NEXT: csrr a0, vl510; CHECK-NEXT: ret511 %load = call { <vscale x 4 x i64>, i32 } @llvm.vp.load.ff.nxv4i64.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)512 ret { <vscale x 4 x i64>, i32 } %load513}514 515define { <vscale x 8 x i64>, i32 } @vploadff_nxv8i64(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {516; CHECK-LABEL: vploadff_nxv8i64:517; CHECK: # %bb.0:518; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma519; CHECK-NEXT: vle64ff.v v8, (a0), v0.t520; CHECK-NEXT: csrr a0, vl521; CHECK-NEXT: ret522 %load = call { <vscale x 8 x i64>, i32 } @llvm.vp.load.ff.nxv8i64.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)523 ret { <vscale x 8 x i64>, i32 } %load524}525 526define { <vscale x 8 x i64>, i32 } @vploadff_nxv8i64_allones_mask(ptr %ptr, i32 zeroext %evl) {527; CHECK-LABEL: vploadff_nxv8i64_allones_mask:528; CHECK: # %bb.0:529; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma530; CHECK-NEXT: vle64ff.v v8, (a0)531; CHECK-NEXT: csrr a0, vl532; CHECK-NEXT: ret533 %load = call { <vscale x 8 x i64>, i32 } @llvm.vp.load.ff.nxv8i64.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)534 ret { <vscale x 8 x i64>, i32 } %load535}536 537define { <vscale x 1 x half>, i32 } @vploadff_nxv1f16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {538; CHECK-LABEL: vploadff_nxv1f16:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma541; CHECK-NEXT: vle16ff.v v8, (a0), v0.t542; CHECK-NEXT: csrr a0, vl543; CHECK-NEXT: ret544 %load = call { <vscale x 1 x half>, i32 } @llvm.vp.load.ff.nxv1f16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)545 ret { <vscale x 1 x half>, i32 } %load546}547 548define { <vscale x 1 x half>, i32 } @vploadff_nxv1f16_allones_mask(ptr %ptr, i32 zeroext %evl) {549; CHECK-LABEL: vploadff_nxv1f16_allones_mask:550; CHECK: # %bb.0:551; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma552; CHECK-NEXT: vle16ff.v v8, (a0)553; CHECK-NEXT: csrr a0, vl554; CHECK-NEXT: ret555 %load = call { <vscale x 1 x half>, i32 } @llvm.vp.load.ff.nxv1f16.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)556 ret { <vscale x 1 x half>, i32 } %load557}558 559define { <vscale x 2 x half>, i32 } @vploadff_nxv2f16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {560; CHECK-LABEL: vploadff_nxv2f16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma563; CHECK-NEXT: vle16ff.v v8, (a0), v0.t564; CHECK-NEXT: csrr a0, vl565; CHECK-NEXT: ret566 %load = call { <vscale x 2 x half>, i32 } @llvm.vp.load.ff.nxv2f16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)567 ret { <vscale x 2 x half>, i32 } %load568}569 570define { <vscale x 2 x half>, i32 } @vploadff_nxv2f16_allones_mask(ptr %ptr, i32 zeroext %evl) {571; CHECK-LABEL: vploadff_nxv2f16_allones_mask:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma574; CHECK-NEXT: vle16ff.v v8, (a0)575; CHECK-NEXT: csrr a0, vl576; CHECK-NEXT: ret577 %load = call { <vscale x 2 x half>, i32 } @llvm.vp.load.ff.nxv2f16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)578 ret { <vscale x 2 x half>, i32 } %load579}580 581define { <vscale x 4 x half>, i32 } @vploadff_nxv4f16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {582; CHECK-LABEL: vploadff_nxv4f16:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma585; CHECK-NEXT: vle16ff.v v8, (a0), v0.t586; CHECK-NEXT: csrr a0, vl587; CHECK-NEXT: ret588 %load = call { <vscale x 4 x half>, i32 } @llvm.vp.load.ff.nxv4f16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)589 ret { <vscale x 4 x half>, i32 } %load590}591 592define { <vscale x 4 x half>, i32 } @vploadff_nxv4f16_allones_mask(ptr %ptr, i32 zeroext %evl) {593; CHECK-LABEL: vploadff_nxv4f16_allones_mask:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma596; CHECK-NEXT: vle16ff.v v8, (a0)597; CHECK-NEXT: csrr a0, vl598; CHECK-NEXT: ret599 %load = call { <vscale x 4 x half>, i32 } @llvm.vp.load.ff.nxv4f16.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)600 ret { <vscale x 4 x half>, i32 } %load601}602 603define { <vscale x 8 x half>, i32 } @vploadff_nxv8f16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {604; CHECK-LABEL: vploadff_nxv8f16:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma607; CHECK-NEXT: vle16ff.v v8, (a0), v0.t608; CHECK-NEXT: csrr a0, vl609; CHECK-NEXT: ret610 %load = call { <vscale x 8 x half>, i32 } @llvm.vp.load.ff.nxv8f16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)611 ret { <vscale x 8 x half>, i32 } %load612}613 614define { <vscale x 8 x half>, i32 } @vploadff_nxv8f16_allones_mask(ptr %ptr, i32 zeroext %evl) {615; CHECK-LABEL: vploadff_nxv8f16_allones_mask:616; CHECK: # %bb.0:617; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma618; CHECK-NEXT: vle16ff.v v8, (a0)619; CHECK-NEXT: csrr a0, vl620; CHECK-NEXT: ret621 %load = call { <vscale x 8 x half>, i32 } @llvm.vp.load.ff.nxv8f16.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)622 ret { <vscale x 8 x half>, i32 } %load623}624 625define { <vscale x 16 x half>, i32 } @vploadff_nxv16f16(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {626; CHECK-LABEL: vploadff_nxv16f16:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma629; CHECK-NEXT: vle16ff.v v8, (a0), v0.t630; CHECK-NEXT: csrr a0, vl631; CHECK-NEXT: ret632 %load = call { <vscale x 16 x half>, i32 } @llvm.vp.load.ff.nxv16f16.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)633 ret { <vscale x 16 x half>, i32 } %load634}635 636define { <vscale x 16 x half>, i32 } @vploadff_nxv16f16_allones_mask(ptr %ptr, i32 zeroext %evl) {637; CHECK-LABEL: vploadff_nxv16f16_allones_mask:638; CHECK: # %bb.0:639; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma640; CHECK-NEXT: vle16ff.v v8, (a0)641; CHECK-NEXT: csrr a0, vl642; CHECK-NEXT: ret643 %load = call { <vscale x 16 x half>, i32 } @llvm.vp.load.ff.nxv16f16.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)644 ret { <vscale x 16 x half>, i32 } %load645}646 647define { <vscale x 32 x half>, i32 } @vploadff_nxv32f16(ptr %ptr, <vscale x 32 x i1> %m, i32 zeroext %evl) {648; CHECK-LABEL: vploadff_nxv32f16:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma651; CHECK-NEXT: vle16ff.v v8, (a0), v0.t652; CHECK-NEXT: csrr a0, vl653; CHECK-NEXT: ret654 %load = call { <vscale x 32 x half>, i32 } @llvm.vp.load.ff.nxv32f16.p0(ptr %ptr, <vscale x 32 x i1> %m, i32 %evl)655 ret { <vscale x 32 x half>, i32 } %load656}657 658define { <vscale x 32 x half>, i32 } @vploadff_nxv32f16_allones_mask(ptr %ptr, i32 zeroext %evl) {659; CHECK-LABEL: vploadff_nxv32f16_allones_mask:660; CHECK: # %bb.0:661; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma662; CHECK-NEXT: vle16ff.v v8, (a0)663; CHECK-NEXT: csrr a0, vl664; CHECK-NEXT: ret665 %load = call { <vscale x 32 x half>, i32 } @llvm.vp.load.ff.nxv32f16.p0(ptr %ptr, <vscale x 32 x i1> splat (i1 true), i32 %evl)666 ret { <vscale x 32 x half>, i32 } %load667}668 669define { <vscale x 1 x float>, i32 } @vploadff_nxv1f32(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {670; CHECK-LABEL: vploadff_nxv1f32:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma673; CHECK-NEXT: vle32ff.v v8, (a0), v0.t674; CHECK-NEXT: csrr a0, vl675; CHECK-NEXT: ret676 %load = call { <vscale x 1 x float>, i32 } @llvm.vp.load.ff.nxv1f32.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)677 ret { <vscale x 1 x float>, i32 } %load678}679 680define { <vscale x 1 x float>, i32 } @vploadff_nxv1f32_allones_mask(ptr %ptr, i32 zeroext %evl) {681; CHECK-LABEL: vploadff_nxv1f32_allones_mask:682; CHECK: # %bb.0:683; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma684; CHECK-NEXT: vle32ff.v v8, (a0)685; CHECK-NEXT: csrr a0, vl686; CHECK-NEXT: ret687 %load = call { <vscale x 1 x float>, i32 } @llvm.vp.load.ff.nxv1f32.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)688 ret { <vscale x 1 x float>, i32 } %load689}690 691define { <vscale x 2 x float>, i32 } @vploadff_nxv2f32(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {692; CHECK-LABEL: vploadff_nxv2f32:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma695; CHECK-NEXT: vle32ff.v v8, (a0), v0.t696; CHECK-NEXT: csrr a0, vl697; CHECK-NEXT: ret698 %load = call { <vscale x 2 x float>, i32 } @llvm.vp.load.ff.nxv2f32.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)699 ret { <vscale x 2 x float>, i32 } %load700}701 702define { <vscale x 2 x float>, i32 } @vploadff_nxv2f32_allones_mask(ptr %ptr, i32 zeroext %evl) {703; CHECK-LABEL: vploadff_nxv2f32_allones_mask:704; CHECK: # %bb.0:705; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma706; CHECK-NEXT: vle32ff.v v8, (a0)707; CHECK-NEXT: csrr a0, vl708; CHECK-NEXT: ret709 %load = call { <vscale x 2 x float>, i32 } @llvm.vp.load.ff.nxv2f32.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)710 ret { <vscale x 2 x float>, i32 } %load711}712 713define { <vscale x 4 x float>, i32 } @vploadff_nxv4f32(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {714; CHECK-LABEL: vploadff_nxv4f32:715; CHECK: # %bb.0:716; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma717; CHECK-NEXT: vle32ff.v v8, (a0), v0.t718; CHECK-NEXT: csrr a0, vl719; CHECK-NEXT: ret720 %load = call { <vscale x 4 x float>, i32 } @llvm.vp.load.ff.nxv4f32.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)721 ret { <vscale x 4 x float>, i32 } %load722}723 724define { <vscale x 4 x float>, i32 } @vploadff_nxv4f32_allones_mask(ptr %ptr, i32 zeroext %evl) {725; CHECK-LABEL: vploadff_nxv4f32_allones_mask:726; CHECK: # %bb.0:727; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma728; CHECK-NEXT: vle32ff.v v8, (a0)729; CHECK-NEXT: csrr a0, vl730; CHECK-NEXT: ret731 %load = call { <vscale x 4 x float>, i32 } @llvm.vp.load.ff.nxv4f32.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)732 ret { <vscale x 4 x float>, i32 } %load733}734 735define { <vscale x 8 x float>, i32 } @vploadff_nxv8f32(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vploadff_nxv8f32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma739; CHECK-NEXT: vle32ff.v v8, (a0), v0.t740; CHECK-NEXT: csrr a0, vl741; CHECK-NEXT: ret742 %load = call { <vscale x 8 x float>, i32 } @llvm.vp.load.ff.nxv8f32.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)743 ret { <vscale x 8 x float>, i32 } %load744}745 746define { <vscale x 8 x float>, i32 } @vploadff_nxv8f32_allones_mask(ptr %ptr, i32 zeroext %evl) {747; CHECK-LABEL: vploadff_nxv8f32_allones_mask:748; CHECK: # %bb.0:749; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma750; CHECK-NEXT: vle32ff.v v8, (a0)751; CHECK-NEXT: csrr a0, vl752; CHECK-NEXT: ret753 %load = call { <vscale x 8 x float>, i32 } @llvm.vp.load.ff.nxv8f32.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)754 ret { <vscale x 8 x float>, i32 } %load755}756 757define { <vscale x 16 x float>, i32 } @vploadff_nxv16f32(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {758; CHECK-LABEL: vploadff_nxv16f32:759; CHECK: # %bb.0:760; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma761; CHECK-NEXT: vle32ff.v v8, (a0), v0.t762; CHECK-NEXT: csrr a0, vl763; CHECK-NEXT: ret764 %load = call { <vscale x 16 x float>, i32 } @llvm.vp.load.ff.nxv16f32.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)765 ret { <vscale x 16 x float>, i32 } %load766}767 768define { <vscale x 16 x float>, i32 } @vploadff_nxv16f32_allones_mask(ptr %ptr, i32 zeroext %evl) {769; CHECK-LABEL: vploadff_nxv16f32_allones_mask:770; CHECK: # %bb.0:771; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma772; CHECK-NEXT: vle32ff.v v8, (a0)773; CHECK-NEXT: csrr a0, vl774; CHECK-NEXT: ret775 %load = call { <vscale x 16 x float>, i32 } @llvm.vp.load.ff.nxv16f32.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)776 ret { <vscale x 16 x float>, i32 } %load777}778 779define { <vscale x 1 x double>, i32 } @vploadff_nxv1f64(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {780; CHECK-LABEL: vploadff_nxv1f64:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma783; CHECK-NEXT: vle64ff.v v8, (a0), v0.t784; CHECK-NEXT: csrr a0, vl785; CHECK-NEXT: ret786 %load = call { <vscale x 1 x double>, i32 } @llvm.vp.load.ff.nxv1f64.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)787 ret { <vscale x 1 x double>, i32 } %load788}789 790define { <vscale x 1 x double>, i32 } @vploadff_nxv1f64_allones_mask(ptr %ptr, i32 zeroext %evl) {791; CHECK-LABEL: vploadff_nxv1f64_allones_mask:792; CHECK: # %bb.0:793; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma794; CHECK-NEXT: vle64ff.v v8, (a0)795; CHECK-NEXT: csrr a0, vl796; CHECK-NEXT: ret797 %load = call { <vscale x 1 x double>, i32 } @llvm.vp.load.ff.nxv1f64.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)798 ret { <vscale x 1 x double>, i32 } %load799}800 801define { <vscale x 2 x double>, i32 } @vploadff_nxv2f64(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {802; CHECK-LABEL: vploadff_nxv2f64:803; CHECK: # %bb.0:804; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma805; CHECK-NEXT: vle64ff.v v8, (a0), v0.t806; CHECK-NEXT: csrr a0, vl807; CHECK-NEXT: ret808 %load = call { <vscale x 2 x double>, i32 } @llvm.vp.load.ff.nxv2f64.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)809 ret { <vscale x 2 x double>, i32 } %load810}811 812define { <vscale x 2 x double>, i32 } @vploadff_nxv2f64_allones_mask(ptr %ptr, i32 zeroext %evl) {813; CHECK-LABEL: vploadff_nxv2f64_allones_mask:814; CHECK: # %bb.0:815; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma816; CHECK-NEXT: vle64ff.v v8, (a0)817; CHECK-NEXT: csrr a0, vl818; CHECK-NEXT: ret819 %load = call { <vscale x 2 x double>, i32 } @llvm.vp.load.ff.nxv2f64.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)820 ret { <vscale x 2 x double>, i32 } %load821}822 823define { <vscale x 4 x double>, i32 } @vploadff_nxv4f64(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {824; CHECK-LABEL: vploadff_nxv4f64:825; CHECK: # %bb.0:826; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma827; CHECK-NEXT: vle64ff.v v8, (a0), v0.t828; CHECK-NEXT: csrr a0, vl829; CHECK-NEXT: ret830 %load = call { <vscale x 4 x double>, i32 } @llvm.vp.load.ff.nxv4f64.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)831 ret { <vscale x 4 x double>, i32 } %load832}833 834define { <vscale x 4 x double>, i32 } @vploadff_nxv4f64_allones_mask(ptr %ptr, i32 zeroext %evl) {835; CHECK-LABEL: vploadff_nxv4f64_allones_mask:836; CHECK: # %bb.0:837; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma838; CHECK-NEXT: vle64ff.v v8, (a0)839; CHECK-NEXT: csrr a0, vl840; CHECK-NEXT: ret841 %load = call { <vscale x 4 x double>, i32 } @llvm.vp.load.ff.nxv4f64.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)842 ret { <vscale x 4 x double>, i32 } %load843}844 845define { <vscale x 8 x double>, i32 } @vploadff_nxv8f64(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {846; CHECK-LABEL: vploadff_nxv8f64:847; CHECK: # %bb.0:848; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma849; CHECK-NEXT: vle64ff.v v8, (a0), v0.t850; CHECK-NEXT: csrr a0, vl851; CHECK-NEXT: ret852 %load = call { <vscale x 8 x double>, i32 } @llvm.vp.load.ff.nxv8f64.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)853 ret { <vscale x 8 x double>, i32 } %load854}855 856define { <vscale x 8 x double>, i32 } @vploadff_nxv8f64_allones_mask(ptr %ptr, i32 zeroext %evl) {857; CHECK-LABEL: vploadff_nxv8f64_allones_mask:858; CHECK: # %bb.0:859; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma860; CHECK-NEXT: vle64ff.v v8, (a0)861; CHECK-NEXT: csrr a0, vl862; CHECK-NEXT: ret863 %load = call { <vscale x 8 x double>, i32 } @llvm.vp.load.ff.nxv8f64.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)864 ret { <vscale x 8 x double>, i32 } %load865}866 867define { <vscale x 1 x bfloat>, i32 } @vploadff_nxv1bf16(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {868; CHECK-LABEL: vploadff_nxv1bf16:869; CHECK: # %bb.0:870; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma871; CHECK-NEXT: vle16ff.v v8, (a0), v0.t872; CHECK-NEXT: csrr a0, vl873; CHECK-NEXT: ret874 %load = call { <vscale x 1 x bfloat>, i32 } @llvm.vp.load.ff.nxv1bf16.p0(ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)875 ret { <vscale x 1 x bfloat>, i32 } %load876}877 878define { <vscale x 1 x bfloat>, i32 } @vploadff_nxv1bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {879; CHECK-LABEL: vploadff_nxv1bf16_allones_mask:880; CHECK: # %bb.0:881; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma882; CHECK-NEXT: vle16ff.v v8, (a0)883; CHECK-NEXT: csrr a0, vl884; CHECK-NEXT: ret885 %load = call { <vscale x 1 x bfloat>, i32 } @llvm.vp.load.ff.nxv1bf16.p0(ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)886 ret { <vscale x 1 x bfloat>, i32 } %load887}888 889define { <vscale x 2 x bfloat>, i32 } @vploadff_nxv2bf16(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {890; CHECK-LABEL: vploadff_nxv2bf16:891; CHECK: # %bb.0:892; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma893; CHECK-NEXT: vle16ff.v v8, (a0), v0.t894; CHECK-NEXT: csrr a0, vl895; CHECK-NEXT: ret896 %load = call { <vscale x 2 x bfloat>, i32 } @llvm.vp.load.ff.nxv2bf16.p0(ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)897 ret { <vscale x 2 x bfloat>, i32 } %load898}899 900define { <vscale x 2 x bfloat>, i32 } @vploadff_nxv2bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {901; CHECK-LABEL: vploadff_nxv2bf16_allones_mask:902; CHECK: # %bb.0:903; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma904; CHECK-NEXT: vle16ff.v v8, (a0)905; CHECK-NEXT: csrr a0, vl906; CHECK-NEXT: ret907 %load = call { <vscale x 2 x bfloat>, i32 } @llvm.vp.load.ff.nxv2bf16.p0(ptr %ptr, <vscale x 2 x i1> splat (i1 true), i32 %evl)908 ret { <vscale x 2 x bfloat>, i32 } %load909}910 911define { <vscale x 4 x bfloat>, i32 } @vploadff_nxv4bf16(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {912; CHECK-LABEL: vploadff_nxv4bf16:913; CHECK: # %bb.0:914; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma915; CHECK-NEXT: vle16ff.v v8, (a0), v0.t916; CHECK-NEXT: csrr a0, vl917; CHECK-NEXT: ret918 %load = call { <vscale x 4 x bfloat>, i32 } @llvm.vp.load.ff.nxv4bf16.p0(ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)919 ret { <vscale x 4 x bfloat>, i32 } %load920}921 922define { <vscale x 4 x bfloat>, i32 } @vploadff_nxv4bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {923; CHECK-LABEL: vploadff_nxv4bf16_allones_mask:924; CHECK: # %bb.0:925; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma926; CHECK-NEXT: vle16ff.v v8, (a0)927; CHECK-NEXT: csrr a0, vl928; CHECK-NEXT: ret929 %load = call { <vscale x 4 x bfloat>, i32 } @llvm.vp.load.ff.nxv4bf16.p0(ptr %ptr, <vscale x 4 x i1> splat (i1 true), i32 %evl)930 ret { <vscale x 4 x bfloat>, i32 } %load931}932 933define { <vscale x 8 x bfloat>, i32 } @vploadff_nxv8bf16(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {934; CHECK-LABEL: vploadff_nxv8bf16:935; CHECK: # %bb.0:936; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma937; CHECK-NEXT: vle16ff.v v8, (a0), v0.t938; CHECK-NEXT: csrr a0, vl939; CHECK-NEXT: ret940 %load = call { <vscale x 8 x bfloat>, i32 } @llvm.vp.load.ff.nxv8bf16.p0(ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)941 ret { <vscale x 8 x bfloat>, i32 } %load942}943 944define { <vscale x 8 x bfloat>, i32 } @vploadff_nxv8bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {945; CHECK-LABEL: vploadff_nxv8bf16_allones_mask:946; CHECK: # %bb.0:947; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma948; CHECK-NEXT: vle16ff.v v8, (a0)949; CHECK-NEXT: csrr a0, vl950; CHECK-NEXT: ret951 %load = call { <vscale x 8 x bfloat>, i32 } @llvm.vp.load.ff.nxv8bf16.p0(ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)952 ret { <vscale x 8 x bfloat>, i32 } %load953}954 955define { <vscale x 16 x bfloat>, i32 } @vploadff_nxv16bf16(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {956; CHECK-LABEL: vploadff_nxv16bf16:957; CHECK: # %bb.0:958; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma959; CHECK-NEXT: vle16ff.v v8, (a0), v0.t960; CHECK-NEXT: csrr a0, vl961; CHECK-NEXT: ret962 %load = call { <vscale x 16 x bfloat>, i32 } @llvm.vp.load.ff.nxv16bf16.p0(ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)963 ret { <vscale x 16 x bfloat>, i32 } %load964}965 966define { <vscale x 16 x bfloat>, i32 } @vploadff_nxv16bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {967; CHECK-LABEL: vploadff_nxv16bf16_allones_mask:968; CHECK: # %bb.0:969; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma970; CHECK-NEXT: vle16ff.v v8, (a0)971; CHECK-NEXT: csrr a0, vl972; CHECK-NEXT: ret973 %load = call { <vscale x 16 x bfloat>, i32 } @llvm.vp.load.ff.nxv16bf16.p0(ptr %ptr, <vscale x 16 x i1> splat (i1 true), i32 %evl)974 ret { <vscale x 16 x bfloat>, i32 } %load975}976 977define { <vscale x 32 x bfloat>, i32 } @vploadff_nxv32bf16(ptr %ptr, <vscale x 32 x i1> %m, i32 zeroext %evl) {978; CHECK-LABEL: vploadff_nxv32bf16:979; CHECK: # %bb.0:980; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma981; CHECK-NEXT: vle16ff.v v8, (a0), v0.t982; CHECK-NEXT: csrr a0, vl983; CHECK-NEXT: ret984 %load = call { <vscale x 32 x bfloat>, i32 } @llvm.vp.load.ff.nxv32bf16.p0(ptr %ptr, <vscale x 32 x i1> %m, i32 %evl)985 ret { <vscale x 32 x bfloat>, i32 } %load986}987 988define { <vscale x 32 x bfloat>, i32 } @vploadff_nxv32bf16_allones_mask(ptr %ptr, i32 zeroext %evl) {989; CHECK-LABEL: vploadff_nxv32bf16_allones_mask:990; CHECK: # %bb.0:991; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma992; CHECK-NEXT: vle16ff.v v8, (a0)993; CHECK-NEXT: csrr a0, vl994; CHECK-NEXT: ret995 %load = call { <vscale x 32 x bfloat>, i32 } @llvm.vp.load.ff.nxv32bf16.p0(ptr %ptr, <vscale x 32 x i1> splat (i1 true), i32 %evl)996 ret { <vscale x 32 x bfloat>, i32 } %load997}998 999define { <vscale x 3 x i8>, i32 } @vploadff_nxv3i8(ptr %ptr, <vscale x 3 x i1> %m, i32 zeroext %evl) {1000; CHECK-LABEL: vploadff_nxv3i8:1001; CHECK: # %bb.0:1002; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1003; CHECK-NEXT: vle8ff.v v8, (a0), v0.t1004; CHECK-NEXT: csrr a0, vl1005; CHECK-NEXT: ret1006 %load = call { <vscale x 3 x i8>, i32 } @llvm.vp.load.ff.nxv3i8.p0(ptr %ptr, <vscale x 3 x i1> %m, i32 %evl)1007 ret { <vscale x 3 x i8>, i32 } %load1008}1009