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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define void @vpstore_nxv1i8(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vpstore_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma15; CHECK-NEXT: vse8.v v8, (a0), v0.t16; CHECK-NEXT: ret17 call void @llvm.vp.store.nxv1i8.p0(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)18 ret void19}20 21define void @vpstore_nxv2i8(<vscale x 2 x i8> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {22; CHECK-LABEL: vpstore_nxv2i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma25; CHECK-NEXT: vse8.v v8, (a0), v0.t26; CHECK-NEXT: ret27 call void @llvm.vp.store.nxv2i8.p0(<vscale x 2 x i8> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)28 ret void29}30 31define void @vpstore_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr, <vscale x 3 x i1> %m, i32 zeroext %evl) {32; CHECK-LABEL: vpstore_nxv3i8:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma35; CHECK-NEXT: vse8.v v8, (a0), v0.t36; CHECK-NEXT: ret37 call void @llvm.vp.store.nxv3i8.p0(<vscale x 3 x i8> %val, ptr %ptr, <vscale x 3 x i1> %m, i32 %evl)38 ret void39}40 41define void @vpstore_nxv4i8(<vscale x 4 x i8> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {42; CHECK-LABEL: vpstore_nxv4i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma45; CHECK-NEXT: vse8.v v8, (a0), v0.t46; CHECK-NEXT: ret47 call void @llvm.vp.store.nxv4i8.p0(<vscale x 4 x i8> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)48 ret void49}50 51define void @vpstore_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vpstore_nxv8i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma55; CHECK-NEXT: vse8.v v8, (a0), v0.t56; CHECK-NEXT: ret57 call void @llvm.vp.store.nxv8i8.p0(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)58 ret void59}60 61define void @vpstore_nxv1i16(<vscale x 1 x i16> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {62; CHECK-LABEL: vpstore_nxv1i16:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma65; CHECK-NEXT: vse16.v v8, (a0), v0.t66; CHECK-NEXT: ret67 call void @llvm.vp.store.nxv1i16.p0(<vscale x 1 x i16> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)68 ret void69}70 71define void @vpstore_nxv2i16(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: vpstore_nxv2i16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma75; CHECK-NEXT: vse16.v v8, (a0), v0.t76; CHECK-NEXT: ret77 call void @llvm.vp.store.nxv2i16.p0(<vscale x 2 x i16> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)78 ret void79}80 81define void @vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {82; CHECK-LABEL: vpstore_nxv4i16:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma85; CHECK-NEXT: vse16.v v8, (a0), v0.t86; CHECK-NEXT: ret87 call void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)88 ret void89}90 91define void @vpstore_nxv8i12(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: vpstore_nxv8i12:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma95; CHECK-NEXT: vse16.v v8, (a0), v0.t96; CHECK-NEXT: ret97 call void @llvm.vp.store.nxv8i12.nxv8i12.p0(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 %evl)98 ret void99}100 101define void @vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: vpstore_nxv8i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma105; CHECK-NEXT: vse16.v v8, (a0), v0.t106; CHECK-NEXT: ret107 call void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)108 ret void109}110 111define void @vpstore_nxv1i32(<vscale x 1 x i32> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vpstore_nxv1i32:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma115; CHECK-NEXT: vse32.v v8, (a0), v0.t116; CHECK-NEXT: ret117 call void @llvm.vp.store.nxv1i32.p0(<vscale x 1 x i32> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)118 ret void119}120 121define void @vpstore_nxv2i32(<vscale x 2 x i32> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vpstore_nxv2i32:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma125; CHECK-NEXT: vse32.v v8, (a0), v0.t126; CHECK-NEXT: ret127 call void @llvm.vp.store.nxv2i32.p0(<vscale x 2 x i32> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)128 ret void129}130 131define void @vpstore_nxv4i32(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {132; CHECK-LABEL: vpstore_nxv4i32:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma135; CHECK-NEXT: vse32.v v8, (a0), v0.t136; CHECK-NEXT: ret137 call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)138 ret void139}140 141define void @vpstore_nxv8i32(<vscale x 8 x i32> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {142; CHECK-LABEL: vpstore_nxv8i32:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma145; CHECK-NEXT: vse32.v v8, (a0), v0.t146; CHECK-NEXT: ret147 call void @llvm.vp.store.nxv8i32.p0(<vscale x 8 x i32> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)148 ret void149}150 151define void @vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {152; CHECK-LABEL: vpstore_nxv1i64:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma155; CHECK-NEXT: vse64.v v8, (a0), v0.t156; CHECK-NEXT: ret157 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)158 ret void159}160 161define void @vpstore_nxv2i64(<vscale x 2 x i64> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: vpstore_nxv2i64:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma165; CHECK-NEXT: vse64.v v8, (a0), v0.t166; CHECK-NEXT: ret167 call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)168 ret void169}170 171define void @vpstore_nxv4i64(<vscale x 4 x i64> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: vpstore_nxv4i64:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma175; CHECK-NEXT: vse64.v v8, (a0), v0.t176; CHECK-NEXT: ret177 call void @llvm.vp.store.nxv4i64.p0(<vscale x 4 x i64> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)178 ret void179}180 181define void @vpstore_nxv8i64(<vscale x 8 x i64> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {182; CHECK-LABEL: vpstore_nxv8i64:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma185; CHECK-NEXT: vse64.v v8, (a0), v0.t186; CHECK-NEXT: ret187 call void @llvm.vp.store.nxv8i64.p0(<vscale x 8 x i64> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)188 ret void189}190 191define void @vpstore_nxv1bf16(<vscale x 1 x bfloat> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: vpstore_nxv1bf16:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma195; CHECK-NEXT: vse16.v v8, (a0), v0.t196; CHECK-NEXT: ret197 call void @llvm.vp.store.nxv1bf16.p0(<vscale x 1 x bfloat> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)198 ret void199}200 201define void @vpstore_nxv2bf16(<vscale x 2 x bfloat> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {202; CHECK-LABEL: vpstore_nxv2bf16:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma205; CHECK-NEXT: vse16.v v8, (a0), v0.t206; CHECK-NEXT: ret207 call void @llvm.vp.store.nxv2bf16.p0(<vscale x 2 x bfloat> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)208 ret void209}210 211define void @vpstore_nxv4bf16(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {212; CHECK-LABEL: vpstore_nxv4bf16:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma215; CHECK-NEXT: vse16.v v8, (a0), v0.t216; CHECK-NEXT: ret217 call void @llvm.vp.store.nxv4bf16.p0(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)218 ret void219}220 221define void @vpstore_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {222; CHECK-LABEL: vpstore_nxv8bf16:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma225; CHECK-NEXT: vse16.v v8, (a0), v0.t226; CHECK-NEXT: ret227 call void @llvm.vp.store.nxv8bf16.p0(<vscale x 8 x bfloat> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)228 ret void229}230 231define void @vpstore_nxv1f16(<vscale x 1 x half> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vpstore_nxv1f16:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma235; CHECK-NEXT: vse16.v v8, (a0), v0.t236; CHECK-NEXT: ret237 call void @llvm.vp.store.nxv1f16.p0(<vscale x 1 x half> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)238 ret void239}240 241define void @vpstore_nxv2f16(<vscale x 2 x half> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {242; CHECK-LABEL: vpstore_nxv2f16:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma245; CHECK-NEXT: vse16.v v8, (a0), v0.t246; CHECK-NEXT: ret247 call void @llvm.vp.store.nxv2f16.p0(<vscale x 2 x half> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)248 ret void249}250 251define void @vpstore_nxv4f16(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vpstore_nxv4f16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma255; CHECK-NEXT: vse16.v v8, (a0), v0.t256; CHECK-NEXT: ret257 call void @llvm.vp.store.nxv4f16.p0(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)258 ret void259}260 261define void @vpstore_nxv8f16(<vscale x 8 x half> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {262; CHECK-LABEL: vpstore_nxv8f16:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma265; CHECK-NEXT: vse16.v v8, (a0), v0.t266; CHECK-NEXT: ret267 call void @llvm.vp.store.nxv8f16.p0(<vscale x 8 x half> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)268 ret void269}270 271define void @vpstore_nxv1f32(<vscale x 1 x float> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vpstore_nxv1f32:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma275; CHECK-NEXT: vse32.v v8, (a0), v0.t276; CHECK-NEXT: ret277 call void @llvm.vp.store.nxv1f32.p0(<vscale x 1 x float> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)278 ret void279}280 281define void @vpstore_nxv2f32(<vscale x 2 x float> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {282; CHECK-LABEL: vpstore_nxv2f32:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma285; CHECK-NEXT: vse32.v v8, (a0), v0.t286; CHECK-NEXT: ret287 call void @llvm.vp.store.nxv2f32.p0(<vscale x 2 x float> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)288 ret void289}290 291define void @vpstore_nxv4f32(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {292; CHECK-LABEL: vpstore_nxv4f32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma295; CHECK-NEXT: vse32.v v8, (a0), v0.t296; CHECK-NEXT: ret297 call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)298 ret void299}300 301define void @vpstore_nxv8f32(<vscale x 8 x float> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {302; CHECK-LABEL: vpstore_nxv8f32:303; CHECK: # %bb.0:304; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma305; CHECK-NEXT: vse32.v v8, (a0), v0.t306; CHECK-NEXT: ret307 call void @llvm.vp.store.nxv8f32.p0(<vscale x 8 x float> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)308 ret void309}310 311define void @vpstore_nxv1f64(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {312; CHECK-LABEL: vpstore_nxv1f64:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma315; CHECK-NEXT: vse64.v v8, (a0), v0.t316; CHECK-NEXT: ret317 call void @llvm.vp.store.nxv1f64.p0(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 %evl)318 ret void319}320 321define void @vpstore_nxv2f64(<vscale x 2 x double> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {322; CHECK-LABEL: vpstore_nxv2f64:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma325; CHECK-NEXT: vse64.v v8, (a0), v0.t326; CHECK-NEXT: ret327 call void @llvm.vp.store.nxv2f64.p0(<vscale x 2 x double> %val, ptr %ptr, <vscale x 2 x i1> %m, i32 %evl)328 ret void329}330 331define void @vpstore_nxv4f64(<vscale x 4 x double> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vpstore_nxv4f64:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma335; CHECK-NEXT: vse64.v v8, (a0), v0.t336; CHECK-NEXT: ret337 call void @llvm.vp.store.nxv4f64.p0(<vscale x 4 x double> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 %evl)338 ret void339}340 341define void @vpstore_nxv8f64(<vscale x 8 x double> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {342; CHECK-LABEL: vpstore_nxv8f64:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma345; CHECK-NEXT: vse64.v v8, (a0), v0.t346; CHECK-NEXT: ret347 call void @llvm.vp.store.nxv8f64.p0(<vscale x 8 x double> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 %evl)348 ret void349}350 351define void @vpstore_nxv1i8_allones_mask(<vscale x 1 x i8> %val, ptr %ptr, i32 zeroext %evl) {352; CHECK-LABEL: vpstore_nxv1i8_allones_mask:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma355; CHECK-NEXT: vse8.v v8, (a0)356; CHECK-NEXT: ret357 call void @llvm.vp.store.nxv1i8.p0(<vscale x 1 x i8> %val, ptr %ptr, <vscale x 1 x i1> splat (i1 true), i32 %evl)358 ret void359}360 361define void @vpstore_nxv16f64(<vscale x 16 x double> %val, ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {362; CHECK-LABEL: vpstore_nxv16f64:363; CHECK: # %bb.0:364; CHECK-NEXT: csrr a2, vlenb365; CHECK-NEXT: mv a3, a1366; CHECK-NEXT: bltu a1, a2, .LBB35_2367; CHECK-NEXT: # %bb.1:368; CHECK-NEXT: mv a3, a2369; CHECK-NEXT: .LBB35_2:370; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma371; CHECK-NEXT: vse64.v v8, (a0), v0.t372; CHECK-NEXT: srli a3, a2, 3373; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma374; CHECK-NEXT: vslidedown.vx v0, v0, a3375; CHECK-NEXT: sub a3, a1, a2376; CHECK-NEXT: slli a2, a2, 3377; CHECK-NEXT: sltu a1, a1, a3378; CHECK-NEXT: addi a1, a1, -1379; CHECK-NEXT: and a1, a1, a3380; CHECK-NEXT: add a0, a0, a2381; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma382; CHECK-NEXT: vse64.v v16, (a0), v0.t383; CHECK-NEXT: ret384 call void @llvm.vp.store.nxv16f64.p0(<vscale x 16 x double> %val, ptr %ptr, <vscale x 16 x i1> %m, i32 %evl)385 ret void386}387 388; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty.389 390define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 17 x i1> %m, i32 zeroext %evl) {391; CHECK-LABEL: vpstore_nxv17f64:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma394; CHECK-NEXT: vmv1r.v v7, v0395; CHECK-NEXT: csrr a3, vlenb396; CHECK-NEXT: slli a4, a3, 1397; CHECK-NEXT: mv a5, a2398; CHECK-NEXT: bltu a2, a4, .LBB36_2399; CHECK-NEXT: # %bb.1:400; CHECK-NEXT: mv a5, a4401; CHECK-NEXT: .LBB36_2:402; CHECK-NEXT: mv a6, a5403; CHECK-NEXT: bltu a5, a3, .LBB36_4404; CHECK-NEXT: # %bb.3:405; CHECK-NEXT: mv a6, a3406; CHECK-NEXT: .LBB36_4:407; CHECK-NEXT: vmv1r.v v0, v7408; CHECK-NEXT: vl8re64.v v24, (a0)409; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma410; CHECK-NEXT: vse64.v v8, (a1), v0.t411; CHECK-NEXT: sub a0, a5, a3412; CHECK-NEXT: srli a6, a3, 3413; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma414; CHECK-NEXT: vslidedown.vx v0, v7, a6415; CHECK-NEXT: slli a6, a3, 3416; CHECK-NEXT: sub a4, a2, a4417; CHECK-NEXT: sltu a5, a5, a0418; CHECK-NEXT: add a6, a1, a6419; CHECK-NEXT: sltu a2, a2, a4420; CHECK-NEXT: addi a5, a5, -1421; CHECK-NEXT: addi a2, a2, -1422; CHECK-NEXT: and a5, a5, a0423; CHECK-NEXT: and a0, a2, a4424; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma425; CHECK-NEXT: vse64.v v16, (a6), v0.t426; CHECK-NEXT: bltu a0, a3, .LBB36_6427; CHECK-NEXT: # %bb.5:428; CHECK-NEXT: mv a0, a3429; CHECK-NEXT: .LBB36_6:430; CHECK-NEXT: slli a2, a3, 4431; CHECK-NEXT: srli a3, a3, 2432; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma433; CHECK-NEXT: vslidedown.vx v0, v7, a3434; CHECK-NEXT: add a1, a1, a2435; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma436; CHECK-NEXT: vse64.v v24, (a1), v0.t437; CHECK-NEXT: ret438 call void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double> %val, ptr %ptr, <vscale x 17 x i1> %m, i32 %evl)439 ret void440}441 442define void @unaligned_vpstore_nxv1i64_allones_mask(<vscale x 1 x i64> %val, <vscale x 1 x i64>* %ptr, i32 zeroext %evl) {443; CHECK-LABEL: unaligned_vpstore_nxv1i64_allones_mask:444; CHECK: # %bb.0:445; CHECK-NEXT: slli a1, a1, 3446; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma447; CHECK-NEXT: vse8.v v8, (a0)448; CHECK-NEXT: ret449 %a = insertelement <vscale x 1 x i1> poison, i1 true, i32 0450 %b = shufflevector <vscale x 1 x i1> %a, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer451 call void @llvm.vp.store.nxv1i64.p0(<vscale x 1 x i64> %val, <vscale x 1 x i64>* align 1 %ptr, <vscale x 1 x i1> %b, i32 %evl)452 ret void453}454 455define void @vpstore_all_active_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr) {456; CHECK-LABEL: vpstore_all_active_nxv8i8:457; CHECK: # %bb.0:458; CHECK-NEXT: vs1r.v v8, (a0)459; CHECK-NEXT: ret460 %vscale = call i32 @llvm.vscale()461 %evl = mul i32 %vscale, 8462 call void @llvm.vp.store.nxv8i8.p0(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> splat (i1 true), i32 %evl)463 ret void464}465