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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i32> @intrinsic_vqdotsu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv1i32_nxv1i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma11; CHECK-NEXT: vqdotsu.vv v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.nxv1i32(15 <vscale x 1 x i32> %0,16 <vscale x 4 x i8> %1,17 <vscale x 4 x i8> %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i32> %a21}22 23define <vscale x 2 x i32> @intrinsic_vqdotsu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv2i32_nxv2i32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma27; CHECK-NEXT: vqdotsu.vv v8, v9, v1028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.nxv2i32(31 <vscale x 2 x i32> %0,32 <vscale x 8 x i8> %1,33 <vscale x 8 x i8> %2,34 iXLen %3, iXLen 0)35 36 ret <vscale x 2 x i32> %a37}38 39define <vscale x 4 x i32> @intrinsic_vqdotsu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv4i32_nxv4i32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma43; CHECK-NEXT: vqdotsu.vv v8, v10, v1244; CHECK-NEXT: ret45entry:46 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.nxv4i32(47 <vscale x 4 x i32> %0,48 <vscale x 16 x i8> %1,49 <vscale x 16 x i8> %2,50 iXLen %3, iXLen 0)51 52 ret <vscale x 4 x i32> %a53}54 55define <vscale x 8 x i32> @intrinsic_vqdotsu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv8i32_nxv8i32:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma59; CHECK-NEXT: vqdotsu.vv v8, v12, v1660; CHECK-NEXT: ret61entry:62 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.nxv8i32(63 <vscale x 8 x i32> %0,64 <vscale x 32 x i8> %1,65 <vscale x 32 x i8> %2,66 iXLen %3, iXLen 0)67 68 ret <vscale x 8 x i32> %a69}70 71define <vscale x 16 x i32> @intrinsic_vqdotsu_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vqdotsu_vv_nxv16i32_nxv16i32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vl8r.v v24, (a0)75; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma76; CHECK-NEXT: vqdotsu.vv v8, v16, v2477; CHECK-NEXT: ret78entry:79 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.nxv16i32(80 <vscale x 16 x i32> %0,81 <vscale x 64 x i8> %1,82 <vscale x 64 x i8> %2,83 iXLen %3, iXLen 0)84 85 ret <vscale x 16 x i32> %a86}87 88define <vscale x 1 x i32> @intrinsic_vqdotsu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {89; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv1i32_nxv1i32:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu92; CHECK-NEXT: vqdotsu.vv v8, v9, v10, v0.t93; CHECK-NEXT: ret94entry:95 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.nxv1i32(96 <vscale x 1 x i32> %0,97 <vscale x 4 x i8> %1,98 <vscale x 4 x i8> %2,99 <vscale x 1 x i1> %m,100 iXLen %3, iXLen 0)101 102 ret <vscale x 1 x i32> %a103}104 105define <vscale x 2 x i32> @intrinsic_vqdotsu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {106; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv2i32_nxv2i32:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu109; CHECK-NEXT: vqdotsu.vv v8, v9, v10, v0.t110; CHECK-NEXT: ret111entry:112 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.nxv2i32(113 <vscale x 2 x i32> %0,114 <vscale x 8 x i8> %1,115 <vscale x 8 x i8> %2,116 <vscale x 2 x i1> %m,117 iXLen %3, iXLen 0)118 119 ret <vscale x 2 x i32> %a120}121 122define <vscale x 4 x i32> @intrinsic_vqdotsu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {123; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv4i32_nxv4i32:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu126; CHECK-NEXT: vqdotsu.vv v8, v10, v12, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.nxv4i32(130 <vscale x 4 x i32> %0,131 <vscale x 16 x i8> %1,132 <vscale x 16 x i8> %2,133 <vscale x 4 x i1> %m,134 iXLen %3, iXLen 0)135 136 ret <vscale x 4 x i32> %a137}138 139define <vscale x 8 x i32> @intrinsic_vqdotsu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv8i32_nxv8i32:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu143; CHECK-NEXT: vqdotsu.vv v8, v12, v16, v0.t144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.nxv8i32(147 <vscale x 8 x i32> %0,148 <vscale x 32 x i8> %1,149 <vscale x 32 x i8> %2,150 <vscale x 8 x i1> %m,151 iXLen %3, iXLen 0)152 153 ret <vscale x 8 x i32> %a154}155 156define <vscale x 16 x i32> @intrinsic_vqdotsu_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {157; CHECK-LABEL: intrinsic_vqdotsu_mask_vv_nxv16i32_nxv16i32:158; CHECK: # %bb.0: # %entry159; CHECK-NEXT: vl8r.v v24, (a0)160; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu161; CHECK-NEXT: vqdotsu.vv v8, v16, v24, v0.t162; CHECK-NEXT: ret163entry:164 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.nxv16i32(165 <vscale x 16 x i32> %0,166 <vscale x 64 x i8> %1,167 <vscale x 64 x i8> %2,168 <vscale x 16 x i1> %m,169 iXLen %3, iXLen 0)170 171 ret <vscale x 16 x i32> %a172}173 174define <vscale x 1 x i32> @intrinsic_vqdotsu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {175; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv1i32_i32:176; CHECK: # %bb.0: # %entry177; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma178; CHECK-NEXT: vqdotsu.vx v8, v9, a0179; CHECK-NEXT: ret180entry:181 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.nxv1i32.i32(182 <vscale x 1 x i32> %0,183 <vscale x 4 x i8> %1,184 i32 %2,185 iXLen %3, iXLen 0)186 187 ret <vscale x 1 x i32> %a188}189 190define <vscale x 2 x i32> @intrinsic_vqdotsu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {191; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv2i32_i32:192; CHECK: # %bb.0: # %entry193; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma194; CHECK-NEXT: vqdotsu.vx v8, v9, a0195; CHECK-NEXT: ret196entry:197 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.nxv2i32.i32(198 <vscale x 2 x i32> %0,199 <vscale x 8 x i8> %1,200 i32 %2,201 iXLen %3, iXLen 0)202 203 ret <vscale x 2 x i32> %a204}205 206define <vscale x 4 x i32> @intrinsic_vqdotsu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {207; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv4i32_i32:208; CHECK: # %bb.0: # %entry209; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma210; CHECK-NEXT: vqdotsu.vx v8, v10, a0211; CHECK-NEXT: ret212entry:213 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.nxv4i32.i32(214 <vscale x 4 x i32> %0,215 <vscale x 16 x i8> %1,216 i32 %2,217 iXLen %3, iXLen 0)218 219 ret <vscale x 4 x i32> %a220}221 222define <vscale x 8 x i32> @intrinsic_vqdotsu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {223; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv8i32_i32:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma226; CHECK-NEXT: vqdotsu.vx v8, v12, a0227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.nxv8i32.i32(230 <vscale x 8 x i32> %0,231 <vscale x 32 x i8> %1,232 i32 %2,233 iXLen %3, iXLen 0)234 235 ret <vscale x 8 x i32> %a236}237 238define <vscale x 16 x i32> @intrinsic_vqdotsu_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vqdotsu_vx_nxv16i32_i32:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma242; CHECK-NEXT: vqdotsu.vx v8, v16, a0243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.nxv16i32.i32(246 <vscale x 16 x i32> %0,247 <vscale x 64 x i8> %1,248 i32 %2,249 iXLen %3, iXLen 0)250 251 ret <vscale x 16 x i32> %a252}253 254define <vscale x 1 x i32> @intrinsic_vqdotsu_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {255; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv1i32_i32:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu258; CHECK-NEXT: vqdotsu.vx v8, v9, a0, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotsu.mask.nxv1i32.i32(262 <vscale x 1 x i32> %0,263 <vscale x 4 x i8> %1,264 i32 %2,265 <vscale x 1 x i1> %m,266 iXLen %3, iXLen 0)267 268 ret <vscale x 1 x i32> %a269}270 271define <vscale x 2 x i32> @intrinsic_vqdotsu_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv2i32_i32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu275; CHECK-NEXT: vqdotsu.vx v8, v9, a0, v0.t276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotsu.mask.nxv2i32.i32(279 <vscale x 2 x i32> %0,280 <vscale x 8 x i8> %1,281 i32 %2,282 <vscale x 2 x i1> %m,283 iXLen %3, iXLen 0)284 285 ret <vscale x 2 x i32> %a286}287 288define <vscale x 4 x i32> @intrinsic_vqdotsu_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {289; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv4i32_i32:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu292; CHECK-NEXT: vqdotsu.vx v8, v10, a0, v0.t293; CHECK-NEXT: ret294entry:295 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotsu.mask.nxv4i32.i32(296 <vscale x 4 x i32> %0,297 <vscale x 16 x i8> %1,298 i32 %2,299 <vscale x 4 x i1> %m,300 iXLen %3, iXLen 0)301 302 ret <vscale x 4 x i32> %a303}304 305define <vscale x 8 x i32> @intrinsic_vqdotsu_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {306; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv8i32_i32:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu309; CHECK-NEXT: vqdotsu.vx v8, v12, a0, v0.t310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotsu.mask.nxv8i32.i32(313 <vscale x 8 x i32> %0,314 <vscale x 32 x i8> %1,315 i32 %2,316 <vscale x 8 x i1> %m,317 iXLen %3, iXLen 0)318 319 ret <vscale x 8 x i32> %a320}321 322define <vscale x 16 x i32> @intrinsic_vqdotsu_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {323; CHECK-LABEL: intrinsic_vqdotsu_mask_vx_nxv16i32_i32:324; CHECK: # %bb.0: # %entry325; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu326; CHECK-NEXT: vqdotsu.vx v8, v16, a0, v0.t327; CHECK-NEXT: ret328entry:329 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotsu.mask.nxv16i32.i32(330 <vscale x 16 x i32> %0,331 <vscale x 64 x i8> %1,332 i32 %2,333 <vscale x 16 x i1> %m,334 iXLen %3, iXLen 0)335 336 ret <vscale x 16 x i32> %a337}338